drivers/gpu/drm/zte/zx_vou.c

   1 /*
   2  * Copyright 2016 Linaro Ltd.
   3  * Copyright 2016 ZTE Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/component.h>
  13 #include <linux/of_address.h>
  14 #include <video/videomode.h>
  15
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_crtc.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_fb_cma_helper.h>
  20 #include <drm/drm_fb_helper.h>
  21 #include <drm/drm_gem_cma_helper.h>
  22 #include <drm/drm_of.h>
  23 #include <drm/drm_plane_helper.h>
  24 #include <drm/drmP.h>
  25
  26 #include "zx_common_regs.h"
  27 #include "zx_drm_drv.h"
  28 #include "zx_plane.h"
  29 #include "zx_vou.h"
  30 #include "zx_vou_regs.h"
  31
  32 #define GL_NUM  2
  33 #define VL_NUM  3
  34
  35 enum vou_chn_type {
  36         VOU_CHN_MAIN,
  37         VOU_CHN_AUX,
  38 };
  39
  40 struct zx_crtc_regs {
  41         u32 fir_active;
  42         u32 fir_htiming;
  43         u32 fir_vtiming;
  44         u32 sec_vtiming;
  45         u32 timing_shift;
  46         u32 timing_pi_shift;
  47 };
  48
  49 static const struct zx_crtc_regs main_crtc_regs = {
  50         .fir_active = FIR_MAIN_ACTIVE,
  51         .fir_htiming = FIR_MAIN_H_TIMING,
  52         .fir_vtiming = FIR_MAIN_V_TIMING,
  53         .sec_vtiming = SEC_MAIN_V_TIMING,
  54         .timing_shift = TIMING_MAIN_SHIFT,
  55         .timing_pi_shift = TIMING_MAIN_PI_SHIFT,
  56 };
  57
  58 static const struct zx_crtc_regs aux_crtc_regs = {
  59         .fir_active = FIR_AUX_ACTIVE,
  60         .fir_htiming = FIR_AUX_H_TIMING,
  61         .fir_vtiming = FIR_AUX_V_TIMING,
  62         .sec_vtiming = SEC_AUX_V_TIMING,
  63         .timing_shift = TIMING_AUX_SHIFT,
  64         .timing_pi_shift = TIMING_AUX_PI_SHIFT,
  65 };
  66
  67 struct zx_crtc_bits {
  68         u32 polarity_mask;
  69         u32 polarity_shift;
  70         u32 int_frame_mask;
  71         u32 tc_enable;
  72         u32 sec_vactive_shift;
  73         u32 sec_vactive_mask;
  74         u32 interlace_select;
  75         u32 pi_enable;
  76         u32 div_vga_shift;
  77         u32 div_pic_shift;
  78         u32 div_tvenc_shift;
  79         u32 div_hdmi_pnx_shift;
  80         u32 div_hdmi_shift;
  81         u32 div_inf_shift;
  82         u32 div_layer_shift;
  83 };
  84
  85 static const struct zx_crtc_bits main_crtc_bits = {
  86         .polarity_mask = MAIN_POL_MASK,
  87         .polarity_shift = MAIN_POL_SHIFT,
  88         .int_frame_mask = TIMING_INT_MAIN_FRAME,
  89         .tc_enable = MAIN_TC_EN,
  90         .sec_vactive_shift = SEC_VACT_MAIN_SHIFT,
  91         .sec_vactive_mask = SEC_VACT_MAIN_MASK,
  92         .interlace_select = MAIN_INTERLACE_SEL,
  93         .pi_enable = MAIN_PI_EN,
  94         .div_vga_shift = VGA_MAIN_DIV_SHIFT,
  95         .div_pic_shift = PIC_MAIN_DIV_SHIFT,
  96         .div_tvenc_shift = TVENC_MAIN_DIV_SHIFT,
  97         .div_hdmi_pnx_shift = HDMI_MAIN_PNX_DIV_SHIFT,
  98         .div_hdmi_shift = HDMI_MAIN_DIV_SHIFT,
  99         .div_inf_shift = INF_MAIN_DIV_SHIFT,
 100         .div_layer_shift = LAYER_MAIN_DIV_SHIFT,
 101 };
 102
 103 static const struct zx_crtc_bits aux_crtc_bits = {
 104         .polarity_mask = AUX_POL_MASK,
 105         .polarity_shift = AUX_POL_SHIFT,
 106         .int_frame_mask = TIMING_INT_AUX_FRAME,
 107         .tc_enable = AUX_TC_EN,
 108         .sec_vactive_shift = SEC_VACT_AUX_SHIFT,
 109         .sec_vactive_mask = SEC_VACT_AUX_MASK,
 110         .interlace_select = AUX_INTERLACE_SEL,
 111         .pi_enable = AUX_PI_EN,
 112         .div_vga_shift = VGA_AUX_DIV_SHIFT,
 113         .div_pic_shift = PIC_AUX_DIV_SHIFT,
 114         .div_tvenc_shift = TVENC_AUX_DIV_SHIFT,
 115         .div_hdmi_pnx_shift = HDMI_AUX_PNX_DIV_SHIFT,
 116         .div_hdmi_shift = HDMI_AUX_DIV_SHIFT,
 117         .div_inf_shift = INF_AUX_DIV_SHIFT,
 118         .div_layer_shift = LAYER_AUX_DIV_SHIFT,
 119 };
 120
 121 struct zx_crtc {
 122         struct drm_crtc crtc;
 123         struct drm_plane *primary;
 124         struct zx_vou_hw *vou;
 125         void __iomem *chnreg;
 126         void __iomem *chncsc;
 127         void __iomem *dither;
 128         const struct zx_crtc_regs *regs;
 129         const struct zx_crtc_bits *bits;
 130         enum vou_chn_type chn_type;
 131         struct clk *pixclk;
 132 };
 133
 134 #define to_zx_crtc(x) container_of(x, struct zx_crtc, crtc)
 135
 136 struct vou_layer_bits {
 137         u32 enable;
 138         u32 chnsel;
 139         u32 clksel;
 140 };
 141
 142 static const struct vou_layer_bits zx_gl_bits[GL_NUM] = {
 143         {
 144                 .enable = OSD_CTRL0_GL0_EN,
 145                 .chnsel = OSD_CTRL0_GL0_SEL,
 146                 .clksel = VOU_CLK_GL0_SEL,
 147         }, {
 148                 .enable = OSD_CTRL0_GL1_EN,
 149                 .chnsel = OSD_CTRL0_GL1_SEL,
 150                 .clksel = VOU_CLK_GL1_SEL,
 151         },
 152 };
 153
 154 static const struct vou_layer_bits zx_vl_bits[VL_NUM] = {
 155         {
 156                 .enable = OSD_CTRL0_VL0_EN,
 157                 .chnsel = OSD_CTRL0_VL0_SEL,
 158                 .clksel = VOU_CLK_VL0_SEL,
 159         }, {
 160                 .enable = OSD_CTRL0_VL1_EN,
 161                 .chnsel = OSD_CTRL0_VL1_SEL,
 162                 .clksel = VOU_CLK_VL1_SEL,
 163         }, {
 164                 .enable = OSD_CTRL0_VL2_EN,
 165                 .chnsel = OSD_CTRL0_VL2_SEL,
 166                 .clksel = VOU_CLK_VL2_SEL,
 167         },
 168 };
 169
 170 struct zx_vou_hw {
 171         struct device *dev;
 172         void __iomem *osd;
 173         void __iomem *timing;
 174         void __iomem *vouctl;
 175         void __iomem *otfppu;
 176         void __iomem *dtrc;
 177         struct clk *axi_clk;
 178         struct clk *ppu_clk;
 179         struct clk *main_clk;
 180         struct clk *aux_clk;
 181         struct zx_crtc *main_crtc;
 182         struct zx_crtc *aux_crtc;
 183 };
 184
 185 enum vou_inf_data_sel {
 186         VOU_YUV444      = 0,
 187         VOU_RGB_101010  = 1,
 188         VOU_RGB_888     = 2,
 189         VOU_RGB_666     = 3,
 190 };
 191
 192 struct vou_inf {
 193         enum vou_inf_id id;
 194         enum vou_inf_data_sel data_sel;
 195         u32 clocks_en_bits;
 196         u32 clocks_sel_bits;
 197 };
 198
 199 static struct vou_inf vou_infs[] = {
 200         [VOU_HDMI] = {
 201                 .data_sel = VOU_YUV444,
 202                 .clocks_en_bits = BIT(24) | BIT(18) | BIT(6),
 203                 .clocks_sel_bits = BIT(13) | BIT(2),
 204         },
 205         [VOU_TV_ENC] = {
 206                 .data_sel = VOU_YUV444,
 207                 .clocks_en_bits = BIT(15),
 208                 .clocks_sel_bits = BIT(11) | BIT(0),
 209         },
 210         [VOU_VGA] = {
 211                 .data_sel = VOU_RGB_888,
 212                 .clocks_en_bits = BIT(1),
 213                 .clocks_sel_bits = BIT(10),
 214         },
 215 };
 216
 217 static inline struct zx_vou_hw *crtc_to_vou(struct drm_crtc *crtc)
 218 {
 219         struct zx_crtc *zcrtc = to_zx_crtc(crtc);
 220
 221         return zcrtc->vou;
 222 }
 223
 224 void vou_inf_hdmi_audio_sel(struct drm_crtc *crtc,
 225                             enum vou_inf_hdmi_audio aud)
 226 {
 227         struct zx_crtc *zcrtc = to_zx_crtc(crtc);
 228         struct zx_vou_hw *vou = zcrtc->vou;
 229
 230         zx_writel_mask(vou->vouctl + VOU_INF_HDMI_CTRL, VOU_HDMI_AUD_MASK, aud);
 231 }
 232
 233 void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc)
 234 {
 235         struct zx_crtc *zcrtc = to_zx_crtc(crtc);
 236         struct zx_vou_hw *vou = zcrtc->vou;
 237         struct vou_inf *inf = &vou_infs[id];
 238         void __iomem *dither = zcrtc->dither;
 239         void __iomem *csc = zcrtc->chncsc;
 240         bool is_main = zcrtc->chn_type == VOU_CHN_MAIN;
 241         u32 data_sel_shift = id << 1;
 242
 243         if (inf->data_sel != VOU_YUV444) {
 244                 /* Enable channel CSC for RGB output */
 245                 zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK,
 246                                CSC_BT709_IMAGE_YCBCR2RGB << CSC_COV_MODE_SHIFT);
 247                 zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE,
 248                                CSC_WORK_ENABLE);
 249
 250                 /* Bypass Dither block for RGB output */
 251                 zx_writel_mask(dither + OSD_DITHER_CTRL0, DITHER_BYSPASS,
 252                                DITHER_BYSPASS);
 253         } else {
 254                 zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE, 0);
 255                 zx_writel_mask(dither + OSD_DITHER_CTRL0, DITHER_BYSPASS, 0);
 256         }
 257
 258         /* Select data format */
 259         zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift,
 260                        inf->data_sel << data_sel_shift);
 261
 262         /* Select channel */
 263         zx_writel_mask(vou->vouctl + VOU_INF_CH_SEL, 0x1 << id,
 264                        zcrtc->chn_type << id);
 265
 266         /* Select interface clocks */
 267         zx_writel_mask(vou->vouctl + VOU_CLK_SEL, inf->clocks_sel_bits,
 268                        is_main ? 0 : inf->clocks_sel_bits);
 269
 270         /* Enable interface clocks */
 271         zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits,
 272                        inf->clocks_en_bits);
 273
 274         /* Enable the device */
 275         zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 1 << id);
 276 }
 277
 278 void vou_inf_disable(enum vou_inf_id id, struct drm_crtc *crtc)
 279 {
 280         struct zx_vou_hw *vou = crtc_to_vou(crtc);
 281         struct vou_inf *inf = &vou_infs[id];
 282
 283         /* Disable the device */
 284         zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 0);
 285
 286         /* Disable interface clocks */
 287         zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits, 0);
 288 }
 289
 290 void zx_vou_config_dividers(struct drm_crtc *crtc,
 291                             struct vou_div_config *configs, int num)
 292 {
 293         struct zx_crtc *zcrtc = to_zx_crtc(crtc);
 294         struct zx_vou_hw *vou = zcrtc->vou;
 295         const struct zx_crtc_bits *bits = zcrtc->bits;
 296         int i;
 297
 298         /* Clear update flag bit */
 299         zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE, 0);
 300
 301         for (i = 0; i < num; i++) {
 302                 struct vou_div_config *cfg = configs + i;
 303                 u32 reg, shift;
 304
 305                 switch (cfg->id) {
 306                 case VOU_DIV_VGA:
 307                         reg = VOU_CLK_SEL;
 308                         shift = bits->div_vga_shift;
 309                         break;
 310                 case VOU_DIV_PIC:
 311                         reg = VOU_CLK_SEL;
 312                         shift = bits->div_pic_shift;
 313                         break;
 314                 case VOU_DIV_TVENC:
 315                         reg = VOU_DIV_PARA;
 316                         shift = bits->div_tvenc_shift;
 317                         break;
 318                 case VOU_DIV_HDMI_PNX:
 319                         reg = VOU_DIV_PARA;
 320                         shift = bits->div_hdmi_pnx_shift;
 321                         break;
 322                 case VOU_DIV_HDMI:
 323                         reg = VOU_DIV_PARA;
 324                         shift = bits->div_hdmi_shift;
 325                         break;
 326                 case VOU_DIV_INF:
 327                         reg = VOU_DIV_PARA;
 328                         shift = bits->div_inf_shift;
 329                         break;
 330                 case VOU_DIV_LAYER:
 331                         reg = VOU_DIV_PARA;
 332                         shift = bits->div_layer_shift;
 333                         break;
 334                 default:
 335                         continue;
 336                 }
 337
 338                 /* Each divider occupies 3 bits */
 339                 zx_writel_mask(vou->vouctl + reg, 0x7 << shift,
 340                                cfg->val << shift);
 341         }
 342
 343         /* Set update flag bit to get dividers effected */
 344         zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE,
 345                        DIV_PARA_UPDATE);
 346 }
 347
 348 static inline void vou_chn_set_update(struct zx_crtc *zcrtc)
 349 {
 350         zx_writel(zcrtc->chnreg + CHN_UPDATE, 1);
 351 }
 352
 353 static void zx_crtc_enable(struct drm_crtc *crtc)
 354 {
 355         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 356         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 357         struct zx_crtc *zcrtc = to_zx_crtc(crtc);
 358         struct zx_vou_hw *vou = zcrtc->vou;
 359         const struct zx_crtc_regs *regs = zcrtc->regs;
 360         const struct zx_crtc_bits *bits = zcrtc->bits;
 361         struct videomode vm;
 362         u32 scan_mask;
 363         u32 pol = 0;
 364         u32 val;
 365         int ret;
 366
 367         drm_display_mode_to_videomode(mode, &vm);
 368
 369         /* Set up timing parameters */
 370         val = V_ACTIVE((interlaced ? vm.vactive / 2 : vm.vactive) - 1);
 371         val |= H_ACTIVE(vm.hactive - 1);
 372         zx_writel(vou->timing + regs->fir_active, val);
 373
 374         val = SYNC_WIDE(vm.hsync_len - 1);
 375         val |= BACK_PORCH(vm.hback_porch - 1);
 376         val |= FRONT_PORCH(vm.hfront_porch - 1);
 377         zx_writel(vou->timing + regs->fir_htiming, val);
 378
 379         val = SYNC_WIDE(vm.vsync_len - 1);
 380         val |= BACK_PORCH(vm.vback_porch - 1);
 381         val |= FRONT_PORCH(vm.vfront_porch - 1);
 382         zx_writel(vou->timing + regs->fir_vtiming, val);
 383
 384         if (interlaced) {
 385                 u32 shift = bits->sec_vactive_shift;
 386                 u32 mask = bits->sec_vactive_mask;
 387
 388                 val = zx_readl(vou->timing + SEC_V_ACTIVE);
 389                 val &= ~mask;
 390                 val |= ((vm.vactive / 2 - 1) << shift) & mask;
 391                 zx_writel(vou->timing + SEC_V_ACTIVE, val);
 392
 393                 val = SYNC_WIDE(vm.vsync_len - 1);
 394                 /*
 395                  * The vback_porch for the second field needs to shift one on
 396                  * the value for the first field.
 397                  */
 398                 val |= BACK_PORCH(vm.vback_porch);
 399                 val |= FRONT_PORCH(vm.vfront_porch - 1);
 400                 zx_writel(vou->timing + regs->sec_vtiming, val);
 401         }
 402
 403         /* Set up polarities */
 404         if (vm.flags & DISPLAY_FLAGS_VSYNC_LOW)
 405                 pol |= 1 << POL_VSYNC_SHIFT;
 406         if (vm.flags & DISPLAY_FLAGS_HSYNC_LOW)
 407                 pol |= 1 << POL_HSYNC_SHIFT;
 408
 409         zx_writel_mask(vou->timing + TIMING_CTRL, bits->polarity_mask,
 410                        pol << bits->polarity_shift);
 411
 412         /* Setup SHIFT register by following what ZTE BSP does */
 413         val = H_SHIFT_VAL;
 414         if (interlaced)
 415                 val |= V_SHIFT_VAL << 16;
 416         zx_writel(vou->timing + regs->timing_shift, val);
 417         zx_writel(vou->timing + regs->timing_pi_shift, H_PI_SHIFT_VAL);
 418
 419         /* Progressive or interlace scan select */
 420         scan_mask = bits->interlace_select | bits->pi_enable;
 421         zx_writel_mask(vou->timing + SCAN_CTRL, scan_mask,
 422                        interlaced ? scan_mask : 0);
 423
 424         /* Enable TIMING_CTRL */
 425         zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable,
 426                        bits->tc_enable);
 427
 428         /* Configure channel screen size */
 429         zx_writel_mask(zcrtc->chnreg + CHN_CTRL1, CHN_SCREEN_W_MASK,
 430                        vm.hactive << CHN_SCREEN_W_SHIFT);
 431         zx_writel_mask(zcrtc->chnreg + CHN_CTRL1, CHN_SCREEN_H_MASK,
 432                        vm.vactive << CHN_SCREEN_H_SHIFT);
 433
 434         /* Configure channel interlace buffer control */
 435         zx_writel_mask(zcrtc->chnreg + CHN_INTERLACE_BUF_CTRL, CHN_INTERLACE_EN,
 436                        interlaced ? CHN_INTERLACE_EN : 0);
 437
 438         /* Update channel */
 439         vou_chn_set_update(zcrtc);
 440
 441         /* Enable channel */
 442         zx_writel_mask(zcrtc->chnreg + CHN_CTRL0, CHN_ENABLE, CHN_ENABLE);
 443
 444         drm_crtc_vblank_on(crtc);
 445
 446         ret = clk_set_rate(zcrtc->pixclk, mode->clock * 1000);
 447         if (ret) {
 448                 DRM_DEV_ERROR(vou->dev, "failed to set pixclk rate: %d\n", ret);
 449                 return;
 450         }
 451
 452         ret = clk_prepare_enable(zcrtc->pixclk);
 453         if (ret)
 454                 DRM_DEV_ERROR(vou->dev, "failed to enable pixclk: %d\n", ret);
 455 }
 456
 457 static void zx_crtc_disable(struct drm_crtc *crtc)
 458 {
 459         struct zx_crtc *zcrtc = to_zx_crtc(crtc);
 460         const struct zx_crtc_bits *bits = zcrtc->bits;
 461         struct zx_vou_hw *vou = zcrtc->vou;
 462
 463         clk_disable_unprepare(zcrtc->pixclk);
 464
 465         drm_crtc_vblank_off(crtc);
 466
 467         /* Disable channel */
 468         zx_writel_mask(zcrtc->chnreg + CHN_CTRL0, CHN_ENABLE, 0);
 469
 470         /* Disable TIMING_CTRL */
 471         zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable, 0);
 472 }
 473
 474 static void zx_crtc_atomic_flush(struct drm_crtc *crtc,
 475                                   struct drm_crtc_state *old_state)
 476 {
 477         struct drm_pending_vblank_event *event = crtc->state->event;
 478
 479         if (!event)
 480                 return;
 481
 482         crtc->state->event = NULL;
 483
 484         spin_lock_irq(&crtc->dev->event_lock);
 485         if (drm_crtc_vblank_get(crtc) == 0)
 486                 drm_crtc_arm_vblank_event(crtc, event);
 487         else
 488                 drm_crtc_send_vblank_event(crtc, event);
 489         spin_unlock_irq(&crtc->dev->event_lock);
 490 }
 491
 492 static const struct drm_crtc_helper_funcs zx_crtc_helper_funcs = {
 493         .enable = zx_crtc_enable,
 494         .disable = zx_crtc_disable,
 495         .atomic_flush = zx_crtc_atomic_flush,
 496 };
 497
 498 static int zx_vou_enable_vblank(struct drm_crtc *crtc)
 499 {
 500         struct zx_crtc *zcrtc = to_zx_crtc(crtc);
 501         struct zx_vou_hw *vou = crtc_to_vou(crtc);
 502         u32 int_frame_mask = zcrtc->bits->int_frame_mask;
 503
 504         zx_writel_mask(vou->timing + TIMING_INT_CTRL, int_frame_mask,
 505                        int_frame_mask);
 506
 507         return 0;
 508 }
 509
 510 static void zx_vou_disable_vblank(struct drm_crtc *crtc)
 511 {
 512         struct zx_crtc *zcrtc = to_zx_crtc(crtc);
 513         struct zx_vou_hw *vou = crtc_to_vou(crtc);
 514
 515         zx_writel_mask(vou->timing + TIMING_INT_CTRL,
 516                        zcrtc->bits->int_frame_mask, 0);
 517 }
 518
 519 static const struct drm_crtc_funcs zx_crtc_funcs = {
 520         .destroy = drm_crtc_cleanup,
 521         .set_config = drm_atomic_helper_set_config,
 522         .page_flip = drm_atomic_helper_page_flip,
 523         .reset = drm_atomic_helper_crtc_reset,
 524         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 525         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 526         .enable_vblank = zx_vou_enable_vblank,
 527         .disable_vblank = zx_vou_disable_vblank,
 528 };
 529
 530 static int zx_crtc_init(struct drm_device *drm, struct zx_vou_hw *vou,
 531                         enum vou_chn_type chn_type)
 532 {
 533         struct device *dev = vou->dev;
 534         struct zx_plane *zplane;
 535         struct zx_crtc *zcrtc;
 536         int ret;
 537
 538         zcrtc = devm_kzalloc(dev, sizeof(*zcrtc), GFP_KERNEL);
 539         if (!zcrtc)
 540                 return -ENOMEM;
 541
 542         zcrtc->vou = vou;
 543         zcrtc->chn_type = chn_type;
 544
 545         zplane = devm_kzalloc(dev, sizeof(*zplane), GFP_KERNEL);
 546         if (!zplane)
 547                 return -ENOMEM;
 548
 549         zplane->dev = dev;
 550
 551         if (chn_type == VOU_CHN_MAIN) {
 552                 zplane->layer = vou->osd + MAIN_GL_OFFSET;
 553                 zplane->csc = vou->osd + MAIN_GL_CSC_OFFSET;
 554                 zplane->hbsc = vou->osd + MAIN_HBSC_OFFSET;
 555                 zplane->rsz = vou->otfppu + MAIN_RSZ_OFFSET;
 556                 zplane->bits = &zx_gl_bits[0];
 557                 zcrtc->chnreg = vou->osd + OSD_MAIN_CHN;
 558                 zcrtc->chncsc = vou->osd + MAIN_CHN_CSC_OFFSET;
 559                 zcrtc->dither = vou->osd + MAIN_DITHER_OFFSET;
 560                 zcrtc->regs = &main_crtc_regs;
 561                 zcrtc->bits = &main_crtc_bits;
 562         } else {
 563                 zplane->layer = vou->osd + AUX_GL_OFFSET;
 564                 zplane->csc = vou->osd + AUX_GL_CSC_OFFSET;
 565                 zplane->hbsc = vou->osd + AUX_HBSC_OFFSET;
 566                 zplane->rsz = vou->otfppu + AUX_RSZ_OFFSET;
 567                 zplane->bits = &zx_gl_bits[1];
 568                 zcrtc->chnreg = vou->osd + OSD_AUX_CHN;
 569                 zcrtc->chncsc = vou->osd + AUX_CHN_CSC_OFFSET;
 570                 zcrtc->dither = vou->osd + AUX_DITHER_OFFSET;
 571                 zcrtc->regs = &aux_crtc_regs;
 572                 zcrtc->bits = &aux_crtc_bits;
 573         }
 574
 575         zcrtc->pixclk = devm_clk_get(dev, (chn_type == VOU_CHN_MAIN) ?
 576                                           "main_wclk" : "aux_wclk");
 577         if (IS_ERR(zcrtc->pixclk)) {
 578                 ret = PTR_ERR(zcrtc->pixclk);
 579                 DRM_DEV_ERROR(dev, "failed to get pix clk: %d\n", ret);
 580                 return ret;
 581         }
 582
 583         ret = zx_plane_init(drm, zplane, DRM_PLANE_TYPE_PRIMARY);
 584         if (ret) {
 585                 DRM_DEV_ERROR(dev, "failed to init primary plane: %d\n", ret);
 586                 return ret;
 587         }
 588
 589         zcrtc->primary = &zplane->plane;
 590
 591         ret = drm_crtc_init_with_planes(drm, &zcrtc->crtc, zcrtc->primary, NULL,
 592                                         &zx_crtc_funcs, NULL);
 593         if (ret) {
 594                 DRM_DEV_ERROR(dev, "failed to init drm crtc: %d\n", ret);
 595                 return ret;
 596         }
 597
 598         drm_crtc_helper_add(&zcrtc->crtc, &zx_crtc_helper_funcs);
 599
 600         if (chn_type == VOU_CHN_MAIN)
 601                 vou->main_crtc = zcrtc;
 602         else
 603                 vou->aux_crtc = zcrtc;
 604
 605         return 0;
 606 }
 607
 608 void zx_vou_layer_enable(struct drm_plane *plane)
 609 {
 610         struct zx_crtc *zcrtc = to_zx_crtc(plane->state->crtc);
 611         struct zx_vou_hw *vou = zcrtc->vou;
 612         struct zx_plane *zplane = to_zx_plane(plane);
 613         const struct vou_layer_bits *bits = zplane->bits;
 614
 615         if (zcrtc->chn_type == VOU_CHN_MAIN) {
 616                 zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel, 0);
 617                 zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, 0);
 618         } else {
 619                 zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel,
 620                                bits->chnsel);
 621                 zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel,
 622                                bits->clksel);
 623         }
 624
 625         zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, bits->enable);
 626 }
 627
 628 void zx_vou_layer_disable(struct drm_plane *plane)
 629 {
 630         struct zx_crtc *zcrtc = to_zx_crtc(plane->crtc);
 631         struct zx_vou_hw *vou = zcrtc->vou;
 632         struct zx_plane *zplane = to_zx_plane(plane);
 633         const struct vou_layer_bits *bits = zplane->bits;
 634
 635         zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, 0);
 636 }
 637
 638 static void zx_overlay_init(struct drm_device *drm, struct zx_vou_hw *vou)
 639 {
 640         struct device *dev = vou->dev;
 641         struct zx_plane *zplane;
 642         int i;
 643         int ret;
 644
 645         /*
 646          * VL0 has some quirks on scaling support which need special handling.
 647          * Let's leave it out for now.
 648          */
 649         for (i = 1; i < VL_NUM; i++) {
 650                 zplane = devm_kzalloc(dev, sizeof(*zplane), GFP_KERNEL);
 651                 if (!zplane) {
 652                         DRM_DEV_ERROR(dev, "failed to allocate zplane %d\n", i);
 653                         return;
 654                 }
 655
 656                 zplane->layer = vou->osd + OSD_VL_OFFSET(i);
 657                 zplane->hbsc = vou->osd + HBSC_VL_OFFSET(i);
 658                 zplane->rsz = vou->otfppu + RSZ_VL_OFFSET(i);
 659                 zplane->bits = &zx_vl_bits[i];
 660
 661                 ret = zx_plane_init(drm, zplane, DRM_PLANE_TYPE_OVERLAY);
 662                 if (ret) {
 663                         DRM_DEV_ERROR(dev, "failed to init overlay %d\n", i);
 664                         continue;
 665                 }
 666         }
 667 }
 668
 669 static inline void zx_osd_int_update(struct zx_crtc *zcrtc)
 670 {
 671         struct drm_crtc *crtc = &zcrtc->crtc;
 672         struct drm_plane *plane;
 673
 674         vou_chn_set_update(zcrtc);
 675
 676         drm_for_each_plane_mask(plane, crtc->dev, crtc->state->plane_mask)
 677                 zx_plane_set_update(plane);
 678 }
 679
 680 static irqreturn_t vou_irq_handler(int irq, void *dev_id)
 681 {
 682         struct zx_vou_hw *vou = dev_id;
 683         u32 state;
 684
 685         /* Handle TIMING_CTRL frame interrupts */
 686         state = zx_readl(vou->timing + TIMING_INT_STATE);
 687         zx_writel(vou->timing + TIMING_INT_STATE, state);
 688
 689         if (state & TIMING_INT_MAIN_FRAME)
 690                 drm_crtc_handle_vblank(&vou->main_crtc->crtc);
 691
 692         if (state & TIMING_INT_AUX_FRAME)
 693                 drm_crtc_handle_vblank(&vou->aux_crtc->crtc);
 694
 695         /* Handle OSD interrupts */
 696         state = zx_readl(vou->osd + OSD_INT_STA);
 697         zx_writel(vou->osd + OSD_INT_CLRSTA, state);
 698
 699         if (state & OSD_INT_MAIN_UPT)
 700                 zx_osd_int_update(vou->main_crtc);
 701
 702         if (state & OSD_INT_AUX_UPT)
 703                 zx_osd_int_update(vou->aux_crtc);
 704
 705         if (state & OSD_INT_ERROR)
 706                 DRM_DEV_ERROR(vou->dev, "OSD ERROR: 0x%08x!\n", state);
 707
 708         return IRQ_HANDLED;
 709 }
 710
 711 static void vou_dtrc_init(struct zx_vou_hw *vou)
 712 {
 713         /* Clear bit for bypass by ID */
 714         zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL,
 715                        TILE2RASTESCAN_BYPASS_MODE, 0);
 716
 717         /* Select ARIDR mode */
 718         zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL, DETILE_ARIDR_MODE_MASK,
 719                        DETILE_ARID_IN_ARIDR);
 720
 721         /* Bypass decompression for both frames */
 722         zx_writel_mask(vou->dtrc + DTRC_F0_CTRL, DTRC_DECOMPRESS_BYPASS,
 723                        DTRC_DECOMPRESS_BYPASS);
 724         zx_writel_mask(vou->dtrc + DTRC_F1_CTRL, DTRC_DECOMPRESS_BYPASS,
 725                        DTRC_DECOMPRESS_BYPASS);
 726
 727         /* Set up ARID register */
 728         zx_writel(vou->dtrc + DTRC_ARID, DTRC_ARID3(0xf) | DTRC_ARID2(0xe) |
 729                   DTRC_ARID1(0xf) | DTRC_ARID0(0xe));
 730 }
 731
 732 static void vou_hw_init(struct zx_vou_hw *vou)
 733 {
 734         /* Release reset for all VOU modules */
 735         zx_writel(vou->vouctl + VOU_SOFT_RST, ~0);
 736
 737         /* Enable all VOU module clocks */
 738         zx_writel(vou->vouctl + VOU_CLK_EN, ~0);
 739
 740         /* Clear both OSD and TIMING_CTRL interrupt state */
 741         zx_writel(vou->osd + OSD_INT_CLRSTA, ~0);
 742         zx_writel(vou->timing + TIMING_INT_STATE, ~0);
 743
 744         /* Enable OSD and TIMING_CTRL interrrupts */
 745         zx_writel(vou->osd + OSD_INT_MSK, OSD_INT_ENABLE);
 746         zx_writel(vou->timing + TIMING_INT_CTRL, TIMING_INT_ENABLE);
 747
 748         /* Select GPC as input to gl/vl scaler as a sane default setting */
 749         zx_writel(vou->otfppu + OTFPPU_RSZ_DATA_SOURCE, 0x2a);
 750
 751         /*
 752          * Needs to reset channel and layer logic per frame when frame starts
 753          * to get VOU work properly.
 754          */
 755         zx_writel_mask(vou->osd + OSD_RST_CLR, RST_PER_FRAME, RST_PER_FRAME);
 756
 757         vou_dtrc_init(vou);
 758 }
 759
 760 static int zx_crtc_bind(struct device *dev, struct device *master, void *data)
 761 {
 762         struct platform_device *pdev = to_platform_device(dev);
 763         struct drm_device *drm = data;
 764         struct zx_vou_hw *vou;
 765         struct resource *res;
 766         int irq;
 767         int ret;
 768
 769         vou = devm_kzalloc(dev, sizeof(*vou), GFP_KERNEL);
 770         if (!vou)
 771                 return -ENOMEM;
 772
 773         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "osd");
 774         vou->osd = devm_ioremap_resource(dev, res);
 775         if (IS_ERR(vou->osd)) {
 776                 ret = PTR_ERR(vou->osd);
 777                 DRM_DEV_ERROR(dev, "failed to remap osd region: %d\n", ret);
 778                 return ret;
 779         }
 780
 781         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "timing_ctrl");
 782         vou->timing = devm_ioremap_resource(dev, res);
 783         if (IS_ERR(vou->timing)) {
 784                 ret = PTR_ERR(vou->timing);
 785                 DRM_DEV_ERROR(dev, "failed to remap timing_ctrl region: %d\n",
 786                               ret);
 787                 return ret;
 788         }
 789
 790         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dtrc");
 791         vou->dtrc = devm_ioremap_resource(dev, res);
 792         if (IS_ERR(vou->dtrc)) {
 793                 ret = PTR_ERR(vou->dtrc);
 794                 DRM_DEV_ERROR(dev, "failed to remap dtrc region: %d\n", ret);
 795                 return ret;
 796         }
 797
 798         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vou_ctrl");
 799         vou->vouctl = devm_ioremap_resource(dev, res);
 800         if (IS_ERR(vou->vouctl)) {
 801                 ret = PTR_ERR(vou->vouctl);
 802                 DRM_DEV_ERROR(dev, "failed to remap vou_ctrl region: %d\n",
 803                               ret);
 804                 return ret;
 805         }
 806
 807         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "otfppu");
 808         vou->otfppu = devm_ioremap_resource(dev, res);
 809         if (IS_ERR(vou->otfppu)) {
 810                 ret = PTR_ERR(vou->otfppu);
 811                 DRM_DEV_ERROR(dev, "failed to remap otfppu region: %d\n", ret);
 812                 return ret;
 813         }
 814
 815         irq = platform_get_irq(pdev, 0);
 816         if (irq < 0)
 817                 return irq;
 818
 819         vou->axi_clk = devm_clk_get(dev, "aclk");
 820         if (IS_ERR(vou->axi_clk)) {
 821                 ret = PTR_ERR(vou->axi_clk);
 822                 DRM_DEV_ERROR(dev, "failed to get axi_clk: %d\n", ret);
 823                 return ret;
 824         }
 825
 826         vou->ppu_clk = devm_clk_get(dev, "ppu_wclk");
 827         if (IS_ERR(vou->ppu_clk)) {
 828                 ret = PTR_ERR(vou->ppu_clk);
 829                 DRM_DEV_ERROR(dev, "failed to get ppu_clk: %d\n", ret);
 830                 return ret;
 831         }
 832
 833         ret = clk_prepare_enable(vou->axi_clk);
 834         if (ret) {
 835                 DRM_DEV_ERROR(dev, "failed to enable axi_clk: %d\n", ret);
 836                 return ret;
 837         }
 838
 839         clk_prepare_enable(vou->ppu_clk);
 840         if (ret) {
 841                 DRM_DEV_ERROR(dev, "failed to enable ppu_clk: %d\n", ret);
 842                 goto disable_axi_clk;
 843         }
 844
 845         vou->dev = dev;
 846         dev_set_drvdata(dev, vou);
 847
 848         vou_hw_init(vou);
 849
 850         ret = devm_request_irq(dev, irq, vou_irq_handler, 0, "zx_vou", vou);
 851         if (ret < 0) {
 852                 DRM_DEV_ERROR(dev, "failed to request vou irq: %d\n", ret);
 853                 goto disable_ppu_clk;
 854         }
 855
 856         ret = zx_crtc_init(drm, vou, VOU_CHN_MAIN);
 857         if (ret) {
 858                 DRM_DEV_ERROR(dev, "failed to init main channel crtc: %d\n",
 859                               ret);
 860                 goto disable_ppu_clk;
 861         }
 862
 863         ret = zx_crtc_init(drm, vou, VOU_CHN_AUX);
 864         if (ret) {
 865                 DRM_DEV_ERROR(dev, "failed to init aux channel crtc: %d\n",
 866                               ret);
 867                 goto disable_ppu_clk;
 868         }
 869
 870         zx_overlay_init(drm, vou);
 871
 872         return 0;
 873
 874 disable_ppu_clk:
 875         clk_disable_unprepare(vou->ppu_clk);
 876 disable_axi_clk:
 877         clk_disable_unprepare(vou->axi_clk);
 878         return ret;
 879 }
 880
 881 static void zx_crtc_unbind(struct device *dev, struct device *master,
 882                            void *data)
 883 {
 884         struct zx_vou_hw *vou = dev_get_drvdata(dev);
 885
 886         clk_disable_unprepare(vou->axi_clk);
 887         clk_disable_unprepare(vou->ppu_clk);
 888 }
 889
 890 static const struct component_ops zx_crtc_component_ops = {
 891         .bind = zx_crtc_bind,
 892         .unbind = zx_crtc_unbind,
 893 };
 894
 895 static int zx_crtc_probe(struct platform_device *pdev)
 896 {
 897         return component_add(&pdev->dev, &zx_crtc_component_ops);
 898 }
 899
 900 static int zx_crtc_remove(struct platform_device *pdev)
 901 {
 902         component_del(&pdev->dev, &zx_crtc_component_ops);
 903         return 0;
 904 }
 905
 906 static const struct of_device_id zx_crtc_of_match[] = {
 907         { .compatible = "zte,zx296718-dpc", },
 908         { /* end */ },
 909 };
 910 MODULE_DEVICE_TABLE(of, zx_crtc_of_match);
 911
 912 struct platform_driver zx_crtc_driver = {
 913         .probe = zx_crtc_probe,
 914         .remove = zx_crtc_remove,
 915         .driver = {
 916                 .name = "zx-crtc",
 917                 .of_match_table = zx_crtc_of_match,
 918         },
 919 };