drivers/pci/pci.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef DRIVERS_PCI_H
   3 #define DRIVERS_PCI_H
   4
   5 #define PCI_FIND_CAP_TTL        48
   6
   7 #define PCI_VSEC_ID_INTEL_TBT   0x1234  /* Thunderbolt */
   8
   9 extern const unsigned char pcie_link_speed[];
  10 extern bool pci_early_dump;
  11
  12 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
  13
  14 /* Functions internal to the PCI core code */
  15
  16 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
  17 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
  18 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
  19 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
  20 { return; }
  21 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
  22 { return; }
  23 #else
  24 void pci_create_firmware_label_files(struct pci_dev *pdev);
  25 void pci_remove_firmware_label_files(struct pci_dev *pdev);
  26 #endif
  27 void pci_cleanup_rom(struct pci_dev *dev);
  28
  29 enum pci_mmap_api {
  30         PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
  31         PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
  32 };
  33 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
  34                   enum pci_mmap_api mmap_api);
  35
  36 int pci_probe_reset_function(struct pci_dev *dev);
  37 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
  38 int pci_bus_error_reset(struct pci_dev *dev);
  39
  40 /**
  41  * struct pci_platform_pm_ops - Firmware PM callbacks
  42  *
  43  * @bridge_d3: Does the bridge allow entering into D3
  44  *
  45  * @is_manageable: returns 'true' if given device is power manageable by the
  46  *                 platform firmware
  47  *
  48  * @set_state: invokes the platform firmware to set the device's power state
  49  *
  50  * @get_state: queries the platform firmware for a device's current power state
  51  *
  52  * @choose_state: returns PCI power state of given device preferred by the
  53  *                platform; to be used during system-wide transitions from a
  54  *                sleeping state to the working state and vice versa
  55  *
  56  * @set_wakeup: enables/disables wakeup capability for the device
  57  *
  58  * @need_resume: returns 'true' if the given device (which is currently
  59  *               suspended) needs to be resumed to be configured for system
  60  *               wakeup.
  61  *
  62  * If given platform is generally capable of power managing PCI devices, all of
  63  * these callbacks are mandatory.
  64  */
  65 struct pci_platform_pm_ops {
  66         bool (*bridge_d3)(struct pci_dev *dev);
  67         bool (*is_manageable)(struct pci_dev *dev);
  68         int (*set_state)(struct pci_dev *dev, pci_power_t state);
  69         pci_power_t (*get_state)(struct pci_dev *dev);
  70         pci_power_t (*choose_state)(struct pci_dev *dev);
  71         int (*set_wakeup)(struct pci_dev *dev, bool enable);
  72         bool (*need_resume)(struct pci_dev *dev);
  73 };
  74
  75 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
  76 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
  77 void pci_power_up(struct pci_dev *dev);
  78 void pci_disable_enabled_device(struct pci_dev *dev);
  79 int pci_finish_runtime_suspend(struct pci_dev *dev);
  80 void pcie_clear_root_pme_status(struct pci_dev *dev);
  81 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
  82 void pci_pme_restore(struct pci_dev *dev);
  83 bool pci_dev_keep_suspended(struct pci_dev *dev);
  84 void pci_dev_complete_resume(struct pci_dev *pci_dev);
  85 void pci_config_pm_runtime_get(struct pci_dev *dev);
  86 void pci_config_pm_runtime_put(struct pci_dev *dev);
  87 void pci_pm_init(struct pci_dev *dev);
  88 void pci_ea_init(struct pci_dev *dev);
  89 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
  90 void pci_free_cap_save_buffers(struct pci_dev *dev);
  91 bool pci_bridge_d3_possible(struct pci_dev *dev);
  92 void pci_bridge_d3_update(struct pci_dev *dev);
  93
  94 static inline void pci_wakeup_event(struct pci_dev *dev)
  95 {
  96         /* Wait 100 ms before the system can be put into a sleep state. */
  97         pm_wakeup_event(&dev->dev, 100);
  98 }
  99
 100 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
 101 {
 102         return !!(pci_dev->subordinate);
 103 }
 104
 105 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
 106 {
 107         /*
 108          * Currently we allow normal PCI devices and PCI bridges transition
 109          * into D3 if their bridge_d3 is set.
 110          */
 111         return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
 112 }
 113
 114 int pci_vpd_init(struct pci_dev *dev);
 115 void pci_vpd_release(struct pci_dev *dev);
 116 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
 117 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
 118
 119 /* PCI /proc functions */
 120 #ifdef CONFIG_PROC_FS
 121 int pci_proc_attach_device(struct pci_dev *dev);
 122 int pci_proc_detach_device(struct pci_dev *dev);
 123 int pci_proc_detach_bus(struct pci_bus *bus);
 124 #else
 125 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
 126 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
 127 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
 128 #endif
 129
 130 /* Functions for PCI Hotplug drivers to use */
 131 int pci_hp_add_bridge(struct pci_dev *dev);
 132
 133 #ifdef HAVE_PCI_LEGACY
 134 void pci_create_legacy_files(struct pci_bus *bus);
 135 void pci_remove_legacy_files(struct pci_bus *bus);
 136 #else
 137 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
 138 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
 139 #endif
 140
 141 /* Lock for read/write access to pci device and bus lists */
 142 extern struct rw_semaphore pci_bus_sem;
 143 extern struct mutex pci_slot_mutex;
 144
 145 extern raw_spinlock_t pci_lock;
 146
 147 extern unsigned int pci_pm_d3_delay;
 148
 149 #ifdef CONFIG_PCI_MSI
 150 void pci_no_msi(void);
 151 #else
 152 static inline void pci_no_msi(void) { }
 153 #endif
 154
 155 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
 156 {
 157         u16 control;
 158
 159         pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
 160         control &= ~PCI_MSI_FLAGS_ENABLE;
 161         if (enable)
 162                 control |= PCI_MSI_FLAGS_ENABLE;
 163         pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
 164 }
 165
 166 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
 167 {
 168         u16 ctrl;
 169
 170         pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
 171         ctrl &= ~clear;
 172         ctrl |= set;
 173         pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
 174 }
 175
 176 void pci_realloc_get_opt(char *);
 177
 178 static inline int pci_no_d1d2(struct pci_dev *dev)
 179 {
 180         unsigned int parent_dstates = 0;
 181
 182         if (dev->bus->self)
 183                 parent_dstates = dev->bus->self->no_d1d2;
 184         return (dev->no_d1d2 || parent_dstates);
 185
 186 }
 187 extern const struct attribute_group *pci_dev_groups[];
 188 extern const struct attribute_group *pcibus_groups[];
 189 extern const struct device_type pci_dev_type;
 190 extern const struct attribute_group *pci_bus_groups[];
 191
 192
 193 /**
 194  * pci_match_one_device - Tell if a PCI device structure has a matching
 195  *                        PCI device id structure
 196  * @id: single PCI device id structure to match
 197  * @dev: the PCI device structure to match against
 198  *
 199  * Returns the matching pci_device_id structure or %NULL if there is no match.
 200  */
 201 static inline const struct pci_device_id *
 202 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
 203 {
 204         if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
 205             (id->device == PCI_ANY_ID || id->device == dev->device) &&
 206             (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
 207             (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
 208             !((id->class ^ dev->class) & id->class_mask))
 209                 return id;
 210         return NULL;
 211 }
 212
 213 /* PCI slot sysfs helper code */
 214 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
 215
 216 extern struct kset *pci_slots_kset;
 217
 218 struct pci_slot_attribute {
 219         struct attribute attr;
 220         ssize_t (*show)(struct pci_slot *, char *);
 221         ssize_t (*store)(struct pci_slot *, const char *, size_t);
 222 };
 223 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
 224
 225 enum pci_bar_type {
 226         pci_bar_unknown,        /* Standard PCI BAR probe */
 227         pci_bar_io,             /* An I/O port BAR */
 228         pci_bar_mem32,          /* A 32-bit memory BAR */
 229         pci_bar_mem64,          /* A 64-bit memory BAR */
 230 };
 231
 232 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
 233 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
 234                                 int crs_timeout);
 235 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
 236                                         int crs_timeout);
 237 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
 238
 239 int pci_setup_device(struct pci_dev *dev);
 240 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 241                     struct resource *res, unsigned int reg);
 242 void pci_configure_ari(struct pci_dev *dev);
 243 void __pci_bus_size_bridges(struct pci_bus *bus,
 244                         struct list_head *realloc_head);
 245 void __pci_bus_assign_resources(const struct pci_bus *bus,
 246                                 struct list_head *realloc_head,
 247                                 struct list_head *fail_head);
 248 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
 249
 250 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
 251 void pci_disable_bridge_window(struct pci_dev *dev);
 252
 253 /* PCIe link information */
 254 #define PCIE_SPEED2STR(speed) \
 255         ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
 256          (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
 257          (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
 258          (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
 259          "Unknown speed")
 260
 261 /* PCIe speed to Mb/s reduced by encoding overhead */
 262 #define PCIE_SPEED2MBS_ENC(speed) \
 263         ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
 264          (speed) == PCIE_SPEED_8_0GT  ?  8000*128/130 : \
 265          (speed) == PCIE_SPEED_5_0GT  ?  5000*8/10 : \
 266          (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
 267          0)
 268
 269 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
 270 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
 271 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
 272                            enum pcie_link_width *width);
 273 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
 274
 275 /* Single Root I/O Virtualization */
 276 struct pci_sriov {
 277         int             pos;            /* Capability position */
 278         int             nres;           /* Number of resources */
 279         u32             cap;            /* SR-IOV Capabilities */
 280         u16             ctrl;           /* SR-IOV Control */
 281         u16             total_VFs;      /* Total VFs associated with the PF */
 282         u16             initial_VFs;    /* Initial VFs associated with the PF */
 283         u16             num_VFs;        /* Number of VFs available */
 284         u16             offset;         /* First VF Routing ID offset */
 285         u16             stride;         /* Following VF stride */
 286         u16             vf_device;      /* VF device ID */
 287         u32             pgsz;           /* Page size for BAR alignment */
 288         u8              link;           /* Function Dependency Link */
 289         u8              max_VF_buses;   /* Max buses consumed by VFs */
 290         u16             driver_max_VFs; /* Max num VFs driver supports */
 291         struct pci_dev  *dev;           /* Lowest numbered PF */
 292         struct pci_dev  *self;          /* This PF */
 293         u32             cfg_size;       /* VF config space size */
 294         u32             class;          /* VF device */
 295         u8              hdr_type;       /* VF header type */
 296         u16             subsystem_vendor; /* VF subsystem vendor */
 297         u16             subsystem_device; /* VF subsystem device */
 298         resource_size_t barsz[PCI_SRIOV_NUM_BARS];      /* VF BAR size */
 299         bool            drivers_autoprobe; /* Auto probing of VFs by driver */
 300 };
 301
 302 /**
 303  * pci_dev_set_io_state - Set the new error state if possible.
 304  *
 305  * @dev - pci device to set new error_state
 306  * @new - the state we want dev to be in
 307  *
 308  * Must be called with device_lock held.
 309  *
 310  * Returns true if state has been changed to the requested state.
 311  */
 312 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
 313                                         pci_channel_state_t new)
 314 {
 315         bool changed = false;
 316
 317         device_lock_assert(&dev->dev);
 318         switch (new) {
 319         case pci_channel_io_perm_failure:
 320                 switch (dev->error_state) {
 321                 case pci_channel_io_frozen:
 322                 case pci_channel_io_normal:
 323                 case pci_channel_io_perm_failure:
 324                         changed = true;
 325                         break;
 326                 }
 327                 break;
 328         case pci_channel_io_frozen:
 329                 switch (dev->error_state) {
 330                 case pci_channel_io_frozen:
 331                 case pci_channel_io_normal:
 332                         changed = true;
 333                         break;
 334                 }
 335                 break;
 336         case pci_channel_io_normal:
 337                 switch (dev->error_state) {
 338                 case pci_channel_io_frozen:
 339                 case pci_channel_io_normal:
 340                         changed = true;
 341                         break;
 342                 }
 343                 break;
 344         }
 345         if (changed)
 346                 dev->error_state = new;
 347         return changed;
 348 }
 349
 350 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
 351 {
 352         device_lock(&dev->dev);
 353         pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
 354         device_unlock(&dev->dev);
 355
 356         return 0;
 357 }
 358
 359 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
 360 {
 361         return dev->error_state == pci_channel_io_perm_failure;
 362 }
 363
 364 /* pci_dev priv_flags */
 365 #define PCI_DEV_ADDED 0
 366
 367 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
 368 {
 369         assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
 370 }
 371
 372 static inline bool pci_dev_is_added(const struct pci_dev *dev)
 373 {
 374         return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
 375 }
 376
 377 #ifdef CONFIG_PCIEAER
 378 #include <linux/aer.h>
 379
 380 #define AER_MAX_MULTI_ERR_DEVICES       5       /* Not likely to have more */
 381
 382 struct aer_err_info {
 383         struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
 384         int error_dev_num;
 385
 386         unsigned int id:16;
 387
 388         unsigned int severity:2;        /* 0:NONFATAL | 1:FATAL | 2:COR */
 389         unsigned int __pad1:5;
 390         unsigned int multi_error_valid:1;
 391
 392         unsigned int first_error:5;
 393         unsigned int __pad2:2;
 394         unsigned int tlp_header_valid:1;
 395
 396         unsigned int status;            /* COR/UNCOR Error Status */
 397         unsigned int mask;              /* COR/UNCOR Error Mask */
 398         struct aer_header_log_regs tlp; /* TLP Header */
 399 };
 400
 401 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
 402 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
 403 #endif  /* CONFIG_PCIEAER */
 404
 405 #ifdef CONFIG_PCIE_DPC
 406 void pci_save_dpc_state(struct pci_dev *dev);
 407 void pci_restore_dpc_state(struct pci_dev *dev);
 408 #else
 409 static inline void pci_save_dpc_state(struct pci_dev *dev) {}
 410 static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
 411 #endif
 412
 413 #ifdef CONFIG_PCI_ATS
 414 void pci_restore_ats_state(struct pci_dev *dev);
 415 #else
 416 static inline void pci_restore_ats_state(struct pci_dev *dev)
 417 {
 418 }
 419 #endif /* CONFIG_PCI_ATS */
 420
 421 #ifdef CONFIG_PCI_IOV
 422 int pci_iov_init(struct pci_dev *dev);
 423 void pci_iov_release(struct pci_dev *dev);
 424 void pci_iov_remove(struct pci_dev *dev);
 425 void pci_iov_update_resource(struct pci_dev *dev, int resno);
 426 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
 427 void pci_restore_iov_state(struct pci_dev *dev);
 428 int pci_iov_bus_range(struct pci_bus *bus);
 429
 430 #else
 431 static inline int pci_iov_init(struct pci_dev *dev)
 432 {
 433         return -ENODEV;
 434 }
 435 static inline void pci_iov_release(struct pci_dev *dev)
 436
 437 {
 438 }
 439 static inline void pci_iov_remove(struct pci_dev *dev)
 440 {
 441 }
 442 static inline void pci_restore_iov_state(struct pci_dev *dev)
 443 {
 444 }
 445 static inline int pci_iov_bus_range(struct pci_bus *bus)
 446 {
 447         return 0;
 448 }
 449
 450 #endif /* CONFIG_PCI_IOV */
 451
 452 unsigned long pci_cardbus_resource_alignment(struct resource *);
 453
 454 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
 455                                                      struct resource *res)
 456 {
 457 #ifdef CONFIG_PCI_IOV
 458         int resno = res - dev->resource;
 459
 460         if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
 461                 return pci_sriov_resource_alignment(dev, resno);
 462 #endif
 463         if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
 464                 return pci_cardbus_resource_alignment(res);
 465         return resource_alignment(res);
 466 }
 467
 468 void pci_enable_acs(struct pci_dev *dev);
 469 #ifdef CONFIG_PCI_QUIRKS
 470 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
 471 int pci_dev_specific_enable_acs(struct pci_dev *dev);
 472 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
 473 #else
 474 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
 475                                                u16 acs_flags)
 476 {
 477         return -ENOTTY;
 478 }
 479 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
 480 {
 481         return -ENOTTY;
 482 }
 483 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
 484 {
 485         return -ENOTTY;
 486 }
 487 #endif
 488
 489 /* PCI error reporting and recovery */
 490 void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state,
 491                       u32 service);
 492
 493 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
 494 #ifdef CONFIG_PCIEASPM
 495 void pcie_aspm_init_link_state(struct pci_dev *pdev);
 496 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
 497 void pcie_aspm_pm_state_change(struct pci_dev *pdev);
 498 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
 499 #else
 500 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
 501 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
 502 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
 503 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
 504 #endif
 505
 506 #ifdef CONFIG_PCIEASPM_DEBUG
 507 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
 508 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
 509 #else
 510 static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
 511 static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
 512 #endif
 513
 514 #ifdef CONFIG_PCIE_PTM
 515 void pci_ptm_init(struct pci_dev *dev);
 516 #else
 517 static inline void pci_ptm_init(struct pci_dev *dev) { }
 518 #endif
 519
 520 struct pci_dev_reset_methods {
 521         u16 vendor;
 522         u16 device;
 523         int (*reset)(struct pci_dev *dev, int probe);
 524 };
 525
 526 #ifdef CONFIG_PCI_QUIRKS
 527 int pci_dev_specific_reset(struct pci_dev *dev, int probe);
 528 #else
 529 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
 530 {
 531         return -ENOTTY;
 532 }
 533 #endif
 534
 535 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
 536 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
 537                           struct resource *res);
 538 #endif
 539
 540 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
 541 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
 542 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
 543 static inline u64 pci_rebar_size_to_bytes(int size)
 544 {
 545         return 1ULL << (size + 20);
 546 }
 547
 548 struct device_node;
 549
 550 #ifdef CONFIG_OF
 551 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
 552 int of_get_pci_domain_nr(struct device_node *node);
 553 int of_pci_get_max_link_speed(struct device_node *node);
 554
 555 #else
 556 static inline int
 557 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
 558 {
 559         return -EINVAL;
 560 }
 561
 562 static inline int
 563 of_get_pci_domain_nr(struct device_node *node)
 564 {
 565         return -1;
 566 }
 567
 568 static inline int
 569 of_pci_get_max_link_speed(struct device_node *node)
 570 {
 571         return -EINVAL;
 572 }
 573 #endif /* CONFIG_OF */
 574
 575 #if defined(CONFIG_OF_ADDRESS)
 576 int devm_of_pci_get_host_bridge_resources(struct device *dev,
 577                         unsigned char busno, unsigned char bus_max,
 578                         struct list_head *resources, resource_size_t *io_base);
 579 #else
 580 static inline int devm_of_pci_get_host_bridge_resources(struct device *dev,
 581                         unsigned char busno, unsigned char bus_max,
 582                         struct list_head *resources, resource_size_t *io_base)
 583 {
 584         return -EINVAL;
 585 }
 586 #endif
 587
 588 #ifdef CONFIG_PCIEAER
 589 void pci_no_aer(void);
 590 void pci_aer_init(struct pci_dev *dev);
 591 void pci_aer_exit(struct pci_dev *dev);
 592 extern const struct attribute_group aer_stats_attr_group;
 593 void pci_aer_clear_fatal_status(struct pci_dev *dev);
 594 void pci_aer_clear_device_status(struct pci_dev *dev);
 595 #else
 596 static inline void pci_no_aer(void) { }
 597 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
 598 static inline void pci_aer_exit(struct pci_dev *d) { }
 599 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
 600 static inline void pci_aer_clear_device_status(struct pci_dev *dev) { }
 601 #endif
 602
 603 #endif /* DRIVERS_PCI_H */