arch/arc/plat-axs10x/axs10x.c

   1 /*
   2  * AXS101/AXS103 Software Development Platform
   3  *
   4  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/of_fdt.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/libfdt.h>
  20
  21 #include <asm/asm-offsets.h>
  22 #include <asm/io.h>
  23 #include <asm/mach_desc.h>
  24 #include <soc/arc/mcip.h>
  25
  26 #define AXS_MB_CGU              0xE0010000
  27 #define AXS_MB_CREG             0xE0011000
  28
  29 #define CREG_MB_IRQ_MUX         (AXS_MB_CREG + 0x214)
  30 #define CREG_MB_SW_RESET        (AXS_MB_CREG + 0x220)
  31 #define CREG_MB_VER             (AXS_MB_CREG + 0x230)
  32 #define CREG_MB_CONFIG          (AXS_MB_CREG + 0x234)
  33
  34 #define AXC001_CREG             0xF0001000
  35 #define AXC001_GPIO_INTC        0xF0003000
  36
  37 static void __init axs10x_enable_gpio_intc_wire(void)
  38 {
  39         /*
  40          * Peripherals on CPU Card and Mother Board are wired to cpu intc via
  41          * intermediate DW APB GPIO blocks (mainly for debouncing)
  42          *
  43          *         ---------------------
  44          *        |  snps,arc700-intc |
  45          *        ---------------------
  46          *          | #7          | #15
  47          * -------------------   -------------------
  48          * | snps,dw-apb-gpio |  | snps,dw-apb-gpio |
  49          * -------------------   -------------------
  50          *        | #12                     |
  51          *        |                 [ Debug UART on cpu card ]
  52          *        |
  53          * ------------------------
  54          * | snps,dw-apb-intc (MB)|
  55          * ------------------------
  56          *  |      |       |      |
  57          * [eth] [uart]        [... other perip on Main Board]
  58          *
  59          * Current implementation of "irq-dw-apb-ictl" driver doesn't work well
  60          * with stacked INTCs. In particular problem happens if its master INTC
  61          * not yet instantiated. See discussion here -
  62          * https://lkml.org/lkml/2015/3/4/755
  63          *
  64          * So setup the first gpio block as a passive pass thru and hide it from
  65          * DT hardware topology - connect MB intc directly to cpu intc
  66          * The GPIO "wire" needs to be init nevertheless (here)
  67          *
  68          * One side adv is that peripheral interrupt handling avoids one nested
  69          * intc ISR hop
  70          */
  71 #define GPIO_INTEN              (AXC001_GPIO_INTC + 0x30)
  72 #define GPIO_INTMASK            (AXC001_GPIO_INTC + 0x34)
  73 #define GPIO_INTTYPE_LEVEL      (AXC001_GPIO_INTC + 0x38)
  74 #define GPIO_INT_POLARITY       (AXC001_GPIO_INTC + 0x3c)
  75 #define MB_TO_GPIO_IRQ          12
  76
  77         iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK);
  78         iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL);
  79         iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY);
  80         iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);
  81 }
  82
  83 static inline void __init
  84 write_cgu_reg(uint32_t value, void __iomem *reg, void __iomem *lock_reg)
  85 {
  86         unsigned int loops = 128 * 1024, ctr;
  87
  88         iowrite32(value, reg);
  89
  90         ctr = loops;
  91         while (((ioread32(lock_reg) & 1) == 1) && ctr--) /* wait for unlock */
  92                 cpu_relax();
  93
  94         ctr = loops;
  95         while (((ioread32(lock_reg) & 1) == 0) && ctr--) /* wait for re-lock */
  96                 cpu_relax();
  97 }
  98
  99 static void __init axs10x_print_board_ver(unsigned int creg, const char *str)
 100 {
 101         union ver {
 102                 struct {
 103 #ifdef CONFIG_CPU_BIG_ENDIAN
 104                         unsigned int pad:11, y:12, m:4, d:5;
 105 #else
 106                         unsigned int d:5, m:4, y:12, pad:11;
 107 #endif
 108                 };
 109                 unsigned int val;
 110         } board;
 111
 112         board.val = ioread32((void __iomem *)creg);
 113         pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m,
 114                 board.y);
 115 }
 116
 117 static void __init axs10x_early_init(void)
 118 {
 119         int mb_rev;
 120         char mb[32];
 121
 122         /* Determine motherboard version */
 123         if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28))
 124                 mb_rev = 3;     /* HT-3 (rev3.0) */
 125         else
 126                 mb_rev = 2;     /* HT-2 (rev2.0) */
 127
 128         axs10x_enable_gpio_intc_wire();
 129
 130         scnprintf(mb, 32, "MainBoard v%d", mb_rev);
 131         axs10x_print_board_ver(CREG_MB_VER, mb);
 132 }
 133
 134 #ifdef CONFIG_AXS101
 135
 136 #define CREG_CPU_ADDR_770       (AXC001_CREG + 0x20)
 137 #define CREG_CPU_ADDR_TUNN      (AXC001_CREG + 0x60)
 138 #define CREG_CPU_ADDR_770_UPD   (AXC001_CREG + 0x34)
 139 #define CREG_CPU_ADDR_TUNN_UPD  (AXC001_CREG + 0x74)
 140
 141 #define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114)
 142 #define CREG_CPU_GPIO_UART_MUX  (AXC001_CREG + 0x120)
 143
 144 /*
 145  * Set up System Memory Map for ARC cpu / peripherals controllers
 146  *
 147  * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
 148  * of which maps to a corresponding 256MB aperture in Target slave memory map.
 149  *
 150  * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
 151  * (0x0000_0000) of DDR Port 0 (slave #1)
 152  *
 153  * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
 154  * which has master/slaves on both ends.
 155  * e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14
 156  * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
 157  * MB AXI Tunnel Master, which also has a mem map setup
 158  *
 159  * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
 160  * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
 161  */
 162 struct aperture {
 163         unsigned int slave_sel:4, slave_off:4, pad:24;
 164 };
 165
 166 /* CPU Card target slaves */
 167 #define AXC001_SLV_NONE                 0
 168 #define AXC001_SLV_DDR_PORT0            1
 169 #define AXC001_SLV_SRAM                 2
 170 #define AXC001_SLV_AXI_TUNNEL           3
 171 #define AXC001_SLV_AXI2APB              6
 172 #define AXC001_SLV_DDR_PORT1            7
 173
 174 /* MB AXI Target slaves */
 175 #define AXS_MB_SLV_NONE                 0
 176 #define AXS_MB_SLV_AXI_TUNNEL_CPU       1
 177 #define AXS_MB_SLV_AXI_TUNNEL_HAPS      2
 178 #define AXS_MB_SLV_SRAM                 3
 179 #define AXS_MB_SLV_CONTROL              4
 180
 181 /* MB AXI masters */
 182 #define AXS_MB_MST_TUNNEL_CPU           0
 183 #define AXS_MB_MST_USB_OHCI             10
 184
 185 /*
 186  * memmap for ARC core on CPU Card
 187  */
 188 static const struct aperture axc001_memmap[16] = {
 189         {AXC001_SLV_AXI_TUNNEL,         0x0},
 190         {AXC001_SLV_AXI_TUNNEL,         0x1},
 191         {AXC001_SLV_SRAM,               0x0}, /* 0x2000_0000: Local SRAM */
 192         {AXC001_SLV_NONE,               0x0},
 193         {AXC001_SLV_NONE,               0x0},
 194         {AXC001_SLV_NONE,               0x0},
 195         {AXC001_SLV_NONE,               0x0},
 196         {AXC001_SLV_NONE,               0x0},
 197         {AXC001_SLV_DDR_PORT0,          0x0}, /* 0x8000_0000: DDR   0..256M */
 198         {AXC001_SLV_DDR_PORT0,          0x1}, /* 0x9000_0000: DDR 256..512M */
 199         {AXC001_SLV_DDR_PORT0,          0x2},
 200         {AXC001_SLV_DDR_PORT0,          0x3},
 201         {AXC001_SLV_NONE,               0x0},
 202         {AXC001_SLV_AXI_TUNNEL,         0xD},
 203         {AXC001_SLV_AXI_TUNNEL,         0xE}, /* MB: CREG, CGU... */
 204         {AXC001_SLV_AXI2APB,            0x0}, /* CPU Card local CREG, CGU... */
 205 };
 206
 207 /*
 208  * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
 209  * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
 210  */
 211 static const struct aperture axc001_axi_tunnel_memmap[16] = {
 212         {AXC001_SLV_AXI_TUNNEL,         0x0},
 213         {AXC001_SLV_AXI_TUNNEL,         0x1},
 214         {AXC001_SLV_SRAM,               0x0},
 215         {AXC001_SLV_NONE,               0x0},
 216         {AXC001_SLV_NONE,               0x0},
 217         {AXC001_SLV_NONE,               0x0},
 218         {AXC001_SLV_NONE,               0x0},
 219         {AXC001_SLV_NONE,               0x0},
 220         {AXC001_SLV_DDR_PORT1,          0x0},
 221         {AXC001_SLV_DDR_PORT1,          0x1},
 222         {AXC001_SLV_DDR_PORT1,          0x2},
 223         {AXC001_SLV_DDR_PORT1,          0x3},
 224         {AXC001_SLV_NONE,               0x0},
 225         {AXC001_SLV_AXI_TUNNEL,         0xD},
 226         {AXC001_SLV_AXI_TUNNEL,         0xE},
 227         {AXC001_SLV_AXI2APB,            0x0},
 228 };
 229
 230 /*
 231  * memmap for MB AXI Masters
 232  * Same mem map for all perip controllers as well as MB AXI Tunnel Master
 233  */
 234 static const struct aperture axs_mb_memmap[16] = {
 235         {AXS_MB_SLV_SRAM,               0x0},
 236         {AXS_MB_SLV_SRAM,               0x0},
 237         {AXS_MB_SLV_NONE,               0x0},
 238         {AXS_MB_SLV_NONE,               0x0},
 239         {AXS_MB_SLV_NONE,               0x0},
 240         {AXS_MB_SLV_NONE,               0x0},
 241         {AXS_MB_SLV_NONE,               0x0},
 242         {AXS_MB_SLV_NONE,               0x0},
 243         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0x8},   /* DDR on CPU Card */
 244         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0x9},   /* DDR on CPU Card */
 245         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0xA},
 246         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0xB},
 247         {AXS_MB_SLV_NONE,               0x0},
 248         {AXS_MB_SLV_AXI_TUNNEL_HAPS,    0xD},
 249         {AXS_MB_SLV_CONTROL,            0x0},   /* MB Local CREG, CGU... */
 250         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0xF},
 251 };
 252
 253 static noinline void __init
 254 axs101_set_memmap(void __iomem *base, const struct aperture map[16])
 255 {
 256         unsigned int slave_select, slave_offset;
 257         int i;
 258
 259         slave_select = slave_offset = 0;
 260         for (i = 0; i < 8; i++) {
 261                 slave_select |= map[i].slave_sel << (i << 2);
 262                 slave_offset |= map[i].slave_off << (i << 2);
 263         }
 264
 265         iowrite32(slave_select, base + 0x0);    /* SLV0 */
 266         iowrite32(slave_offset, base + 0x8);    /* OFFSET0 */
 267
 268         slave_select = slave_offset = 0;
 269         for (i = 0; i < 8; i++) {
 270                 slave_select |= map[i+8].slave_sel << (i << 2);
 271                 slave_offset |= map[i+8].slave_off << (i << 2);
 272         }
 273
 274         iowrite32(slave_select, base + 0x4);    /* SLV1 */
 275         iowrite32(slave_offset, base + 0xC);    /* OFFSET1 */
 276 }
 277
 278 static void __init axs101_early_init(void)
 279 {
 280         int i;
 281
 282         /* ARC 770D memory view */
 283         axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap);
 284         iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD);
 285
 286         /* AXI tunnel memory map (incoming traffic from MB into CPU Card */
 287         axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN,
 288                               axc001_axi_tunnel_memmap);
 289         iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD);
 290
 291         /* MB peripherals memory map */
 292         for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++)
 293                 axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4),
 294                                       axs_mb_memmap);
 295
 296         iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */
 297
 298         /* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */
 299         iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
 300
 301         /* Set up the MB interrupt system: mux interrupts to GPIO7) */
 302         iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
 303
 304         /* reset ethernet and ULPI interfaces */
 305         iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET);
 306
 307         /* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */
 308         iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX);
 309
 310         axs10x_early_init();
 311 }
 312
 313 #endif  /* CONFIG_AXS101 */
 314
 315 #ifdef CONFIG_AXS103
 316
 317 #define AXC003_CGU      0xF0000000
 318 #define AXC003_CREG     0xF0001000
 319 #define AXC003_MST_AXI_TUNNEL   0
 320 #define AXC003_MST_HS38         1
 321
 322 #define CREG_CPU_AXI_M0_IRQ_MUX (AXC003_CREG + 0x440)
 323 #define CREG_CPU_GPIO_UART_MUX  (AXC003_CREG + 0x480)
 324 #define CREG_CPU_TUN_IO_CTRL    (AXC003_CREG + 0x494)
 325
 326
 327 union pll_reg {
 328         struct {
 329 #ifdef CONFIG_CPU_BIG_ENDIAN
 330                 unsigned int pad:17, noupd:1, bypass:1, edge:1, high:6, low:6;
 331 #else
 332                 unsigned int low:6, high:6, edge:1, bypass:1, noupd:1, pad:17;
 333 #endif
 334         };
 335         unsigned int val;
 336 };
 337
 338 static unsigned int __init axs103_get_freq(void)
 339 {
 340         union pll_reg idiv, fbdiv, odiv;
 341         unsigned int f = 33333333;
 342
 343         idiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 0);
 344         fbdiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 4);
 345         odiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 8);
 346
 347         if (idiv.bypass != 1)
 348                 f = f / (idiv.low + idiv.high);
 349
 350         if (fbdiv.bypass != 1)
 351                 f = f * (fbdiv.low + fbdiv.high);
 352
 353         if (odiv.bypass != 1)
 354                 f = f / (odiv.low + odiv.high);
 355
 356         f = (f + 500000) / 1000000; /* Rounding */
 357         return f;
 358 }
 359
 360 static inline unsigned int __init encode_div(unsigned int id, int upd)
 361 {
 362         union pll_reg div;
 363
 364         div.val = 0;
 365
 366         div.noupd = !upd;
 367         div.bypass = id == 1 ? 1 : 0;
 368         div.edge = (id%2 == 0) ? 0 : 1;  /* 0 = rising */
 369         div.low = (id%2 == 0) ? id >> 1 : (id >> 1)+1;
 370         div.high = id >> 1;
 371
 372         return div.val;
 373 }
 374
 375 noinline static void __init
 376 axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od)
 377 {
 378         write_cgu_reg(encode_div(id, 0),
 379                       (void __iomem *)AXC003_CGU + 0x80 + 0,
 380                       (void __iomem *)AXC003_CGU + 0x110);
 381
 382         write_cgu_reg(encode_div(fd, 0),
 383                       (void __iomem *)AXC003_CGU + 0x80 + 4,
 384                       (void __iomem *)AXC003_CGU + 0x110);
 385
 386         write_cgu_reg(encode_div(od, 1),
 387                       (void __iomem *)AXC003_CGU + 0x80 + 8,
 388                       (void __iomem *)AXC003_CGU + 0x110);
 389 }
 390
 391 static void __init axs103_early_init(void)
 392 {
 393         int offset = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
 394         const struct fdt_property *prop = fdt_get_property(initial_boot_params,
 395                                                            offset,
 396                                                            "clock-frequency",
 397                                                            NULL);
 398         u32 freq = be32_to_cpu(*(u32*)(prop->data)) / 1000000, orig = freq;
 399
 400         /*
 401          * AXS103 configurations for SMP/QUAD configurations share device tree
 402          * which defaults to 90 MHz. However recent failures of Quad config
 403          * revealed P&R timing violations so clamp it down to safe 50 MHz
 404          * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
 405          *
 406          * This hack is really hacky as of now. Fix it properly by getting the
 407          * number of cores as return value of platform's early SMP callback
 408          */
 409 #ifdef CONFIG_ARC_MCIP
 410         unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
 411         if (num_cores > 2)
 412                 freq = 50;
 413 #endif
 414
 415         switch (freq) {
 416         case 33:
 417                 axs103_set_freq(1, 1, 1);
 418                 break;
 419         case 50:
 420                 axs103_set_freq(1, 30, 20);
 421                 break;
 422         case 75:
 423                 axs103_set_freq(2, 45, 10);
 424                 break;
 425         case 90:
 426                 axs103_set_freq(2, 54, 10);
 427                 break;
 428         case 100:
 429                 axs103_set_freq(1, 30, 10);
 430                 break;
 431         case 125:
 432                 axs103_set_freq(2, 45,  6);
 433                 break;
 434         default:
 435                 /*
 436                  * In this case, core_frequency derived from
 437                  * DT "clock-frequency" might not match with board value.
 438                  * Hence update it to match the board value.
 439                  */
 440                 freq = axs103_get_freq();
 441                 break;
 442         }
 443
 444         pr_info("Freq is %dMHz\n", freq);
 445
 446         /* Patching .dtb in-place with new core clock value */
 447         if (freq != orig ) {
 448                 freq = cpu_to_be32(freq * 1000000);
 449                 fdt_setprop_inplace(initial_boot_params, offset,
 450                                     "clock-frequency", &freq, sizeof(freq));
 451         }
 452
 453         /* Memory maps already config in pre-bootloader */
 454
 455         /* set GPIO mux to UART */
 456         iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
 457
 458         iowrite32((0x00100000U | 0x000C0000U | 0x00003322U),
 459                   (void __iomem *) CREG_CPU_TUN_IO_CTRL);
 460
 461         /* Set up the AXS_MB interrupt system.*/
 462         iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX
 463                                          + (AXC003_MST_HS38 << 2)));
 464
 465         /* connect ICTL - Main Board with GPIO line */
 466         iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
 467
 468         axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card");
 469
 470         axs10x_early_init();
 471 }
 472 #endif
 473
 474 #ifdef CONFIG_AXS101
 475
 476 static const char *axs101_compat[] __initconst = {
 477         "snps,axs101",
 478         NULL,
 479 };
 480
 481 MACHINE_START(AXS101, "axs101")
 482         .dt_compat      = axs101_compat,
 483         .init_early     = axs101_early_init,
 484 MACHINE_END
 485
 486 #endif  /* CONFIG_AXS101 */
 487
 488 #ifdef CONFIG_AXS103
 489
 490 static const char *axs103_compat[] __initconst = {
 491         "snps,axs103",
 492         NULL,
 493 };
 494
 495 MACHINE_START(AXS103, "axs103")
 496         .dt_compat      = axs103_compat,
 497         .init_early     = axs103_early_init,
 498 MACHINE_END
 499
 500 /*
 501  * For the VDK OS-kit, to get the offset to pid and command fields
 502  */
 503 char coware_swa_pid_offset[TASK_PID];
 504 char coware_swa_comm_offset[TASK_COMM];
 505
 506 #endif  /* CONFIG_AXS103 */