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Merge tag 'chrome-platform-for-linus-4.13' of git://git.kernel.org/pub/scm/linux...
[linux/fpc-iii.git] / drivers / net / dsa / bcm_sf2.c
blob648f91b58d1e260a71de7db12dc39627bc40a35c
1 /*
2 * Broadcom Starfighter 2 DSA switch driver
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
17 #include <linux/of.h>
18 #include <linux/phy.h>
19 #include <linux/phy_fixed.h>
20 #include <linux/mii.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
26 #include <net/dsa.h>
27 #include <linux/ethtool.h>
28 #include <linux/if_bridge.h>
29 #include <linux/brcmphy.h>
30 #include <linux/etherdevice.h>
31 #include <linux/platform_data/b53.h>
32
33 #include "bcm_sf2.h"
34 #include "bcm_sf2_regs.h"
35 #include "b53/b53_priv.h"
36 #include "b53/b53_regs.h"
37
38 static enum dsa_tag_protocol bcm_sf2_sw_get_tag_protocol(struct dsa_switch *ds)
39 {
40 return DSA_TAG_PROTO_BRCM;
41 }
42
43 static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
44 {
45 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
46 unsigned int i;
47 u32 reg;
48
49 /* Enable the IMP Port to be in the same VLAN as the other ports
50 * on a per-port basis such that we only have Port i and IMP in
51 * the same VLAN.
52 */
53 for (i = 0; i < priv->hw_params.num_ports; i++) {
54 if (!((1 << i) & ds->enabled_port_mask))
55 continue;
56
57 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
58 reg |= (1 << cpu_port);
59 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
60 }
61 }
62
63 static void bcm_sf2_brcm_hdr_setup(struct bcm_sf2_priv *priv, int port)
64 {
65 u32 reg, val;
66
67 /* Resolve which bit controls the Broadcom tag */
68 switch (port) {
69 case 8:
70 val = BRCM_HDR_EN_P8;
71 break;
72 case 7:
73 val = BRCM_HDR_EN_P7;
74 break;
75 case 5:
76 val = BRCM_HDR_EN_P5;
77 break;
78 default:
79 val = 0;
80 break;
81 }
82
83 /* Enable Broadcom tags for IMP port */
84 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
85 reg |= val;
86 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
87
88 /* Enable reception Broadcom tag for CPU TX (switch RX) to
89 * allow us to tag outgoing frames
90 */
91 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
92 reg &= ~(1 << port);
93 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
94
95 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
96 * allow delivering frames to the per-port net_devices
97 */
98 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
99 reg &= ~(1 << port);
100 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
101 }
102
103 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
104 {
105 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
106 u32 reg, offset;
107
108 if (priv->type == BCM7445_DEVICE_ID)
109 offset = CORE_STS_OVERRIDE_IMP;
110 else
111 offset = CORE_STS_OVERRIDE_IMP2;
112
113 /* Enable the port memories */
114 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
115 reg &= ~P_TXQ_PSM_VDD(port);
116 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
117
118 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
119 reg = core_readl(priv, CORE_IMP_CTL);
120 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
121 reg &= ~(RX_DIS | TX_DIS);
122 core_writel(priv, reg, CORE_IMP_CTL);
123
124 /* Enable forwarding */
125 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
126
127 /* Enable IMP port in dumb mode */
128 reg = core_readl(priv, CORE_SWITCH_CTRL);
129 reg |= MII_DUMB_FWDG_EN;
130 core_writel(priv, reg, CORE_SWITCH_CTRL);
131
132 bcm_sf2_brcm_hdr_setup(priv, port);
133
134 /* Force link status for IMP port */
135 reg = core_readl(priv, offset);
136 reg |= (MII_SW_OR | LINK_STS);
137 core_writel(priv, reg, offset);
138 }
139
140 static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
141 {
142 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
143 u32 reg;
144
145 reg = core_readl(priv, CORE_EEE_EN_CTRL);
146 if (enable)
147 reg |= 1 << port;
148 else
149 reg &= ~(1 << port);
150 core_writel(priv, reg, CORE_EEE_EN_CTRL);
151 }
152
153 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
154 {
155 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
156 u32 reg;
157
158 reg = reg_readl(priv, REG_SPHY_CNTRL);
159 if (enable) {
160 reg |= PHY_RESET;
161 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
162 reg_writel(priv, reg, REG_SPHY_CNTRL);
163 udelay(21);
164 reg = reg_readl(priv, REG_SPHY_CNTRL);
165 reg &= ~PHY_RESET;
166 } else {
167 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
168 reg_writel(priv, reg, REG_SPHY_CNTRL);
169 mdelay(1);
170 reg |= CK25_DIS;
171 }
172 reg_writel(priv, reg, REG_SPHY_CNTRL);
173
174 /* Use PHY-driven LED signaling */
175 if (!enable) {
176 reg = reg_readl(priv, REG_LED_CNTRL(0));
177 reg |= SPDLNK_SRC_SEL;
178 reg_writel(priv, reg, REG_LED_CNTRL(0));
179 }
180 }
181
182 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
183 int port)
184 {
185 unsigned int off;
186
187 switch (port) {
188 case 7:
189 off = P7_IRQ_OFF;
190 break;
191 case 0:
192 /* Port 0 interrupts are located on the first bank */
193 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
194 return;
195 default:
196 off = P_IRQ_OFF(port);
197 break;
198 }
199
200 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
201 }
202
203 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
204 int port)
205 {
206 unsigned int off;
207
208 switch (port) {
209 case 7:
210 off = P7_IRQ_OFF;
211 break;
212 case 0:
213 /* Port 0 interrupts are located on the first bank */
214 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
215 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
216 return;
217 default:
218 off = P_IRQ_OFF(port);
219 break;
220 }
221
222 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
223 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
224 }
225
226 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
227 struct phy_device *phy)
228 {
229 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
230 s8 cpu_port = ds->dst->cpu_dp->index;
231 unsigned int i;
232 u32 reg;
233
234 /* Clear the memory power down */
235 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
236 reg &= ~P_TXQ_PSM_VDD(port);
237 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
238
239 /* Enable Broadcom tags for that port if requested */
240 if (priv->brcm_tag_mask & BIT(port))
241 bcm_sf2_brcm_hdr_setup(priv, port);
242
243 /* Configure Traffic Class to QoS mapping, allow each priority to map
244 * to a different queue number
245 */
246 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
247 for (i = 0; i < 8; i++)
248 reg |= i << (PRT_TO_QID_SHIFT * i);
249 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
250
251 /* Clear the Rx and Tx disable bits and set to no spanning tree */
252 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
253
254 /* Re-enable the GPHY and re-apply workarounds */
255 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
256 bcm_sf2_gphy_enable_set(ds, true);
257 if (phy) {
258 /* if phy_stop() has been called before, phy
259 * will be in halted state, and phy_start()
260 * will call resume.
261 *
262 * the resume path does not configure back
263 * autoneg settings, and since we hard reset
264 * the phy manually here, we need to reset the
265 * state machine also.
266 */
267 phy->state = PHY_READY;
268 phy_init_hw(phy);
269 }
270 }
271
272 /* Enable MoCA port interrupts to get notified */
273 if (port == priv->moca_port)
274 bcm_sf2_port_intr_enable(priv, port);
275
276 /* Set this port, and only this one to be in the default VLAN,
277 * if member of a bridge, restore its membership prior to
278 * bringing down this port.
279 */
280 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
281 reg &= ~PORT_VLAN_CTRL_MASK;
282 reg |= (1 << port);
283 reg |= priv->dev->ports[port].vlan_ctl_mask;
284 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
285
286 bcm_sf2_imp_vlan_setup(ds, cpu_port);
287
288 /* If EEE was enabled, restore it */
289 if (priv->port_sts[port].eee.eee_enabled)
290 bcm_sf2_eee_enable_set(ds, port, true);
291
292 return 0;
293 }
294
295 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
296 struct phy_device *phy)
297 {
298 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
299 u32 off, reg;
300
301 if (priv->wol_ports_mask & (1 << port))
302 return;
303
304 if (port == priv->moca_port)
305 bcm_sf2_port_intr_disable(priv, port);
306
307 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
308 bcm_sf2_gphy_enable_set(ds, false);
309
310 if (dsa_is_cpu_port(ds, port))
311 off = CORE_IMP_CTL;
312 else
313 off = CORE_G_PCTL_PORT(port);
314
315 reg = core_readl(priv, off);
316 reg |= RX_DIS | TX_DIS;
317 core_writel(priv, reg, off);
318
319 /* Power down the port memory */
320 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
321 reg |= P_TXQ_PSM_VDD(port);
322 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
323 }
324
325 /* Returns 0 if EEE was not enabled, or 1 otherwise
326 */
327 static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
328 struct phy_device *phy)
329 {
330 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
331 struct ethtool_eee *p = &priv->port_sts[port].eee;
332 int ret;
333
334 p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
335
336 ret = phy_init_eee(phy, 0);
337 if (ret)
338 return 0;
339
340 bcm_sf2_eee_enable_set(ds, port, true);
341
342 return 1;
343 }
344
345 static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
346 struct ethtool_eee *e)
347 {
348 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
349 struct ethtool_eee *p = &priv->port_sts[port].eee;
350 u32 reg;
351
352 reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
353 e->eee_enabled = p->eee_enabled;
354 e->eee_active = !!(reg & (1 << port));
355
356 return 0;
357 }
358
359 static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
360 struct phy_device *phydev,
361 struct ethtool_eee *e)
362 {
363 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
364 struct ethtool_eee *p = &priv->port_sts[port].eee;
365
366 p->eee_enabled = e->eee_enabled;
367
368 if (!p->eee_enabled) {
369 bcm_sf2_eee_enable_set(ds, port, false);
370 } else {
371 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
372 if (!p->eee_enabled)
373 return -EOPNOTSUPP;
374 }
375
376 return 0;
377 }
378
379 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
380 int regnum, u16 val)
381 {
382 int ret = 0;
383 u32 reg;
384
385 reg = reg_readl(priv, REG_SWITCH_CNTRL);
386 reg |= MDIO_MASTER_SEL;
387 reg_writel(priv, reg, REG_SWITCH_CNTRL);
388
389 /* Page << 8 | offset */
390 reg = 0x70;
391 reg <<= 2;
392 core_writel(priv, addr, reg);
393
394 /* Page << 8 | offset */
395 reg = 0x80 << 8 | regnum << 1;
396 reg <<= 2;
397
398 if (op)
399 ret = core_readl(priv, reg);
400 else
401 core_writel(priv, val, reg);
402
403 reg = reg_readl(priv, REG_SWITCH_CNTRL);
404 reg &= ~MDIO_MASTER_SEL;
405 reg_writel(priv, reg, REG_SWITCH_CNTRL);
406
407 return ret & 0xffff;
408 }
409
410 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
411 {
412 struct bcm_sf2_priv *priv = bus->priv;
413
414 /* Intercept reads from Broadcom pseudo-PHY address, else, send
415 * them to our master MDIO bus controller
416 */
417 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
418 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
419 else
420 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
421 }
422
423 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
424 u16 val)
425 {
426 struct bcm_sf2_priv *priv = bus->priv;
427
428 /* Intercept writes to the Broadcom pseudo-PHY address, else,
429 * send them to our master MDIO bus controller
430 */
431 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
432 bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
433 else
434 mdiobus_write_nested(priv->master_mii_bus, addr, regnum, val);
435
436 return 0;
437 }
438
439 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
440 {
441 struct bcm_sf2_priv *priv = dev_id;
442
443 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
444 ~priv->irq0_mask;
445 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
446
447 return IRQ_HANDLED;
448 }
449
450 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
451 {
452 struct bcm_sf2_priv *priv = dev_id;
453
454 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
455 ~priv->irq1_mask;
456 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
457
458 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
459 priv->port_sts[7].link = 1;
460 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
461 priv->port_sts[7].link = 0;
462
463 return IRQ_HANDLED;
464 }
465
466 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
467 {
468 unsigned int timeout = 1000;
469 u32 reg;
470
471 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
472 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
473 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
474
475 do {
476 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
477 if (!(reg & SOFTWARE_RESET))
478 break;
479
480 usleep_range(1000, 2000);
481 } while (timeout-- > 0);
482
483 if (timeout == 0)
484 return -ETIMEDOUT;
485
486 return 0;
487 }
488
489 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
490 {
491 intrl2_0_mask_set(priv, 0xffffffff);
492 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
493 intrl2_1_mask_set(priv, 0xffffffff);
494 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
495 }
496
497 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
498 struct device_node *dn)
499 {
500 struct device_node *port;
501 int mode;
502 unsigned int port_num;
503
504 priv->moca_port = -1;
505
506 for_each_available_child_of_node(dn, port) {
507 if (of_property_read_u32(port, "reg", &port_num))
508 continue;
509
510 /* Internal PHYs get assigned a specific 'phy-mode' property
511 * value: "internal" to help flag them before MDIO probing
512 * has completed, since they might be turned off at that
513 * time
514 */
515 mode = of_get_phy_mode(port);
516 if (mode < 0)
517 continue;
518
519 if (mode == PHY_INTERFACE_MODE_INTERNAL)
520 priv->int_phy_mask |= 1 << port_num;
521
522 if (mode == PHY_INTERFACE_MODE_MOCA)
523 priv->moca_port = port_num;
524
525 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
526 priv->brcm_tag_mask |= 1 << port_num;
527 }
528 }
529
530 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
531 {
532 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
533 struct device_node *dn;
534 static int index;
535 int err;
536
537 /* Find our integrated MDIO bus node */
538 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
539 priv->master_mii_bus = of_mdio_find_bus(dn);
540 if (!priv->master_mii_bus)
541 return -EPROBE_DEFER;
542
543 get_device(&priv->master_mii_bus->dev);
544 priv->master_mii_dn = dn;
545
546 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
547 if (!priv->slave_mii_bus)
548 return -ENOMEM;
549
550 priv->slave_mii_bus->priv = priv;
551 priv->slave_mii_bus->name = "sf2 slave mii";
552 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
553 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
554 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
555 index++);
556 priv->slave_mii_bus->dev.of_node = dn;
557
558 /* Include the pseudo-PHY address to divert reads towards our
559 * workaround. This is only required for 7445D0, since 7445E0
560 * disconnects the internal switch pseudo-PHY such that we can use the
561 * regular SWITCH_MDIO master controller instead.
562 *
563 * Here we flag the pseudo PHY as needing special treatment and would
564 * otherwise make all other PHY read/writes go to the master MDIO bus
565 * controller that comes with this switch backed by the "mdio-unimac"
566 * driver.
567 */
568 if (of_machine_is_compatible("brcm,bcm7445d0"))
569 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
570 else
571 priv->indir_phy_mask = 0;
572
573 ds->phys_mii_mask = priv->indir_phy_mask;
574 ds->slave_mii_bus = priv->slave_mii_bus;
575 priv->slave_mii_bus->parent = ds->dev->parent;
576 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
577
578 if (dn)
579 err = of_mdiobus_register(priv->slave_mii_bus, dn);
580 else
581 err = mdiobus_register(priv->slave_mii_bus);
582
583 if (err)
584 of_node_put(dn);
585
586 return err;
587 }
588
589 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
590 {
591 mdiobus_unregister(priv->slave_mii_bus);
592 if (priv->master_mii_dn)
593 of_node_put(priv->master_mii_dn);
594 }
595
596 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
597 {
598 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
599
600 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
601 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
602 * the REG_PHY_REVISION register layout is.
603 */
604
605 return priv->hw_params.gphy_rev;
606 }
607
608 static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
609 struct phy_device *phydev)
610 {
611 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
612 struct ethtool_eee *p = &priv->port_sts[port].eee;
613 u32 id_mode_dis = 0, port_mode;
614 const char *str = NULL;
615 u32 reg, offset;
616
617 if (priv->type == BCM7445_DEVICE_ID)
618 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
619 else
620 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
621
622 switch (phydev->interface) {
623 case PHY_INTERFACE_MODE_RGMII:
624 str = "RGMII (no delay)";
625 id_mode_dis = 1;
626 case PHY_INTERFACE_MODE_RGMII_TXID:
627 if (!str)
628 str = "RGMII (TX delay)";
629 port_mode = EXT_GPHY;
630 break;
631 case PHY_INTERFACE_MODE_MII:
632 str = "MII";
633 port_mode = EXT_EPHY;
634 break;
635 case PHY_INTERFACE_MODE_REVMII:
636 str = "Reverse MII";
637 port_mode = EXT_REVMII;
638 break;
639 default:
640 /* All other PHYs: internal and MoCA */
641 goto force_link;
642 }
643
644 /* If the link is down, just disable the interface to conserve power */
645 if (!phydev->link) {
646 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
647 reg &= ~RGMII_MODE_EN;
648 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
649 goto force_link;
650 }
651
652 /* Clear id_mode_dis bit, and the existing port mode, but
653 * make sure we enable the RGMII block for data to pass
654 */
655 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
656 reg &= ~ID_MODE_DIS;
657 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
658 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
659
660 reg |= port_mode | RGMII_MODE_EN;
661 if (id_mode_dis)
662 reg |= ID_MODE_DIS;
663
664 if (phydev->pause) {
665 if (phydev->asym_pause)
666 reg |= TX_PAUSE_EN;
667 reg |= RX_PAUSE_EN;
668 }
669
670 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
671
672 pr_info("Port %d configured for %s\n", port, str);
673
674 force_link:
675 /* Force link settings detected from the PHY */
676 reg = SW_OVERRIDE;
677 switch (phydev->speed) {
678 case SPEED_1000:
679 reg |= SPDSTS_1000 << SPEED_SHIFT;
680 break;
681 case SPEED_100:
682 reg |= SPDSTS_100 << SPEED_SHIFT;
683 break;
684 }
685
686 if (phydev->link)
687 reg |= LINK_STS;
688 if (phydev->duplex == DUPLEX_FULL)
689 reg |= DUPLX_MODE;
690
691 core_writel(priv, reg, offset);
692
693 if (!phydev->is_pseudo_fixed_link)
694 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
695 }
696
697 static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
698 struct fixed_phy_status *status)
699 {
700 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
701 u32 duplex, pause, offset;
702 u32 reg;
703
704 if (priv->type == BCM7445_DEVICE_ID)
705 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
706 else
707 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
708
709 duplex = core_readl(priv, CORE_DUPSTS);
710 pause = core_readl(priv, CORE_PAUSESTS);
711
712 status->link = 0;
713
714 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
715 * which means that we need to force the link at the port override
716 * level to get the data to flow. We do use what the interrupt handler
717 * did determine before.
718 *
719 * For the other ports, we just force the link status, since this is
720 * a fixed PHY device.
721 */
722 if (port == priv->moca_port) {
723 status->link = priv->port_sts[port].link;
724 /* For MoCA interfaces, also force a link down notification
725 * since some version of the user-space daemon (mocad) use
726 * cmd->autoneg to force the link, which messes up the PHY
727 * state machine and make it go in PHY_FORCING state instead.
728 */
729 if (!status->link)
730 netif_carrier_off(ds->ports[port].netdev);
731 status->duplex = 1;
732 } else {
733 status->link = 1;
734 status->duplex = !!(duplex & (1 << port));
735 }
736
737 reg = core_readl(priv, offset);
738 reg |= SW_OVERRIDE;
739 if (status->link)
740 reg |= LINK_STS;
741 else
742 reg &= ~LINK_STS;
743 core_writel(priv, reg, offset);
744
745 if ((pause & (1 << port)) &&
746 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
747 status->asym_pause = 1;
748 status->pause = 1;
749 }
750
751 if (pause & (1 << port))
752 status->pause = 1;
753 }
754
755 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
756 {
757 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
758 unsigned int port;
759
760 bcm_sf2_intr_disable(priv);
761
762 /* Disable all ports physically present including the IMP
763 * port, the other ones have already been disabled during
764 * bcm_sf2_sw_setup
765 */
766 for (port = 0; port < DSA_MAX_PORTS; port++) {
767 if ((1 << port) & ds->enabled_port_mask ||
768 dsa_is_cpu_port(ds, port))
769 bcm_sf2_port_disable(ds, port, NULL);
770 }
771
772 return 0;
773 }
774
775 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
776 {
777 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
778 unsigned int port;
779 int ret;
780
781 ret = bcm_sf2_sw_rst(priv);
782 if (ret) {
783 pr_err("%s: failed to software reset switch\n", __func__);
784 return ret;
785 }
786
787 if (priv->hw_params.num_gphy == 1)
788 bcm_sf2_gphy_enable_set(ds, true);
789
790 for (port = 0; port < DSA_MAX_PORTS; port++) {
791 if ((1 << port) & ds->enabled_port_mask)
792 bcm_sf2_port_setup(ds, port, NULL);
793 else if (dsa_is_cpu_port(ds, port))
794 bcm_sf2_imp_setup(ds, port);
795 }
796
797 return 0;
798 }
799
800 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
801 struct ethtool_wolinfo *wol)
802 {
803 struct net_device *p = ds->dst[ds->index].cpu_dp->netdev;
804 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
805 struct ethtool_wolinfo pwol;
806
807 /* Get the parent device WoL settings */
808 p->ethtool_ops->get_wol(p, &pwol);
809
810 /* Advertise the parent device supported settings */
811 wol->supported = pwol.supported;
812 memset(&wol->sopass, 0, sizeof(wol->sopass));
813
814 if (pwol.wolopts & WAKE_MAGICSECURE)
815 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
816
817 if (priv->wol_ports_mask & (1 << port))
818 wol->wolopts = pwol.wolopts;
819 else
820 wol->wolopts = 0;
821 }
822
823 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
824 struct ethtool_wolinfo *wol)
825 {
826 struct net_device *p = ds->dst[ds->index].cpu_dp->netdev;
827 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
828 s8 cpu_port = ds->dst->cpu_dp->index;
829 struct ethtool_wolinfo pwol;
830
831 p->ethtool_ops->get_wol(p, &pwol);
832 if (wol->wolopts & ~pwol.supported)
833 return -EINVAL;
834
835 if (wol->wolopts)
836 priv->wol_ports_mask |= (1 << port);
837 else
838 priv->wol_ports_mask &= ~(1 << port);
839
840 /* If we have at least one port enabled, make sure the CPU port
841 * is also enabled. If the CPU port is the last one enabled, we disable
842 * it since this configuration does not make sense.
843 */
844 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
845 priv->wol_ports_mask |= (1 << cpu_port);
846 else
847 priv->wol_ports_mask &= ~(1 << cpu_port);
848
849 return p->ethtool_ops->set_wol(p, wol);
850 }
851
852 static int bcm_sf2_vlan_op_wait(struct bcm_sf2_priv *priv)
853 {
854 unsigned int timeout = 10;
855 u32 reg;
856
857 do {
858 reg = core_readl(priv, CORE_ARLA_VTBL_RWCTRL);
859 if (!(reg & ARLA_VTBL_STDN))
860 return 0;
861
862 usleep_range(1000, 2000);
863 } while (timeout--);
864
865 return -ETIMEDOUT;
866 }
867
868 static int bcm_sf2_vlan_op(struct bcm_sf2_priv *priv, u8 op)
869 {
870 core_writel(priv, ARLA_VTBL_STDN | op, CORE_ARLA_VTBL_RWCTRL);
871
872 return bcm_sf2_vlan_op_wait(priv);
873 }
874
875 static void bcm_sf2_sw_configure_vlan(struct dsa_switch *ds)
876 {
877 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
878 unsigned int port;
879
880 /* Clear all VLANs */
881 bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_CLEAR);
882
883 for (port = 0; port < priv->hw_params.num_ports; port++) {
884 if (!((1 << port) & ds->enabled_port_mask))
885 continue;
886
887 core_writel(priv, 1, CORE_DEFAULT_1Q_TAG_P(port));
888 }
889 }
890
891 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
892 {
893 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
894 unsigned int port;
895
896 /* Enable all valid ports and disable those unused */
897 for (port = 0; port < priv->hw_params.num_ports; port++) {
898 /* IMP port receives special treatment */
899 if ((1 << port) & ds->enabled_port_mask)
900 bcm_sf2_port_setup(ds, port, NULL);
901 else if (dsa_is_cpu_port(ds, port))
902 bcm_sf2_imp_setup(ds, port);
903 else
904 bcm_sf2_port_disable(ds, port, NULL);
905 }
906
907 bcm_sf2_sw_configure_vlan(ds);
908
909 return 0;
910 }
911
912 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
913 * register basis so we need to translate that into an address that the
914 * bus-glue understands.
915 */
916 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
917
918 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
919 u8 *val)
920 {
921 struct bcm_sf2_priv *priv = dev->priv;
922
923 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
924
925 return 0;
926 }
927
928 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
929 u16 *val)
930 {
931 struct bcm_sf2_priv *priv = dev->priv;
932
933 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
934
935 return 0;
936 }
937
938 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
939 u32 *val)
940 {
941 struct bcm_sf2_priv *priv = dev->priv;
942
943 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
944
945 return 0;
946 }
947
948 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
949 u64 *val)
950 {
951 struct bcm_sf2_priv *priv = dev->priv;
952
953 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
954
955 return 0;
956 }
957
958 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
959 u8 value)
960 {
961 struct bcm_sf2_priv *priv = dev->priv;
962
963 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
964
965 return 0;
966 }
967
968 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
969 u16 value)
970 {
971 struct bcm_sf2_priv *priv = dev->priv;
972
973 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
974
975 return 0;
976 }
977
978 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
979 u32 value)
980 {
981 struct bcm_sf2_priv *priv = dev->priv;
982
983 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
984
985 return 0;
986 }
987
988 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
989 u64 value)
990 {
991 struct bcm_sf2_priv *priv = dev->priv;
992
993 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
994
995 return 0;
996 }
997
998 static struct b53_io_ops bcm_sf2_io_ops = {
999 .read8 = bcm_sf2_core_read8,
1000 .read16 = bcm_sf2_core_read16,
1001 .read32 = bcm_sf2_core_read32,
1002 .read48 = bcm_sf2_core_read64,
1003 .read64 = bcm_sf2_core_read64,
1004 .write8 = bcm_sf2_core_write8,
1005 .write16 = bcm_sf2_core_write16,
1006 .write32 = bcm_sf2_core_write32,
1007 .write48 = bcm_sf2_core_write64,
1008 .write64 = bcm_sf2_core_write64,
1009 };
1010
1011 static const struct dsa_switch_ops bcm_sf2_ops = {
1012 .get_tag_protocol = bcm_sf2_sw_get_tag_protocol,
1013 .setup = bcm_sf2_sw_setup,
1014 .get_strings = b53_get_strings,
1015 .get_ethtool_stats = b53_get_ethtool_stats,
1016 .get_sset_count = b53_get_sset_count,
1017 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1018 .adjust_link = bcm_sf2_sw_adjust_link,
1019 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
1020 .suspend = bcm_sf2_sw_suspend,
1021 .resume = bcm_sf2_sw_resume,
1022 .get_wol = bcm_sf2_sw_get_wol,
1023 .set_wol = bcm_sf2_sw_set_wol,
1024 .port_enable = bcm_sf2_port_setup,
1025 .port_disable = bcm_sf2_port_disable,
1026 .get_eee = bcm_sf2_sw_get_eee,
1027 .set_eee = bcm_sf2_sw_set_eee,
1028 .port_bridge_join = b53_br_join,
1029 .port_bridge_leave = b53_br_leave,
1030 .port_stp_state_set = b53_br_set_stp_state,
1031 .port_fast_age = b53_br_fast_age,
1032 .port_vlan_filtering = b53_vlan_filtering,
1033 .port_vlan_prepare = b53_vlan_prepare,
1034 .port_vlan_add = b53_vlan_add,
1035 .port_vlan_del = b53_vlan_del,
1036 .port_vlan_dump = b53_vlan_dump,
1037 .port_fdb_prepare = b53_fdb_prepare,
1038 .port_fdb_dump = b53_fdb_dump,
1039 .port_fdb_add = b53_fdb_add,
1040 .port_fdb_del = b53_fdb_del,
1041 .get_rxnfc = bcm_sf2_get_rxnfc,
1042 .set_rxnfc = bcm_sf2_set_rxnfc,
1043 .port_mirror_add = b53_mirror_add,
1044 .port_mirror_del = b53_mirror_del,
1045 };
1046
1047 struct bcm_sf2_of_data {
1048 u32 type;
1049 const u16 *reg_offsets;
1050 unsigned int core_reg_align;
1051 };
1052
1053 /* Register offsets for the SWITCH_REG_* block */
1054 static const u16 bcm_sf2_7445_reg_offsets[] = {
1055 [REG_SWITCH_CNTRL] = 0x00,
1056 [REG_SWITCH_STATUS] = 0x04,
1057 [REG_DIR_DATA_WRITE] = 0x08,
1058 [REG_DIR_DATA_READ] = 0x0C,
1059 [REG_SWITCH_REVISION] = 0x18,
1060 [REG_PHY_REVISION] = 0x1C,
1061 [REG_SPHY_CNTRL] = 0x2C,
1062 [REG_RGMII_0_CNTRL] = 0x34,
1063 [REG_RGMII_1_CNTRL] = 0x40,
1064 [REG_RGMII_2_CNTRL] = 0x4c,
1065 [REG_LED_0_CNTRL] = 0x90,
1066 [REG_LED_1_CNTRL] = 0x94,
1067 [REG_LED_2_CNTRL] = 0x98,
1068 };
1069
1070 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1071 .type = BCM7445_DEVICE_ID,
1072 .core_reg_align = 0,
1073 .reg_offsets = bcm_sf2_7445_reg_offsets,
1074 };
1075
1076 static const u16 bcm_sf2_7278_reg_offsets[] = {
1077 [REG_SWITCH_CNTRL] = 0x00,
1078 [REG_SWITCH_STATUS] = 0x04,
1079 [REG_DIR_DATA_WRITE] = 0x08,
1080 [REG_DIR_DATA_READ] = 0x0c,
1081 [REG_SWITCH_REVISION] = 0x10,
1082 [REG_PHY_REVISION] = 0x14,
1083 [REG_SPHY_CNTRL] = 0x24,
1084 [REG_RGMII_0_CNTRL] = 0xe0,
1085 [REG_RGMII_1_CNTRL] = 0xec,
1086 [REG_RGMII_2_CNTRL] = 0xf8,
1087 [REG_LED_0_CNTRL] = 0x40,
1088 [REG_LED_1_CNTRL] = 0x4c,
1089 [REG_LED_2_CNTRL] = 0x58,
1090 };
1091
1092 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1093 .type = BCM7278_DEVICE_ID,
1094 .core_reg_align = 1,
1095 .reg_offsets = bcm_sf2_7278_reg_offsets,
1096 };
1097
1098 static const struct of_device_id bcm_sf2_of_match[] = {
1099 { .compatible = "brcm,bcm7445-switch-v4.0",
1100 .data = &bcm_sf2_7445_data
1101 },
1102 { .compatible = "brcm,bcm7278-switch-v4.0",
1103 .data = &bcm_sf2_7278_data
1104 },
1105 { /* sentinel */ },
1106 };
1107 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1108
1109 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1110 {
1111 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1112 struct device_node *dn = pdev->dev.of_node;
1113 const struct of_device_id *of_id = NULL;
1114 const struct bcm_sf2_of_data *data;
1115 struct b53_platform_data *pdata;
1116 struct dsa_switch_ops *ops;
1117 struct bcm_sf2_priv *priv;
1118 struct b53_device *dev;
1119 struct dsa_switch *ds;
1120 void __iomem **base;
1121 struct resource *r;
1122 unsigned int i;
1123 u32 reg, rev;
1124 int ret;
1125
1126 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1127 if (!priv)
1128 return -ENOMEM;
1129
1130 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1131 if (!ops)
1132 return -ENOMEM;
1133
1134 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1135 if (!dev)
1136 return -ENOMEM;
1137
1138 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1139 if (!pdata)
1140 return -ENOMEM;
1141
1142 of_id = of_match_node(bcm_sf2_of_match, dn);
1143 if (!of_id || !of_id->data)
1144 return -EINVAL;
1145
1146 data = of_id->data;
1147
1148 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1149 priv->type = data->type;
1150 priv->reg_offsets = data->reg_offsets;
1151 priv->core_reg_align = data->core_reg_align;
1152
1153 /* Auto-detection using standard registers will not work, so
1154 * provide an indication of what kind of device we are for
1155 * b53_common to work with
1156 */
1157 pdata->chip_id = priv->type;
1158 dev->pdata = pdata;
1159
1160 priv->dev = dev;
1161 ds = dev->ds;
1162 ds->ops = &bcm_sf2_ops;
1163
1164 dev_set_drvdata(&pdev->dev, priv);
1165
1166 spin_lock_init(&priv->indir_lock);
1167 mutex_init(&priv->stats_mutex);
1168 mutex_init(&priv->cfp.lock);
1169
1170 /* CFP rule #0 cannot be used for specific classifications, flag it as
1171 * permanently used
1172 */
1173 set_bit(0, priv->cfp.used);
1174
1175 bcm_sf2_identify_ports(priv, dn->child);
1176
1177 priv->irq0 = irq_of_parse_and_map(dn, 0);
1178 priv->irq1 = irq_of_parse_and_map(dn, 1);
1179
1180 base = &priv->core;
1181 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1182 r = platform_get_resource(pdev, IORESOURCE_MEM, i);
1183 *base = devm_ioremap_resource(&pdev->dev, r);
1184 if (IS_ERR(*base)) {
1185 pr_err("unable to find register: %s\n", reg_names[i]);
1186 return PTR_ERR(*base);
1187 }
1188 base++;
1189 }
1190
1191 ret = bcm_sf2_sw_rst(priv);
1192 if (ret) {
1193 pr_err("unable to software reset switch: %d\n", ret);
1194 return ret;
1195 }
1196
1197 ret = bcm_sf2_mdio_register(ds);
1198 if (ret) {
1199 pr_err("failed to register MDIO bus\n");
1200 return ret;
1201 }
1202
1203 ret = bcm_sf2_cfp_rst(priv);
1204 if (ret) {
1205 pr_err("failed to reset CFP\n");
1206 goto out_mdio;
1207 }
1208
1209 /* Disable all interrupts and request them */
1210 bcm_sf2_intr_disable(priv);
1211
1212 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1213 "switch_0", priv);
1214 if (ret < 0) {
1215 pr_err("failed to request switch_0 IRQ\n");
1216 goto out_mdio;
1217 }
1218
1219 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1220 "switch_1", priv);
1221 if (ret < 0) {
1222 pr_err("failed to request switch_1 IRQ\n");
1223 goto out_mdio;
1224 }
1225
1226 /* Reset the MIB counters */
1227 reg = core_readl(priv, CORE_GMNCFGCFG);
1228 reg |= RST_MIB_CNT;
1229 core_writel(priv, reg, CORE_GMNCFGCFG);
1230 reg &= ~RST_MIB_CNT;
1231 core_writel(priv, reg, CORE_GMNCFGCFG);
1232
1233 /* Get the maximum number of ports for this switch */
1234 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1235 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1236 priv->hw_params.num_ports = DSA_MAX_PORTS;
1237
1238 /* Assume a single GPHY setup if we can't read that property */
1239 if (of_property_read_u32(dn, "brcm,num-gphy",
1240 &priv->hw_params.num_gphy))
1241 priv->hw_params.num_gphy = 1;
1242
1243 rev = reg_readl(priv, REG_SWITCH_REVISION);
1244 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1245 SWITCH_TOP_REV_MASK;
1246 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1247
1248 rev = reg_readl(priv, REG_PHY_REVISION);
1249 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1250
1251 ret = b53_switch_register(dev);
1252 if (ret)
1253 goto out_mdio;
1254
1255 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1256 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1257 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1258 priv->core, priv->irq0, priv->irq1);
1259
1260 return 0;
1261
1262 out_mdio:
1263 bcm_sf2_mdio_unregister(priv);
1264 return ret;
1265 }
1266
1267 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1268 {
1269 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1270
1271 /* Disable all ports and interrupts */
1272 priv->wol_ports_mask = 0;
1273 bcm_sf2_sw_suspend(priv->dev->ds);
1274 dsa_unregister_switch(priv->dev->ds);
1275 bcm_sf2_mdio_unregister(priv);
1276
1277 return 0;
1278 }
1279
1280 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1281 {
1282 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1283
1284 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1285 * successful MDIO bus scan to occur. If we did turn off the GPHY
1286 * before (e.g: port_disable), this will also power it back on.
1287 *
1288 * Do not rely on kexec_in_progress, just power the PHY on.
1289 */
1290 if (priv->hw_params.num_gphy == 1)
1291 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1292 }
1293
1294 #ifdef CONFIG_PM_SLEEP
1295 static int bcm_sf2_suspend(struct device *dev)
1296 {
1297 struct platform_device *pdev = to_platform_device(dev);
1298 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1299
1300 return dsa_switch_suspend(priv->dev->ds);
1301 }
1302
1303 static int bcm_sf2_resume(struct device *dev)
1304 {
1305 struct platform_device *pdev = to_platform_device(dev);
1306 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1307
1308 return dsa_switch_resume(priv->dev->ds);
1309 }
1310 #endif /* CONFIG_PM_SLEEP */
1311
1312 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1313 bcm_sf2_suspend, bcm_sf2_resume);
1314
1315
1316 static struct platform_driver bcm_sf2_driver = {
1317 .probe = bcm_sf2_sw_probe,
1318 .remove = bcm_sf2_sw_remove,
1319 .shutdown = bcm_sf2_sw_shutdown,
1320 .driver = {
1321 .name = "brcm-sf2",
1322 .of_match_table = bcm_sf2_of_match,
1323 .pm = &bcm_sf2_pm_ops,
1324 },
1325 };
1326 module_platform_driver(bcm_sf2_driver);
1327
1328 MODULE_AUTHOR("Broadcom Corporation");
1329 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1330 MODULE_LICENSE("GPL");
1331 MODULE_ALIAS("platform:brcm-sf2");
Linux with added FPC-III support