drivers/net/ethernet/amazon/ena/ena_regs_defs.h

   1 /*
   2  * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef _ENA_REGS_H_
  33 #define _ENA_REGS_H_
  34
  35 enum ena_regs_reset_reason_types {
  36         ENA_REGS_RESET_NORMAL                   = 0,
  37
  38         ENA_REGS_RESET_KEEP_ALIVE_TO            = 1,
  39
  40         ENA_REGS_RESET_ADMIN_TO                 = 2,
  41
  42         ENA_REGS_RESET_MISS_TX_CMPL             = 3,
  43
  44         ENA_REGS_RESET_INV_RX_REQ_ID            = 4,
  45
  46         ENA_REGS_RESET_INV_TX_REQ_ID            = 5,
  47
  48         ENA_REGS_RESET_TOO_MANY_RX_DESCS        = 6,
  49
  50         ENA_REGS_RESET_INIT_ERR                 = 7,
  51
  52         ENA_REGS_RESET_DRIVER_INVALID_STATE     = 8,
  53
  54         ENA_REGS_RESET_OS_TRIGGER               = 9,
  55
  56         ENA_REGS_RESET_OS_NETDEV_WD             = 10,
  57
  58         ENA_REGS_RESET_SHUTDOWN                 = 11,
  59
  60         ENA_REGS_RESET_USER_TRIGGER             = 12,
  61
  62         ENA_REGS_RESET_GENERIC                  = 13,
  63 };
  64
  65 /* ena_registers offsets */
  66 #define ENA_REGS_VERSION_OFF            0x0
  67 #define ENA_REGS_CONTROLLER_VERSION_OFF         0x4
  68 #define ENA_REGS_CAPS_OFF               0x8
  69 #define ENA_REGS_CAPS_EXT_OFF           0xc
  70 #define ENA_REGS_AQ_BASE_LO_OFF         0x10
  71 #define ENA_REGS_AQ_BASE_HI_OFF         0x14
  72 #define ENA_REGS_AQ_CAPS_OFF            0x18
  73 #define ENA_REGS_ACQ_BASE_LO_OFF                0x20
  74 #define ENA_REGS_ACQ_BASE_HI_OFF                0x24
  75 #define ENA_REGS_ACQ_CAPS_OFF           0x28
  76 #define ENA_REGS_AQ_DB_OFF              0x2c
  77 #define ENA_REGS_ACQ_TAIL_OFF           0x30
  78 #define ENA_REGS_AENQ_CAPS_OFF          0x34
  79 #define ENA_REGS_AENQ_BASE_LO_OFF               0x38
  80 #define ENA_REGS_AENQ_BASE_HI_OFF               0x3c
  81 #define ENA_REGS_AENQ_HEAD_DB_OFF               0x40
  82 #define ENA_REGS_AENQ_TAIL_OFF          0x44
  83 #define ENA_REGS_INTR_MASK_OFF          0x4c
  84 #define ENA_REGS_DEV_CTL_OFF            0x54
  85 #define ENA_REGS_DEV_STS_OFF            0x58
  86 #define ENA_REGS_MMIO_REG_READ_OFF              0x5c
  87 #define ENA_REGS_MMIO_RESP_LO_OFF               0x60
  88 #define ENA_REGS_MMIO_RESP_HI_OFF               0x64
  89 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF               0x68
  90
  91 /* version register */
  92 #define ENA_REGS_VERSION_MINOR_VERSION_MASK             0xff
  93 #define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT            8
  94 #define ENA_REGS_VERSION_MAJOR_VERSION_MASK             0xff00
  95
  96 /* controller_version register */
  97 #define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK               0xff
  98 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT         8
  99 #define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK          0xff00
 100 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT         16
 101 #define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK          0xff0000
 102 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT               24
 103 #define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK                0xff000000
 104
 105 /* caps register */
 106 #define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK            0x1
 107 #define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT               1
 108 #define ENA_REGS_CAPS_RESET_TIMEOUT_MASK                0x3e
 109 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT              8
 110 #define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK               0xff00
 111 #define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT                16
 112 #define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK         0xf0000
 113
 114 /* aq_caps register */
 115 #define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK          0xffff
 116 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT            16
 117 #define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK             0xffff0000
 118
 119 /* acq_caps register */
 120 #define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK                0xffff
 121 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT          16
 122 #define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK           0xffff0000
 123
 124 /* aenq_caps register */
 125 #define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK              0xffff
 126 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT                16
 127 #define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK         0xffff0000
 128
 129 /* dev_ctl register */
 130 #define ENA_REGS_DEV_CTL_DEV_RESET_MASK         0x1
 131 #define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT               1
 132 #define ENA_REGS_DEV_CTL_AQ_RESTART_MASK                0x2
 133 #define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT                2
 134 #define ENA_REGS_DEV_CTL_QUIESCENT_MASK         0x4
 135 #define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT                3
 136 #define ENA_REGS_DEV_CTL_IO_RESUME_MASK         0x8
 137 #define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT             28
 138 #define ENA_REGS_DEV_CTL_RESET_REASON_MASK              0xf0000000
 139
 140 /* dev_sts register */
 141 #define ENA_REGS_DEV_STS_READY_MASK             0x1
 142 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT           1
 143 #define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK            0x2
 144 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT              2
 145 #define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK               0x4
 146 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT                3
 147 #define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK         0x8
 148 #define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT           4
 149 #define ENA_REGS_DEV_STS_RESET_FINISHED_MASK            0x10
 150 #define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT              5
 151 #define ENA_REGS_DEV_STS_FATAL_ERROR_MASK               0x20
 152 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT              6
 153 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK               0x40
 154 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT         7
 155 #define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK          0x80
 156
 157 /* mmio_reg_read register */
 158 #define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK              0xffff
 159 #define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT            16
 160 #define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK             0xffff0000
 161
 162 /* rss_ind_entry_update register */
 163 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK                0xffff
 164 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT              16
 165 #define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK               0xffff0000
 166
 167 #endif /*_ENA_REGS_H_ */