arch/arm/mach-omap2/hsmmc.c

   1 /*
   2  * linux/arch/arm/mach-omap2/hsmmc.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/slab.h>
  14 #include <linux/string.h>
  15 #include <linux/delay.h>
  16 #include <mach/hardware.h>
  17 #include <plat/mmc.h>
  18 #include <plat/omap-pm.h>
  19 #include <plat/mux.h>
  20 #include <plat/omap_device.h>
  21
  22 #include "mux.h"
  23 #include "hsmmc.h"
  24 #include "control.h"
  25
  26 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  27
  28 static u16 control_pbias_offset;
  29 static u16 control_devconf1_offset;
  30 static u16 control_mmc1;
  31
  32 #define HSMMC_NAME_LEN  9
  33
  34 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  35
  36 static int hsmmc_get_context_loss(struct device *dev)
  37 {
  38         return omap_pm_get_dev_context_loss_count(dev);
  39 }
  40
  41 #else
  42 #define hsmmc_get_context_loss NULL
  43 #endif
  44
  45 static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
  46                                   int power_on, int vdd)
  47 {
  48         u32 reg, prog_io;
  49         struct omap_mmc_platform_data *mmc = dev->platform_data;
  50
  51         if (mmc->slots[0].remux)
  52                 mmc->slots[0].remux(dev, slot, power_on);
  53
  54         /*
  55          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
  56          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
  57          * 1.8V and 3.0V modes, controlled by the PBIAS register.
  58          *
  59          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
  60          * is most naturally TWL VSIM; those pins also use PBIAS.
  61          *
  62          * FIXME handle VMMC1A as needed ...
  63          */
  64         if (power_on) {
  65                 if (cpu_is_omap2430()) {
  66                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
  67                         if ((1 << vdd) >= MMC_VDD_30_31)
  68                                 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
  69                         else
  70                                 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
  71                         omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
  72                 }
  73
  74                 if (mmc->slots[0].internal_clock) {
  75                         reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  76                         reg |= OMAP2_MMCSDIO1ADPCLKISEL;
  77                         omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
  78                 }
  79
  80                 reg = omap_ctrl_readl(control_pbias_offset);
  81                 if (cpu_is_omap3630()) {
  82                         /* Set MMC I/O to 52Mhz */
  83                         prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
  84                         prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
  85                         omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
  86                 } else {
  87                         reg |= OMAP2_PBIASSPEEDCTRL0;
  88                 }
  89                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  90                 omap_ctrl_writel(reg, control_pbias_offset);
  91         } else {
  92                 reg = omap_ctrl_readl(control_pbias_offset);
  93                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  94                 omap_ctrl_writel(reg, control_pbias_offset);
  95         }
  96 }
  97
  98 static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
  99                                  int power_on, int vdd)
 100 {
 101         u32 reg;
 102
 103         /* 100ms delay required for PBIAS configuration */
 104         msleep(100);
 105
 106         if (power_on) {
 107                 reg = omap_ctrl_readl(control_pbias_offset);
 108                 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
 109                 if ((1 << vdd) <= MMC_VDD_165_195)
 110                         reg &= ~OMAP2_PBIASLITEVMODE0;
 111                 else
 112                         reg |= OMAP2_PBIASLITEVMODE0;
 113                 omap_ctrl_writel(reg, control_pbias_offset);
 114         } else {
 115                 reg = omap_ctrl_readl(control_pbias_offset);
 116                 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
 117                         OMAP2_PBIASLITEVMODE0);
 118                 omap_ctrl_writel(reg, control_pbias_offset);
 119         }
 120 }
 121
 122 static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
 123                                   int power_on, int vdd)
 124 {
 125         u32 reg;
 126
 127         /*
 128          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
 129          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
 130          * 1.8V and 3.0V modes, controlled by the PBIAS register.
 131          *
 132          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
 133          * is most naturally TWL VSIM; those pins also use PBIAS.
 134          *
 135          * FIXME handle VMMC1A as needed ...
 136          */
 137         reg = omap4_ctrl_pad_readl(control_pbias_offset);
 138         reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 139                 OMAP4_MMC1_PWRDNZ_MASK |
 140                 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 141         omap4_ctrl_pad_writel(reg, control_pbias_offset);
 142 }
 143
 144 static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
 145                                  int power_on, int vdd)
 146 {
 147         u32 reg;
 148
 149         if (power_on) {
 150                 reg = omap4_ctrl_pad_readl(control_pbias_offset);
 151                 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
 152                 if ((1 << vdd) <= MMC_VDD_165_195)
 153                         reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
 154                 else
 155                         reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
 156                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 157                         OMAP4_MMC1_PWRDNZ_MASK |
 158                         OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 159                 omap4_ctrl_pad_writel(reg, control_pbias_offset);
 160                 /* 4 microsec delay for comparator to generate an error*/
 161                 udelay(4);
 162                 reg = omap4_ctrl_pad_readl(control_pbias_offset);
 163                 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
 164                         pr_err("Pbias Voltage is not same as LDO\n");
 165                         /* Caution : On VMODE_ERROR Power Down MMC IO */
 166                         reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
 167                                 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 168                         omap4_ctrl_pad_writel(reg, control_pbias_offset);
 169                 }
 170         } else {
 171                 reg = omap4_ctrl_pad_readl(control_pbias_offset);
 172                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 173                         OMAP4_MMC1_PWRDNZ_MASK |
 174                         OMAP4_MMC1_PBIASLITE_VMODE_MASK |
 175                         OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
 176                 omap4_ctrl_pad_writel(reg, control_pbias_offset);
 177         }
 178 }
 179
 180 static void hsmmc23_before_set_reg(struct device *dev, int slot,
 181                                    int power_on, int vdd)
 182 {
 183         struct omap_mmc_platform_data *mmc = dev->platform_data;
 184
 185         if (mmc->slots[0].remux)
 186                 mmc->slots[0].remux(dev, slot, power_on);
 187
 188         if (power_on) {
 189                 /* Only MMC2 supports a CLKIN */
 190                 if (mmc->slots[0].internal_clock) {
 191                         u32 reg;
 192
 193                         reg = omap_ctrl_readl(control_devconf1_offset);
 194                         reg |= OMAP2_MMCSDIO2ADPCLKISEL;
 195                         omap_ctrl_writel(reg, control_devconf1_offset);
 196                 }
 197         }
 198 }
 199
 200 static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
 201                                                         int vdd)
 202 {
 203         return 0;
 204 }
 205
 206 static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
 207                         int controller_nr)
 208 {
 209         if ((mmc_controller->slots[0].switch_pin > 0) && \
 210                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
 211                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
 212                                         OMAP_PIN_INPUT_PULLUP);
 213         if ((mmc_controller->slots[0].gpio_wp > 0) && \
 214                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
 215                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
 216                                         OMAP_PIN_INPUT_PULLUP);
 217         if (cpu_is_omap34xx()) {
 218                 if (controller_nr == 0) {
 219                         omap_mux_init_signal("sdmmc1_clk",
 220                                 OMAP_PIN_INPUT_PULLUP);
 221                         omap_mux_init_signal("sdmmc1_cmd",
 222                                 OMAP_PIN_INPUT_PULLUP);
 223                         omap_mux_init_signal("sdmmc1_dat0",
 224                                 OMAP_PIN_INPUT_PULLUP);
 225                         if (mmc_controller->slots[0].caps &
 226                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 227                                 omap_mux_init_signal("sdmmc1_dat1",
 228                                         OMAP_PIN_INPUT_PULLUP);
 229                                 omap_mux_init_signal("sdmmc1_dat2",
 230                                         OMAP_PIN_INPUT_PULLUP);
 231                                 omap_mux_init_signal("sdmmc1_dat3",
 232                                         OMAP_PIN_INPUT_PULLUP);
 233                         }
 234                         if (mmc_controller->slots[0].caps &
 235                                                 MMC_CAP_8_BIT_DATA) {
 236                                 omap_mux_init_signal("sdmmc1_dat4",
 237                                         OMAP_PIN_INPUT_PULLUP);
 238                                 omap_mux_init_signal("sdmmc1_dat5",
 239                                         OMAP_PIN_INPUT_PULLUP);
 240                                 omap_mux_init_signal("sdmmc1_dat6",
 241                                         OMAP_PIN_INPUT_PULLUP);
 242                                 omap_mux_init_signal("sdmmc1_dat7",
 243                                         OMAP_PIN_INPUT_PULLUP);
 244                         }
 245                 }
 246                 if (controller_nr == 1) {
 247                         /* MMC2 */
 248                         omap_mux_init_signal("sdmmc2_clk",
 249                                 OMAP_PIN_INPUT_PULLUP);
 250                         omap_mux_init_signal("sdmmc2_cmd",
 251                                 OMAP_PIN_INPUT_PULLUP);
 252                         omap_mux_init_signal("sdmmc2_dat0",
 253                                 OMAP_PIN_INPUT_PULLUP);
 254
 255                         /*
 256                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7
 257                          * need to be muxed in the board-*.c files
 258                          */
 259                         if (mmc_controller->slots[0].caps &
 260                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 261                                 omap_mux_init_signal("sdmmc2_dat1",
 262                                         OMAP_PIN_INPUT_PULLUP);
 263                                 omap_mux_init_signal("sdmmc2_dat2",
 264                                         OMAP_PIN_INPUT_PULLUP);
 265                                 omap_mux_init_signal("sdmmc2_dat3",
 266                                         OMAP_PIN_INPUT_PULLUP);
 267                         }
 268                         if (mmc_controller->slots[0].caps &
 269                                                         MMC_CAP_8_BIT_DATA) {
 270                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
 271                                         OMAP_PIN_INPUT_PULLUP);
 272                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
 273                                         OMAP_PIN_INPUT_PULLUP);
 274                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
 275                                         OMAP_PIN_INPUT_PULLUP);
 276                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
 277                                         OMAP_PIN_INPUT_PULLUP);
 278                         }
 279                 }
 280
 281                 /*
 282                  * For MMC3 the pins need to be muxed in the board-*.c files
 283                  */
 284         }
 285 }
 286
 287 static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 288                                         struct omap_mmc_platform_data *mmc)
 289 {
 290         char *hc_name;
 291
 292         hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
 293         if (!hc_name) {
 294                 pr_err("Cannot allocate memory for controller slot name\n");
 295                 kfree(hc_name);
 296                 return -ENOMEM;
 297         }
 298
 299         if (c->name)
 300                 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
 301         else
 302                 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
 303                                                                 c->mmc, 1);
 304         mmc->slots[0].name = hc_name;
 305         mmc->nr_slots = 1;
 306         mmc->slots[0].caps = c->caps;
 307         mmc->slots[0].internal_clock = !c->ext_clock;
 308         mmc->dma_mask = 0xffffffff;
 309         if (cpu_is_omap44xx())
 310                 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
 311         else
 312                 mmc->reg_offset = 0;
 313
 314         mmc->get_context_loss_count = hsmmc_get_context_loss;
 315
 316         mmc->slots[0].switch_pin = c->gpio_cd;
 317         mmc->slots[0].gpio_wp = c->gpio_wp;
 318
 319         mmc->slots[0].remux = c->remux;
 320         mmc->slots[0].init_card = c->init_card;
 321
 322         if (c->cover_only)
 323                 mmc->slots[0].cover = 1;
 324
 325         if (c->nonremovable)
 326                 mmc->slots[0].nonremovable = 1;
 327
 328         if (c->power_saving)
 329                 mmc->slots[0].power_saving = 1;
 330
 331         if (c->no_off)
 332                 mmc->slots[0].no_off = 1;
 333
 334         if (c->vcc_aux_disable_is_sleep)
 335                 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
 336
 337         /*
 338          * NOTE:  MMC slots should have a Vcc regulator set up.
 339          * This may be from a TWL4030-family chip, another
 340          * controllable regulator, or a fixed supply.
 341          *
 342          * temporary HACK: ocr_mask instead of fixed supply
 343          */
 344         mmc->slots[0].ocr_mask = c->ocr_mask;
 345
 346         if (cpu_is_omap3517() || cpu_is_omap3505())
 347                 mmc->slots[0].set_power = nop_mmc_set_power;
 348         else
 349                 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 350
 351         if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
 352                 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
 353
 354         switch (c->mmc) {
 355         case 1:
 356                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 357                         /* on-chip level shifting via PBIAS0/PBIAS1 */
 358                         if (cpu_is_omap44xx()) {
 359                                 mmc->slots[0].before_set_reg =
 360                                                 omap4_hsmmc1_before_set_reg;
 361                                 mmc->slots[0].after_set_reg =
 362                                                 omap4_hsmmc1_after_set_reg;
 363                         } else {
 364                                 mmc->slots[0].before_set_reg =
 365                                                 omap_hsmmc1_before_set_reg;
 366                                 mmc->slots[0].after_set_reg =
 367                                                 omap_hsmmc1_after_set_reg;
 368                         }
 369                 }
 370
 371                 /* OMAP3630 HSMMC1 supports only 4-bit */
 372                 if (cpu_is_omap3630() &&
 373                                 (c->caps & MMC_CAP_8_BIT_DATA)) {
 374                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 375                         c->caps |= MMC_CAP_4_BIT_DATA;
 376                         mmc->slots[0].caps = c->caps;
 377                 }
 378                 break;
 379         case 2:
 380                 if (c->ext_clock)
 381                         c->transceiver = 1;
 382                 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
 383                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 384                         c->caps |= MMC_CAP_4_BIT_DATA;
 385                 }
 386                 /* FALLTHROUGH */
 387         case 3:
 388                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 389                         /* off-chip level shifting, or none */
 390                         mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
 391                         mmc->slots[0].after_set_reg = NULL;
 392                 }
 393                 break;
 394         case 4:
 395         case 5:
 396                 mmc->slots[0].before_set_reg = NULL;
 397                 mmc->slots[0].after_set_reg = NULL;
 398                 break;
 399         default:
 400                 pr_err("MMC%d configuration not supported!\n", c->mmc);
 401                 kfree(hc_name);
 402                 return -ENODEV;
 403         }
 404         return 0;
 405 }
 406
 407 static struct omap_device_pm_latency omap_hsmmc_latency[] = {
 408         [0] = {
 409                 .deactivate_func = omap_device_idle_hwmods,
 410                 .activate_func   = omap_device_enable_hwmods,
 411                 .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
 412         },
 413         /*
 414          * XXX There should also be an entry here to power off/on the
 415          * MMC regulators/PBIAS cells, etc.
 416          */
 417 };
 418
 419 #define MAX_OMAP_MMC_HWMOD_NAME_LEN             16
 420
 421 void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
 422 {
 423         struct omap_hwmod *oh;
 424         struct omap_device *od;
 425         struct omap_device_pm_latency *ohl;
 426         char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
 427         struct omap_mmc_platform_data *mmc_data;
 428         struct omap_mmc_dev_attr *mmc_dev_attr;
 429         char *name;
 430         int l;
 431         int ohl_cnt = 0;
 432
 433         mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
 434         if (!mmc_data) {
 435                 pr_err("Cannot allocate memory for mmc device!\n");
 436                 goto done;
 437         }
 438
 439         if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
 440                 pr_err("%s fails!\n", __func__);
 441                 goto done;
 442         }
 443         omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
 444
 445         name = "omap_hsmmc";
 446         ohl = omap_hsmmc_latency;
 447         ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
 448
 449         l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
 450                      "mmc%d", ctrl_nr);
 451         WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
 452              "String buffer overflow in MMC%d device setup\n", ctrl_nr);
 453         oh = omap_hwmod_lookup(oh_name);
 454         if (!oh) {
 455                 pr_err("Could not look up %s\n", oh_name);
 456                 kfree(mmc_data->slots[0].name);
 457                 goto done;
 458         }
 459
 460         if (oh->dev_attr != NULL) {
 461                 mmc_dev_attr = oh->dev_attr;
 462                 mmc_data->controller_flags = mmc_dev_attr->flags;
 463         }
 464
 465         od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
 466                 sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
 467         if (IS_ERR(od)) {
 468                 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
 469                 kfree(mmc_data->slots[0].name);
 470                 goto done;
 471         }
 472         /*
 473          * return device handle to board setup code
 474          * required to populate for regulator framework structure
 475          */
 476         hsmmcinfo->dev = &od->pdev.dev;
 477
 478 done:
 479         kfree(mmc_data);
 480 }
 481
 482 void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
 483 {
 484         u32 reg;
 485
 486         if (!cpu_is_omap44xx()) {
 487                 if (cpu_is_omap2430()) {
 488                         control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
 489                         control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
 490                 } else {
 491                         control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
 492                         control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
 493                 }
 494         } else {
 495                 control_pbias_offset =
 496                         OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
 497                 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
 498                 reg = omap4_ctrl_pad_readl(control_mmc1);
 499                 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
 500                         OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
 501                 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
 502                         OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
 503                 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
 504                         OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
 505                         OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
 506                 omap4_ctrl_pad_writel(reg, control_mmc1);
 507         }
 508
 509         for (; controllers->mmc; controllers++)
 510                 omap_init_hsmmc(controllers, controllers->mmc);
 511
 512 }
 513
 514 #endif