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cfg80211: fix scan crash on single-band cards
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
blobabc548a0c98dacae4bd6c5fc7d8eb615dde9b4c5
1 /*
2 * Hardware modules present on the OMAP44xx chips
3 *
4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21 #include <linux/io.h>
22
23 #include <plat/omap_hwmod.h>
24 #include <plat/cpu.h>
25 #include <plat/gpio.h>
26 #include <plat/dma.h>
27 #include <plat/mcspi.h>
28 #include <plat/mcbsp.h>
29 #include <plat/mmc.h>
30
31 #include "omap_hwmod_common_data.h"
32
33 #include "cm1_44xx.h"
34 #include "cm2_44xx.h"
35 #include "prm44xx.h"
36 #include "prm-regbits-44xx.h"
37 #include "wd_timer.h"
38
39 /* Base offset for all OMAP4 interrupts external to MPUSS */
40 #define OMAP44XX_IRQ_GIC_START 32
41
42 /* Base offset for all OMAP4 dma requests */
43 #define OMAP44XX_DMA_REQ_START 1
44
45 /* Backward references (IPs with Bus Master capability) */
46 static struct omap_hwmod omap44xx_aess_hwmod;
47 static struct omap_hwmod omap44xx_dma_system_hwmod;
48 static struct omap_hwmod omap44xx_dmm_hwmod;
49 static struct omap_hwmod omap44xx_dsp_hwmod;
50 static struct omap_hwmod omap44xx_dss_hwmod;
51 static struct omap_hwmod omap44xx_emif_fw_hwmod;
52 static struct omap_hwmod omap44xx_hsi_hwmod;
53 static struct omap_hwmod omap44xx_ipu_hwmod;
54 static struct omap_hwmod omap44xx_iss_hwmod;
55 static struct omap_hwmod omap44xx_iva_hwmod;
56 static struct omap_hwmod omap44xx_l3_instr_hwmod;
57 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
58 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
59 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
60 static struct omap_hwmod omap44xx_l4_abe_hwmod;
61 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
62 static struct omap_hwmod omap44xx_l4_per_hwmod;
63 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
64 static struct omap_hwmod omap44xx_mmc1_hwmod;
65 static struct omap_hwmod omap44xx_mmc2_hwmod;
66 static struct omap_hwmod omap44xx_mpu_hwmod;
67 static struct omap_hwmod omap44xx_mpu_private_hwmod;
68 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
69
70 /*
71 * Interconnects omap_hwmod structures
72 * hwmods that compose the global OMAP interconnect
73 */
74
75 /*
76 * 'dmm' class
77 * instance(s): dmm
78 */
79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
80 .name = "dmm",
81 };
82
83 /* dmm interface data */
84 /* l3_main_1 -> dmm */
85 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
86 .master = &omap44xx_l3_main_1_hwmod,
87 .slave = &omap44xx_dmm_hwmod,
88 .clk = "l3_div_ck",
89 .user = OCP_USER_SDMA,
90 };
91
92 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
93 {
94 .pa_start = 0x4e000000,
95 .pa_end = 0x4e0007ff,
96 .flags = ADDR_TYPE_RT
97 },
98 };
99
100 /* mpu -> dmm */
101 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
102 .master = &omap44xx_mpu_hwmod,
103 .slave = &omap44xx_dmm_hwmod,
104 .clk = "l3_div_ck",
105 .addr = omap44xx_dmm_addrs,
106 .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs),
107 .user = OCP_USER_MPU,
108 };
109
110 /* dmm slave ports */
111 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
112 &omap44xx_l3_main_1__dmm,
113 &omap44xx_mpu__dmm,
114 };
115
116 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
117 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
118 };
119
120 static struct omap_hwmod omap44xx_dmm_hwmod = {
121 .name = "dmm",
122 .class = &omap44xx_dmm_hwmod_class,
123 .slaves = omap44xx_dmm_slaves,
124 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
125 .mpu_irqs = omap44xx_dmm_irqs,
126 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
127 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
128 };
129
130 /*
131 * 'emif_fw' class
132 * instance(s): emif_fw
133 */
134 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
135 .name = "emif_fw",
136 };
137
138 /* emif_fw interface data */
139 /* dmm -> emif_fw */
140 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
141 .master = &omap44xx_dmm_hwmod,
142 .slave = &omap44xx_emif_fw_hwmod,
143 .clk = "l3_div_ck",
144 .user = OCP_USER_MPU | OCP_USER_SDMA,
145 };
146
147 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
148 {
149 .pa_start = 0x4a20c000,
150 .pa_end = 0x4a20c0ff,
151 .flags = ADDR_TYPE_RT
152 },
153 };
154
155 /* l4_cfg -> emif_fw */
156 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
157 .master = &omap44xx_l4_cfg_hwmod,
158 .slave = &omap44xx_emif_fw_hwmod,
159 .clk = "l4_div_ck",
160 .addr = omap44xx_emif_fw_addrs,
161 .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs),
162 .user = OCP_USER_MPU,
163 };
164
165 /* emif_fw slave ports */
166 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
167 &omap44xx_dmm__emif_fw,
168 &omap44xx_l4_cfg__emif_fw,
169 };
170
171 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
172 .name = "emif_fw",
173 .class = &omap44xx_emif_fw_hwmod_class,
174 .slaves = omap44xx_emif_fw_slaves,
175 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
176 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
177 };
178
179 /*
180 * 'l3' class
181 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
182 */
183 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
184 .name = "l3",
185 };
186
187 /* l3_instr interface data */
188 /* iva -> l3_instr */
189 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
190 .master = &omap44xx_iva_hwmod,
191 .slave = &omap44xx_l3_instr_hwmod,
192 .clk = "l3_div_ck",
193 .user = OCP_USER_MPU | OCP_USER_SDMA,
194 };
195
196 /* l3_main_3 -> l3_instr */
197 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
198 .master = &omap44xx_l3_main_3_hwmod,
199 .slave = &omap44xx_l3_instr_hwmod,
200 .clk = "l3_div_ck",
201 .user = OCP_USER_MPU | OCP_USER_SDMA,
202 };
203
204 /* l3_instr slave ports */
205 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
206 &omap44xx_iva__l3_instr,
207 &omap44xx_l3_main_3__l3_instr,
208 };
209
210 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
211 .name = "l3_instr",
212 .class = &omap44xx_l3_hwmod_class,
213 .slaves = omap44xx_l3_instr_slaves,
214 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
216 };
217
218 /* l3_main_1 interface data */
219 /* dsp -> l3_main_1 */
220 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
221 .master = &omap44xx_dsp_hwmod,
222 .slave = &omap44xx_l3_main_1_hwmod,
223 .clk = "l3_div_ck",
224 .user = OCP_USER_MPU | OCP_USER_SDMA,
225 };
226
227 /* dss -> l3_main_1 */
228 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
229 .master = &omap44xx_dss_hwmod,
230 .slave = &omap44xx_l3_main_1_hwmod,
231 .clk = "l3_div_ck",
232 .user = OCP_USER_MPU | OCP_USER_SDMA,
233 };
234
235 /* l3_main_2 -> l3_main_1 */
236 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
237 .master = &omap44xx_l3_main_2_hwmod,
238 .slave = &omap44xx_l3_main_1_hwmod,
239 .clk = "l3_div_ck",
240 .user = OCP_USER_MPU | OCP_USER_SDMA,
241 };
242
243 /* l4_cfg -> l3_main_1 */
244 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
245 .master = &omap44xx_l4_cfg_hwmod,
246 .slave = &omap44xx_l3_main_1_hwmod,
247 .clk = "l4_div_ck",
248 .user = OCP_USER_MPU | OCP_USER_SDMA,
249 };
250
251 /* mmc1 -> l3_main_1 */
252 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
253 .master = &omap44xx_mmc1_hwmod,
254 .slave = &omap44xx_l3_main_1_hwmod,
255 .clk = "l3_div_ck",
256 .user = OCP_USER_MPU | OCP_USER_SDMA,
257 };
258
259 /* mmc2 -> l3_main_1 */
260 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
261 .master = &omap44xx_mmc2_hwmod,
262 .slave = &omap44xx_l3_main_1_hwmod,
263 .clk = "l3_div_ck",
264 .user = OCP_USER_MPU | OCP_USER_SDMA,
265 };
266
267 /* L3 target configuration and error log registers */
268 static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
269 { .irq = 9 + OMAP44XX_IRQ_GIC_START },
270 { .irq = 10 + OMAP44XX_IRQ_GIC_START },
271 };
272
273 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
274 {
275 .pa_start = 0x44000000,
276 .pa_end = 0x44000fff,
277 .flags = ADDR_TYPE_RT,
278 },
279 };
280
281 /* mpu -> l3_main_1 */
282 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
283 .master = &omap44xx_mpu_hwmod,
284 .slave = &omap44xx_l3_main_1_hwmod,
285 .clk = "l3_div_ck",
286 .addr = omap44xx_l3_main_1_addrs,
287 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_1_addrs),
288 .user = OCP_USER_MPU | OCP_USER_SDMA,
289 };
290
291 /* l3_main_1 slave ports */
292 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
293 &omap44xx_dsp__l3_main_1,
294 &omap44xx_dss__l3_main_1,
295 &omap44xx_l3_main_2__l3_main_1,
296 &omap44xx_l4_cfg__l3_main_1,
297 &omap44xx_mmc1__l3_main_1,
298 &omap44xx_mmc2__l3_main_1,
299 &omap44xx_mpu__l3_main_1,
300 };
301
302 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
303 .name = "l3_main_1",
304 .class = &omap44xx_l3_hwmod_class,
305 .mpu_irqs = omap44xx_l3_targ_irqs,
306 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_l3_targ_irqs),
307 .slaves = omap44xx_l3_main_1_slaves,
308 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
309 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
310 };
311
312 /* l3_main_2 interface data */
313 /* dma_system -> l3_main_2 */
314 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
315 .master = &omap44xx_dma_system_hwmod,
316 .slave = &omap44xx_l3_main_2_hwmod,
317 .clk = "l3_div_ck",
318 .user = OCP_USER_MPU | OCP_USER_SDMA,
319 };
320
321 /* hsi -> l3_main_2 */
322 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
323 .master = &omap44xx_hsi_hwmod,
324 .slave = &omap44xx_l3_main_2_hwmod,
325 .clk = "l3_div_ck",
326 .user = OCP_USER_MPU | OCP_USER_SDMA,
327 };
328
329 /* ipu -> l3_main_2 */
330 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
331 .master = &omap44xx_ipu_hwmod,
332 .slave = &omap44xx_l3_main_2_hwmod,
333 .clk = "l3_div_ck",
334 .user = OCP_USER_MPU | OCP_USER_SDMA,
335 };
336
337 /* iss -> l3_main_2 */
338 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
339 .master = &omap44xx_iss_hwmod,
340 .slave = &omap44xx_l3_main_2_hwmod,
341 .clk = "l3_div_ck",
342 .user = OCP_USER_MPU | OCP_USER_SDMA,
343 };
344
345 /* iva -> l3_main_2 */
346 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
347 .master = &omap44xx_iva_hwmod,
348 .slave = &omap44xx_l3_main_2_hwmod,
349 .clk = "l3_div_ck",
350 .user = OCP_USER_MPU | OCP_USER_SDMA,
351 };
352
353 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
354 {
355 .pa_start = 0x44800000,
356 .pa_end = 0x44801fff,
357 .flags = ADDR_TYPE_RT,
358 },
359 };
360
361 /* l3_main_1 -> l3_main_2 */
362 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
363 .master = &omap44xx_l3_main_1_hwmod,
364 .slave = &omap44xx_l3_main_2_hwmod,
365 .clk = "l3_div_ck",
366 .addr = omap44xx_l3_main_2_addrs,
367 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_2_addrs),
368 .user = OCP_USER_MPU | OCP_USER_SDMA,
369 };
370
371 /* l4_cfg -> l3_main_2 */
372 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
373 .master = &omap44xx_l4_cfg_hwmod,
374 .slave = &omap44xx_l3_main_2_hwmod,
375 .clk = "l4_div_ck",
376 .user = OCP_USER_MPU | OCP_USER_SDMA,
377 };
378
379 /* usb_otg_hs -> l3_main_2 */
380 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
381 .master = &omap44xx_usb_otg_hs_hwmod,
382 .slave = &omap44xx_l3_main_2_hwmod,
383 .clk = "l3_div_ck",
384 .user = OCP_USER_MPU | OCP_USER_SDMA,
385 };
386
387 /* l3_main_2 slave ports */
388 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
389 &omap44xx_dma_system__l3_main_2,
390 &omap44xx_hsi__l3_main_2,
391 &omap44xx_ipu__l3_main_2,
392 &omap44xx_iss__l3_main_2,
393 &omap44xx_iva__l3_main_2,
394 &omap44xx_l3_main_1__l3_main_2,
395 &omap44xx_l4_cfg__l3_main_2,
396 &omap44xx_usb_otg_hs__l3_main_2,
397 };
398
399 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
400 .name = "l3_main_2",
401 .class = &omap44xx_l3_hwmod_class,
402 .slaves = omap44xx_l3_main_2_slaves,
403 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
404 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
405 };
406
407 /* l3_main_3 interface data */
408 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
409 {
410 .pa_start = 0x45000000,
411 .pa_end = 0x45000fff,
412 .flags = ADDR_TYPE_RT,
413 },
414 };
415
416 /* l3_main_1 -> l3_main_3 */
417 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
418 .master = &omap44xx_l3_main_1_hwmod,
419 .slave = &omap44xx_l3_main_3_hwmod,
420 .clk = "l3_div_ck",
421 .addr = omap44xx_l3_main_3_addrs,
422 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_3_addrs),
423 .user = OCP_USER_MPU | OCP_USER_SDMA,
424 };
425
426 /* l3_main_2 -> l3_main_3 */
427 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
428 .master = &omap44xx_l3_main_2_hwmod,
429 .slave = &omap44xx_l3_main_3_hwmod,
430 .clk = "l3_div_ck",
431 .user = OCP_USER_MPU | OCP_USER_SDMA,
432 };
433
434 /* l4_cfg -> l3_main_3 */
435 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
436 .master = &omap44xx_l4_cfg_hwmod,
437 .slave = &omap44xx_l3_main_3_hwmod,
438 .clk = "l4_div_ck",
439 .user = OCP_USER_MPU | OCP_USER_SDMA,
440 };
441
442 /* l3_main_3 slave ports */
443 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
444 &omap44xx_l3_main_1__l3_main_3,
445 &omap44xx_l3_main_2__l3_main_3,
446 &omap44xx_l4_cfg__l3_main_3,
447 };
448
449 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
450 .name = "l3_main_3",
451 .class = &omap44xx_l3_hwmod_class,
452 .slaves = omap44xx_l3_main_3_slaves,
453 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
454 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
455 };
456
457 /*
458 * 'l4' class
459 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
460 */
461 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
462 .name = "l4",
463 };
464
465 /* l4_abe interface data */
466 /* aess -> l4_abe */
467 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
468 .master = &omap44xx_aess_hwmod,
469 .slave = &omap44xx_l4_abe_hwmod,
470 .clk = "ocp_abe_iclk",
471 .user = OCP_USER_MPU | OCP_USER_SDMA,
472 };
473
474 /* dsp -> l4_abe */
475 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
476 .master = &omap44xx_dsp_hwmod,
477 .slave = &omap44xx_l4_abe_hwmod,
478 .clk = "ocp_abe_iclk",
479 .user = OCP_USER_MPU | OCP_USER_SDMA,
480 };
481
482 /* l3_main_1 -> l4_abe */
483 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
484 .master = &omap44xx_l3_main_1_hwmod,
485 .slave = &omap44xx_l4_abe_hwmod,
486 .clk = "l3_div_ck",
487 .user = OCP_USER_MPU | OCP_USER_SDMA,
488 };
489
490 /* mpu -> l4_abe */
491 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
492 .master = &omap44xx_mpu_hwmod,
493 .slave = &omap44xx_l4_abe_hwmod,
494 .clk = "ocp_abe_iclk",
495 .user = OCP_USER_MPU | OCP_USER_SDMA,
496 };
497
498 /* l4_abe slave ports */
499 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
500 &omap44xx_aess__l4_abe,
501 &omap44xx_dsp__l4_abe,
502 &omap44xx_l3_main_1__l4_abe,
503 &omap44xx_mpu__l4_abe,
504 };
505
506 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
507 .name = "l4_abe",
508 .class = &omap44xx_l4_hwmod_class,
509 .slaves = omap44xx_l4_abe_slaves,
510 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
511 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
512 };
513
514 /* l4_cfg interface data */
515 /* l3_main_1 -> l4_cfg */
516 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
517 .master = &omap44xx_l3_main_1_hwmod,
518 .slave = &omap44xx_l4_cfg_hwmod,
519 .clk = "l3_div_ck",
520 .user = OCP_USER_MPU | OCP_USER_SDMA,
521 };
522
523 /* l4_cfg slave ports */
524 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
525 &omap44xx_l3_main_1__l4_cfg,
526 };
527
528 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
529 .name = "l4_cfg",
530 .class = &omap44xx_l4_hwmod_class,
531 .slaves = omap44xx_l4_cfg_slaves,
532 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
533 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
534 };
535
536 /* l4_per interface data */
537 /* l3_main_2 -> l4_per */
538 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
539 .master = &omap44xx_l3_main_2_hwmod,
540 .slave = &omap44xx_l4_per_hwmod,
541 .clk = "l3_div_ck",
542 .user = OCP_USER_MPU | OCP_USER_SDMA,
543 };
544
545 /* l4_per slave ports */
546 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
547 &omap44xx_l3_main_2__l4_per,
548 };
549
550 static struct omap_hwmod omap44xx_l4_per_hwmod = {
551 .name = "l4_per",
552 .class = &omap44xx_l4_hwmod_class,
553 .slaves = omap44xx_l4_per_slaves,
554 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
555 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
556 };
557
558 /* l4_wkup interface data */
559 /* l4_cfg -> l4_wkup */
560 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
561 .master = &omap44xx_l4_cfg_hwmod,
562 .slave = &omap44xx_l4_wkup_hwmod,
563 .clk = "l4_div_ck",
564 .user = OCP_USER_MPU | OCP_USER_SDMA,
565 };
566
567 /* l4_wkup slave ports */
568 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
569 &omap44xx_l4_cfg__l4_wkup,
570 };
571
572 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
573 .name = "l4_wkup",
574 .class = &omap44xx_l4_hwmod_class,
575 .slaves = omap44xx_l4_wkup_slaves,
576 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
577 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
578 };
579
580 /*
581 * 'mpu_bus' class
582 * instance(s): mpu_private
583 */
584 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
585 .name = "mpu_bus",
586 };
587
588 /* mpu_private interface data */
589 /* mpu -> mpu_private */
590 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
591 .master = &omap44xx_mpu_hwmod,
592 .slave = &omap44xx_mpu_private_hwmod,
593 .clk = "l3_div_ck",
594 .user = OCP_USER_MPU | OCP_USER_SDMA,
595 };
596
597 /* mpu_private slave ports */
598 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
599 &omap44xx_mpu__mpu_private,
600 };
601
602 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
603 .name = "mpu_private",
604 .class = &omap44xx_mpu_bus_hwmod_class,
605 .slaves = omap44xx_mpu_private_slaves,
606 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
607 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
608 };
609
610 /*
611 * Modules omap_hwmod structures
612 *
613 * The following IPs are excluded for the moment because:
614 * - They do not need an explicit SW control using omap_hwmod API.
615 * - They still need to be validated with the driver
616 * properly adapted to omap_hwmod / omap_device
617 *
618 * c2c
619 * c2c_target_fw
620 * cm_core
621 * cm_core_aon
622 * ctrl_module_core
623 * ctrl_module_pad_core
624 * ctrl_module_pad_wkup
625 * ctrl_module_wkup
626 * debugss
627 * efuse_ctrl_cust
628 * efuse_ctrl_std
629 * elm
630 * emif1
631 * emif2
632 * fdif
633 * gpmc
634 * gpu
635 * hdq1w
636 * hsi
637 * ocmc_ram
638 * ocp2scp_usb_phy
639 * ocp_wp_noc
640 * prcm_mpu
641 * prm
642 * scrm
643 * sl2if
644 * slimbus1
645 * slimbus2
646 * usb_host_fs
647 * usb_host_hs
648 * usb_phy_cm
649 * usb_tll_hs
650 * usim
651 */
652
653 /*
654 * 'aess' class
655 * audio engine sub system
656 */
657
658 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
659 .rev_offs = 0x0000,
660 .sysc_offs = 0x0010,
661 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
662 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
663 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
664 .sysc_fields = &omap_hwmod_sysc_type2,
665 };
666
667 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
668 .name = "aess",
669 .sysc = &omap44xx_aess_sysc,
670 };
671
672 /* aess */
673 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
674 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
675 };
676
677 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
678 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
679 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
680 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
681 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
682 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
683 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
684 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
685 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
686 };
687
688 /* aess master ports */
689 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
690 &omap44xx_aess__l4_abe,
691 };
692
693 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
694 {
695 .pa_start = 0x401f1000,
696 .pa_end = 0x401f13ff,
697 .flags = ADDR_TYPE_RT
698 },
699 };
700
701 /* l4_abe -> aess */
702 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
703 .master = &omap44xx_l4_abe_hwmod,
704 .slave = &omap44xx_aess_hwmod,
705 .clk = "ocp_abe_iclk",
706 .addr = omap44xx_aess_addrs,
707 .addr_cnt = ARRAY_SIZE(omap44xx_aess_addrs),
708 .user = OCP_USER_MPU,
709 };
710
711 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
712 {
713 .pa_start = 0x490f1000,
714 .pa_end = 0x490f13ff,
715 .flags = ADDR_TYPE_RT
716 },
717 };
718
719 /* l4_abe -> aess (dma) */
720 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
721 .master = &omap44xx_l4_abe_hwmod,
722 .slave = &omap44xx_aess_hwmod,
723 .clk = "ocp_abe_iclk",
724 .addr = omap44xx_aess_dma_addrs,
725 .addr_cnt = ARRAY_SIZE(omap44xx_aess_dma_addrs),
726 .user = OCP_USER_SDMA,
727 };
728
729 /* aess slave ports */
730 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
731 &omap44xx_l4_abe__aess,
732 &omap44xx_l4_abe__aess_dma,
733 };
734
735 static struct omap_hwmod omap44xx_aess_hwmod = {
736 .name = "aess",
737 .class = &omap44xx_aess_hwmod_class,
738 .mpu_irqs = omap44xx_aess_irqs,
739 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs),
740 .sdma_reqs = omap44xx_aess_sdma_reqs,
741 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
742 .main_clk = "aess_fck",
743 .prcm = {
744 .omap4 = {
745 .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
746 },
747 },
748 .slaves = omap44xx_aess_slaves,
749 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
750 .masters = omap44xx_aess_masters,
751 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
752 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
753 };
754
755 /*
756 * 'bandgap' class
757 * bangap reference for ldo regulators
758 */
759
760 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
761 .name = "bandgap",
762 };
763
764 /* bandgap */
765 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
766 { .role = "fclk", .clk = "bandgap_fclk" },
767 };
768
769 static struct omap_hwmod omap44xx_bandgap_hwmod = {
770 .name = "bandgap",
771 .class = &omap44xx_bandgap_hwmod_class,
772 .prcm = {
773 .omap4 = {
774 .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
775 },
776 },
777 .opt_clks = bandgap_opt_clks,
778 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
779 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
780 };
781
782 /*
783 * 'counter' class
784 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
785 */
786
787 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
788 .rev_offs = 0x0000,
789 .sysc_offs = 0x0004,
790 .sysc_flags = SYSC_HAS_SIDLEMODE,
791 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
792 SIDLE_SMART_WKUP),
793 .sysc_fields = &omap_hwmod_sysc_type1,
794 };
795
796 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
797 .name = "counter",
798 .sysc = &omap44xx_counter_sysc,
799 };
800
801 /* counter_32k */
802 static struct omap_hwmod omap44xx_counter_32k_hwmod;
803 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
804 {
805 .pa_start = 0x4a304000,
806 .pa_end = 0x4a30401f,
807 .flags = ADDR_TYPE_RT
808 },
809 };
810
811 /* l4_wkup -> counter_32k */
812 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
813 .master = &omap44xx_l4_wkup_hwmod,
814 .slave = &omap44xx_counter_32k_hwmod,
815 .clk = "l4_wkup_clk_mux_ck",
816 .addr = omap44xx_counter_32k_addrs,
817 .addr_cnt = ARRAY_SIZE(omap44xx_counter_32k_addrs),
818 .user = OCP_USER_MPU | OCP_USER_SDMA,
819 };
820
821 /* counter_32k slave ports */
822 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
823 &omap44xx_l4_wkup__counter_32k,
824 };
825
826 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
827 .name = "counter_32k",
828 .class = &omap44xx_counter_hwmod_class,
829 .flags = HWMOD_SWSUP_SIDLE,
830 .main_clk = "sys_32k_ck",
831 .prcm = {
832 .omap4 = {
833 .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
834 },
835 },
836 .slaves = omap44xx_counter_32k_slaves,
837 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
838 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
839 };
840
841 /*
842 * 'dma' class
843 * dma controller for data exchange between memory to memory (i.e. internal or
844 * external memory) and gp peripherals to memory or memory to gp peripherals
845 */
846
847 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
848 .rev_offs = 0x0000,
849 .sysc_offs = 0x002c,
850 .syss_offs = 0x0028,
851 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
852 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
853 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
854 SYSS_HAS_RESET_STATUS),
855 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
856 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
857 .sysc_fields = &omap_hwmod_sysc_type1,
858 };
859
860 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
861 .name = "dma",
862 .sysc = &omap44xx_dma_sysc,
863 };
864
865 /* dma dev_attr */
866 static struct omap_dma_dev_attr dma_dev_attr = {
867 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
868 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
869 .lch_count = 32,
870 };
871
872 /* dma_system */
873 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
874 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
875 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
876 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
877 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
878 };
879
880 /* dma_system master ports */
881 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
882 &omap44xx_dma_system__l3_main_2,
883 };
884
885 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
886 {
887 .pa_start = 0x4a056000,
888 .pa_end = 0x4a056fff,
889 .flags = ADDR_TYPE_RT
890 },
891 };
892
893 /* l4_cfg -> dma_system */
894 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
895 .master = &omap44xx_l4_cfg_hwmod,
896 .slave = &omap44xx_dma_system_hwmod,
897 .clk = "l4_div_ck",
898 .addr = omap44xx_dma_system_addrs,
899 .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
900 .user = OCP_USER_MPU | OCP_USER_SDMA,
901 };
902
903 /* dma_system slave ports */
904 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
905 &omap44xx_l4_cfg__dma_system,
906 };
907
908 static struct omap_hwmod omap44xx_dma_system_hwmod = {
909 .name = "dma_system",
910 .class = &omap44xx_dma_hwmod_class,
911 .mpu_irqs = omap44xx_dma_system_irqs,
912 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
913 .main_clk = "l3_div_ck",
914 .prcm = {
915 .omap4 = {
916 .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
917 },
918 },
919 .dev_attr = &dma_dev_attr,
920 .slaves = omap44xx_dma_system_slaves,
921 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
922 .masters = omap44xx_dma_system_masters,
923 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
924 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
925 };
926
927 /*
928 * 'dmic' class
929 * digital microphone controller
930 */
931
932 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
933 .rev_offs = 0x0000,
934 .sysc_offs = 0x0010,
935 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
936 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
937 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
938 SIDLE_SMART_WKUP),
939 .sysc_fields = &omap_hwmod_sysc_type2,
940 };
941
942 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
943 .name = "dmic",
944 .sysc = &omap44xx_dmic_sysc,
945 };
946
947 /* dmic */
948 static struct omap_hwmod omap44xx_dmic_hwmod;
949 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
950 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
951 };
952
953 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
954 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
955 };
956
957 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
958 {
959 .pa_start = 0x4012e000,
960 .pa_end = 0x4012e07f,
961 .flags = ADDR_TYPE_RT
962 },
963 };
964
965 /* l4_abe -> dmic */
966 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
967 .master = &omap44xx_l4_abe_hwmod,
968 .slave = &omap44xx_dmic_hwmod,
969 .clk = "ocp_abe_iclk",
970 .addr = omap44xx_dmic_addrs,
971 .addr_cnt = ARRAY_SIZE(omap44xx_dmic_addrs),
972 .user = OCP_USER_MPU,
973 };
974
975 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
976 {
977 .pa_start = 0x4902e000,
978 .pa_end = 0x4902e07f,
979 .flags = ADDR_TYPE_RT
980 },
981 };
982
983 /* l4_abe -> dmic (dma) */
984 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
985 .master = &omap44xx_l4_abe_hwmod,
986 .slave = &omap44xx_dmic_hwmod,
987 .clk = "ocp_abe_iclk",
988 .addr = omap44xx_dmic_dma_addrs,
989 .addr_cnt = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
990 .user = OCP_USER_SDMA,
991 };
992
993 /* dmic slave ports */
994 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
995 &omap44xx_l4_abe__dmic,
996 &omap44xx_l4_abe__dmic_dma,
997 };
998
999 static struct omap_hwmod omap44xx_dmic_hwmod = {
1000 .name = "dmic",
1001 .class = &omap44xx_dmic_hwmod_class,
1002 .mpu_irqs = omap44xx_dmic_irqs,
1003 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs),
1004 .sdma_reqs = omap44xx_dmic_sdma_reqs,
1005 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
1006 .main_clk = "dmic_fck",
1007 .prcm = {
1008 .omap4 = {
1009 .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1010 },
1011 },
1012 .slaves = omap44xx_dmic_slaves,
1013 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
1014 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1015 };
1016
1017 /*
1018 * 'dsp' class
1019 * dsp sub-system
1020 */
1021
1022 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1023 .name = "dsp",
1024 };
1025
1026 /* dsp */
1027 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1028 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1029 };
1030
1031 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1032 { .name = "mmu_cache", .rst_shift = 1 },
1033 };
1034
1035 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1036 { .name = "dsp", .rst_shift = 0 },
1037 };
1038
1039 /* dsp -> iva */
1040 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1041 .master = &omap44xx_dsp_hwmod,
1042 .slave = &omap44xx_iva_hwmod,
1043 .clk = "dpll_iva_m5x2_ck",
1044 };
1045
1046 /* dsp master ports */
1047 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1048 &omap44xx_dsp__l3_main_1,
1049 &omap44xx_dsp__l4_abe,
1050 &omap44xx_dsp__iva,
1051 };
1052
1053 /* l4_cfg -> dsp */
1054 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1055 .master = &omap44xx_l4_cfg_hwmod,
1056 .slave = &omap44xx_dsp_hwmod,
1057 .clk = "l4_div_ck",
1058 .user = OCP_USER_MPU | OCP_USER_SDMA,
1059 };
1060
1061 /* dsp slave ports */
1062 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1063 &omap44xx_l4_cfg__dsp,
1064 };
1065
1066 /* Pseudo hwmod for reset control purpose only */
1067 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1068 .name = "dsp_c0",
1069 .class = &omap44xx_dsp_hwmod_class,
1070 .flags = HWMOD_INIT_NO_RESET,
1071 .rst_lines = omap44xx_dsp_c0_resets,
1072 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1073 .prcm = {
1074 .omap4 = {
1075 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1076 },
1077 },
1078 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1079 };
1080
1081 static struct omap_hwmod omap44xx_dsp_hwmod = {
1082 .name = "dsp",
1083 .class = &omap44xx_dsp_hwmod_class,
1084 .mpu_irqs = omap44xx_dsp_irqs,
1085 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
1086 .rst_lines = omap44xx_dsp_resets,
1087 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1088 .main_clk = "dsp_fck",
1089 .prcm = {
1090 .omap4 = {
1091 .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1092 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1093 },
1094 },
1095 .slaves = omap44xx_dsp_slaves,
1096 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1097 .masters = omap44xx_dsp_masters,
1098 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1099 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1100 };
1101
1102 /*
1103 * 'dss' class
1104 * display sub-system
1105 */
1106
1107 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1108 .rev_offs = 0x0000,
1109 .syss_offs = 0x0014,
1110 .sysc_flags = SYSS_HAS_RESET_STATUS,
1111 };
1112
1113 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1114 .name = "dss",
1115 .sysc = &omap44xx_dss_sysc,
1116 };
1117
1118 /* dss */
1119 /* dss master ports */
1120 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1121 &omap44xx_dss__l3_main_1,
1122 };
1123
1124 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1125 {
1126 .pa_start = 0x58000000,
1127 .pa_end = 0x5800007f,
1128 .flags = ADDR_TYPE_RT
1129 },
1130 };
1131
1132 /* l3_main_2 -> dss */
1133 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1134 .master = &omap44xx_l3_main_2_hwmod,
1135 .slave = &omap44xx_dss_hwmod,
1136 .clk = "l3_div_ck",
1137 .addr = omap44xx_dss_dma_addrs,
1138 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs),
1139 .user = OCP_USER_SDMA,
1140 };
1141
1142 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1143 {
1144 .pa_start = 0x48040000,
1145 .pa_end = 0x4804007f,
1146 .flags = ADDR_TYPE_RT
1147 },
1148 };
1149
1150 /* l4_per -> dss */
1151 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1152 .master = &omap44xx_l4_per_hwmod,
1153 .slave = &omap44xx_dss_hwmod,
1154 .clk = "l4_div_ck",
1155 .addr = omap44xx_dss_addrs,
1156 .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs),
1157 .user = OCP_USER_MPU,
1158 };
1159
1160 /* dss slave ports */
1161 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1162 &omap44xx_l3_main_2__dss,
1163 &omap44xx_l4_per__dss,
1164 };
1165
1166 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1167 { .role = "sys_clk", .clk = "dss_sys_clk" },
1168 { .role = "tv_clk", .clk = "dss_tv_clk" },
1169 { .role = "dss_clk", .clk = "dss_dss_clk" },
1170 { .role = "video_clk", .clk = "dss_48mhz_clk" },
1171 };
1172
1173 static struct omap_hwmod omap44xx_dss_hwmod = {
1174 .name = "dss_core",
1175 .class = &omap44xx_dss_hwmod_class,
1176 .main_clk = "dss_fck",
1177 .prcm = {
1178 .omap4 = {
1179 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1180 },
1181 },
1182 .opt_clks = dss_opt_clks,
1183 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1184 .slaves = omap44xx_dss_slaves,
1185 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1186 .masters = omap44xx_dss_masters,
1187 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1188 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1189 };
1190
1191 /*
1192 * 'dispc' class
1193 * display controller
1194 */
1195
1196 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1197 .rev_offs = 0x0000,
1198 .sysc_offs = 0x0010,
1199 .syss_offs = 0x0014,
1200 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1201 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1202 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1203 SYSS_HAS_RESET_STATUS),
1204 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1205 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1206 .sysc_fields = &omap_hwmod_sysc_type1,
1207 };
1208
1209 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1210 .name = "dispc",
1211 .sysc = &omap44xx_dispc_sysc,
1212 };
1213
1214 /* dss_dispc */
1215 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1216 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1217 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1218 };
1219
1220 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1221 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1222 };
1223
1224 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1225 {
1226 .pa_start = 0x58001000,
1227 .pa_end = 0x58001fff,
1228 .flags = ADDR_TYPE_RT
1229 },
1230 };
1231
1232 /* l3_main_2 -> dss_dispc */
1233 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1234 .master = &omap44xx_l3_main_2_hwmod,
1235 .slave = &omap44xx_dss_dispc_hwmod,
1236 .clk = "l3_div_ck",
1237 .addr = omap44xx_dss_dispc_dma_addrs,
1238 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
1239 .user = OCP_USER_SDMA,
1240 };
1241
1242 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1243 {
1244 .pa_start = 0x48041000,
1245 .pa_end = 0x48041fff,
1246 .flags = ADDR_TYPE_RT
1247 },
1248 };
1249
1250 /* l4_per -> dss_dispc */
1251 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1252 .master = &omap44xx_l4_per_hwmod,
1253 .slave = &omap44xx_dss_dispc_hwmod,
1254 .clk = "l4_div_ck",
1255 .addr = omap44xx_dss_dispc_addrs,
1256 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
1257 .user = OCP_USER_MPU,
1258 };
1259
1260 /* dss_dispc slave ports */
1261 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1262 &omap44xx_l3_main_2__dss_dispc,
1263 &omap44xx_l4_per__dss_dispc,
1264 };
1265
1266 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1267 .name = "dss_dispc",
1268 .class = &omap44xx_dispc_hwmod_class,
1269 .mpu_irqs = omap44xx_dss_dispc_irqs,
1270 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
1271 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
1272 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
1273 .main_clk = "dss_fck",
1274 .prcm = {
1275 .omap4 = {
1276 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1277 },
1278 },
1279 .slaves = omap44xx_dss_dispc_slaves,
1280 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1281 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1282 };
1283
1284 /*
1285 * 'dsi' class
1286 * display serial interface controller
1287 */
1288
1289 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1290 .rev_offs = 0x0000,
1291 .sysc_offs = 0x0010,
1292 .syss_offs = 0x0014,
1293 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1294 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1295 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1296 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1297 .sysc_fields = &omap_hwmod_sysc_type1,
1298 };
1299
1300 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1301 .name = "dsi",
1302 .sysc = &omap44xx_dsi_sysc,
1303 };
1304
1305 /* dss_dsi1 */
1306 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1307 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1308 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1309 };
1310
1311 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1312 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1313 };
1314
1315 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1316 {
1317 .pa_start = 0x58004000,
1318 .pa_end = 0x580041ff,
1319 .flags = ADDR_TYPE_RT
1320 },
1321 };
1322
1323 /* l3_main_2 -> dss_dsi1 */
1324 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1325 .master = &omap44xx_l3_main_2_hwmod,
1326 .slave = &omap44xx_dss_dsi1_hwmod,
1327 .clk = "l3_div_ck",
1328 .addr = omap44xx_dss_dsi1_dma_addrs,
1329 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
1330 .user = OCP_USER_SDMA,
1331 };
1332
1333 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1334 {
1335 .pa_start = 0x48044000,
1336 .pa_end = 0x480441ff,
1337 .flags = ADDR_TYPE_RT
1338 },
1339 };
1340
1341 /* l4_per -> dss_dsi1 */
1342 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1343 .master = &omap44xx_l4_per_hwmod,
1344 .slave = &omap44xx_dss_dsi1_hwmod,
1345 .clk = "l4_div_ck",
1346 .addr = omap44xx_dss_dsi1_addrs,
1347 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
1348 .user = OCP_USER_MPU,
1349 };
1350
1351 /* dss_dsi1 slave ports */
1352 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1353 &omap44xx_l3_main_2__dss_dsi1,
1354 &omap44xx_l4_per__dss_dsi1,
1355 };
1356
1357 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1358 .name = "dss_dsi1",
1359 .class = &omap44xx_dsi_hwmod_class,
1360 .mpu_irqs = omap44xx_dss_dsi1_irqs,
1361 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
1362 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
1363 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
1364 .main_clk = "dss_fck",
1365 .prcm = {
1366 .omap4 = {
1367 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1368 },
1369 },
1370 .slaves = omap44xx_dss_dsi1_slaves,
1371 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1372 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1373 };
1374
1375 /* dss_dsi2 */
1376 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1377 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1378 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1379 };
1380
1381 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1382 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1383 };
1384
1385 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1386 {
1387 .pa_start = 0x58005000,
1388 .pa_end = 0x580051ff,
1389 .flags = ADDR_TYPE_RT
1390 },
1391 };
1392
1393 /* l3_main_2 -> dss_dsi2 */
1394 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1395 .master = &omap44xx_l3_main_2_hwmod,
1396 .slave = &omap44xx_dss_dsi2_hwmod,
1397 .clk = "l3_div_ck",
1398 .addr = omap44xx_dss_dsi2_dma_addrs,
1399 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
1400 .user = OCP_USER_SDMA,
1401 };
1402
1403 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1404 {
1405 .pa_start = 0x48045000,
1406 .pa_end = 0x480451ff,
1407 .flags = ADDR_TYPE_RT
1408 },
1409 };
1410
1411 /* l4_per -> dss_dsi2 */
1412 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1413 .master = &omap44xx_l4_per_hwmod,
1414 .slave = &omap44xx_dss_dsi2_hwmod,
1415 .clk = "l4_div_ck",
1416 .addr = omap44xx_dss_dsi2_addrs,
1417 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
1418 .user = OCP_USER_MPU,
1419 };
1420
1421 /* dss_dsi2 slave ports */
1422 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1423 &omap44xx_l3_main_2__dss_dsi2,
1424 &omap44xx_l4_per__dss_dsi2,
1425 };
1426
1427 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1428 .name = "dss_dsi2",
1429 .class = &omap44xx_dsi_hwmod_class,
1430 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1431 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
1432 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1433 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
1434 .main_clk = "dss_fck",
1435 .prcm = {
1436 .omap4 = {
1437 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1438 },
1439 },
1440 .slaves = omap44xx_dss_dsi2_slaves,
1441 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1442 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1443 };
1444
1445 /*
1446 * 'hdmi' class
1447 * hdmi controller
1448 */
1449
1450 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1451 .rev_offs = 0x0000,
1452 .sysc_offs = 0x0010,
1453 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1454 SYSC_HAS_SOFTRESET),
1455 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1456 SIDLE_SMART_WKUP),
1457 .sysc_fields = &omap_hwmod_sysc_type2,
1458 };
1459
1460 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1461 .name = "hdmi",
1462 .sysc = &omap44xx_hdmi_sysc,
1463 };
1464
1465 /* dss_hdmi */
1466 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1467 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1468 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1469 };
1470
1471 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1472 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1473 };
1474
1475 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1476 {
1477 .pa_start = 0x58006000,
1478 .pa_end = 0x58006fff,
1479 .flags = ADDR_TYPE_RT
1480 },
1481 };
1482
1483 /* l3_main_2 -> dss_hdmi */
1484 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1485 .master = &omap44xx_l3_main_2_hwmod,
1486 .slave = &omap44xx_dss_hdmi_hwmod,
1487 .clk = "l3_div_ck",
1488 .addr = omap44xx_dss_hdmi_dma_addrs,
1489 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
1490 .user = OCP_USER_SDMA,
1491 };
1492
1493 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1494 {
1495 .pa_start = 0x48046000,
1496 .pa_end = 0x48046fff,
1497 .flags = ADDR_TYPE_RT
1498 },
1499 };
1500
1501 /* l4_per -> dss_hdmi */
1502 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1503 .master = &omap44xx_l4_per_hwmod,
1504 .slave = &omap44xx_dss_hdmi_hwmod,
1505 .clk = "l4_div_ck",
1506 .addr = omap44xx_dss_hdmi_addrs,
1507 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
1508 .user = OCP_USER_MPU,
1509 };
1510
1511 /* dss_hdmi slave ports */
1512 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1513 &omap44xx_l3_main_2__dss_hdmi,
1514 &omap44xx_l4_per__dss_hdmi,
1515 };
1516
1517 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1518 .name = "dss_hdmi",
1519 .class = &omap44xx_hdmi_hwmod_class,
1520 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1521 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
1522 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1523 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
1524 .main_clk = "dss_fck",
1525 .prcm = {
1526 .omap4 = {
1527 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1528 },
1529 },
1530 .slaves = omap44xx_dss_hdmi_slaves,
1531 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1532 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1533 };
1534
1535 /*
1536 * 'rfbi' class
1537 * remote frame buffer interface
1538 */
1539
1540 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1541 .rev_offs = 0x0000,
1542 .sysc_offs = 0x0010,
1543 .syss_offs = 0x0014,
1544 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1545 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1546 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1547 .sysc_fields = &omap_hwmod_sysc_type1,
1548 };
1549
1550 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1551 .name = "rfbi",
1552 .sysc = &omap44xx_rfbi_sysc,
1553 };
1554
1555 /* dss_rfbi */
1556 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1557 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1558 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1559 };
1560
1561 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1562 {
1563 .pa_start = 0x58002000,
1564 .pa_end = 0x580020ff,
1565 .flags = ADDR_TYPE_RT
1566 },
1567 };
1568
1569 /* l3_main_2 -> dss_rfbi */
1570 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1571 .master = &omap44xx_l3_main_2_hwmod,
1572 .slave = &omap44xx_dss_rfbi_hwmod,
1573 .clk = "l3_div_ck",
1574 .addr = omap44xx_dss_rfbi_dma_addrs,
1575 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
1576 .user = OCP_USER_SDMA,
1577 };
1578
1579 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1580 {
1581 .pa_start = 0x48042000,
1582 .pa_end = 0x480420ff,
1583 .flags = ADDR_TYPE_RT
1584 },
1585 };
1586
1587 /* l4_per -> dss_rfbi */
1588 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1589 .master = &omap44xx_l4_per_hwmod,
1590 .slave = &omap44xx_dss_rfbi_hwmod,
1591 .clk = "l4_div_ck",
1592 .addr = omap44xx_dss_rfbi_addrs,
1593 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
1594 .user = OCP_USER_MPU,
1595 };
1596
1597 /* dss_rfbi slave ports */
1598 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1599 &omap44xx_l3_main_2__dss_rfbi,
1600 &omap44xx_l4_per__dss_rfbi,
1601 };
1602
1603 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1604 .name = "dss_rfbi",
1605 .class = &omap44xx_rfbi_hwmod_class,
1606 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1607 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
1608 .main_clk = "dss_fck",
1609 .prcm = {
1610 .omap4 = {
1611 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1612 },
1613 },
1614 .slaves = omap44xx_dss_rfbi_slaves,
1615 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1616 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1617 };
1618
1619 /*
1620 * 'venc' class
1621 * video encoder
1622 */
1623
1624 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1625 .name = "venc",
1626 };
1627
1628 /* dss_venc */
1629 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1630 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1631 {
1632 .pa_start = 0x58003000,
1633 .pa_end = 0x580030ff,
1634 .flags = ADDR_TYPE_RT
1635 },
1636 };
1637
1638 /* l3_main_2 -> dss_venc */
1639 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1640 .master = &omap44xx_l3_main_2_hwmod,
1641 .slave = &omap44xx_dss_venc_hwmod,
1642 .clk = "l3_div_ck",
1643 .addr = omap44xx_dss_venc_dma_addrs,
1644 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
1645 .user = OCP_USER_SDMA,
1646 };
1647
1648 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1649 {
1650 .pa_start = 0x48043000,
1651 .pa_end = 0x480430ff,
1652 .flags = ADDR_TYPE_RT
1653 },
1654 };
1655
1656 /* l4_per -> dss_venc */
1657 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1658 .master = &omap44xx_l4_per_hwmod,
1659 .slave = &omap44xx_dss_venc_hwmod,
1660 .clk = "l4_div_ck",
1661 .addr = omap44xx_dss_venc_addrs,
1662 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs),
1663 .user = OCP_USER_MPU,
1664 };
1665
1666 /* dss_venc slave ports */
1667 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1668 &omap44xx_l3_main_2__dss_venc,
1669 &omap44xx_l4_per__dss_venc,
1670 };
1671
1672 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1673 .name = "dss_venc",
1674 .class = &omap44xx_venc_hwmod_class,
1675 .main_clk = "dss_fck",
1676 .prcm = {
1677 .omap4 = {
1678 .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1679 },
1680 },
1681 .slaves = omap44xx_dss_venc_slaves,
1682 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1683 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1684 };
1685
1686 /*
1687 * 'gpio' class
1688 * general purpose io module
1689 */
1690
1691 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1692 .rev_offs = 0x0000,
1693 .sysc_offs = 0x0010,
1694 .syss_offs = 0x0114,
1695 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1696 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1697 SYSS_HAS_RESET_STATUS),
1698 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1699 SIDLE_SMART_WKUP),
1700 .sysc_fields = &omap_hwmod_sysc_type1,
1701 };
1702
1703 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1704 .name = "gpio",
1705 .sysc = &omap44xx_gpio_sysc,
1706 .rev = 2,
1707 };
1708
1709 /* gpio dev_attr */
1710 static struct omap_gpio_dev_attr gpio_dev_attr = {
1711 .bank_width = 32,
1712 .dbck_flag = true,
1713 };
1714
1715 /* gpio1 */
1716 static struct omap_hwmod omap44xx_gpio1_hwmod;
1717 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1718 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1719 };
1720
1721 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1722 {
1723 .pa_start = 0x4a310000,
1724 .pa_end = 0x4a3101ff,
1725 .flags = ADDR_TYPE_RT
1726 },
1727 };
1728
1729 /* l4_wkup -> gpio1 */
1730 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1731 .master = &omap44xx_l4_wkup_hwmod,
1732 .slave = &omap44xx_gpio1_hwmod,
1733 .clk = "l4_wkup_clk_mux_ck",
1734 .addr = omap44xx_gpio1_addrs,
1735 .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
1736 .user = OCP_USER_MPU | OCP_USER_SDMA,
1737 };
1738
1739 /* gpio1 slave ports */
1740 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1741 &omap44xx_l4_wkup__gpio1,
1742 };
1743
1744 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1745 { .role = "dbclk", .clk = "gpio1_dbclk" },
1746 };
1747
1748 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1749 .name = "gpio1",
1750 .class = &omap44xx_gpio_hwmod_class,
1751 .mpu_irqs = omap44xx_gpio1_irqs,
1752 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
1753 .main_clk = "gpio1_ick",
1754 .prcm = {
1755 .omap4 = {
1756 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1757 },
1758 },
1759 .opt_clks = gpio1_opt_clks,
1760 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1761 .dev_attr = &gpio_dev_attr,
1762 .slaves = omap44xx_gpio1_slaves,
1763 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
1764 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1765 };
1766
1767 /* gpio2 */
1768 static struct omap_hwmod omap44xx_gpio2_hwmod;
1769 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1770 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1771 };
1772
1773 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1774 {
1775 .pa_start = 0x48055000,
1776 .pa_end = 0x480551ff,
1777 .flags = ADDR_TYPE_RT
1778 },
1779 };
1780
1781 /* l4_per -> gpio2 */
1782 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1783 .master = &omap44xx_l4_per_hwmod,
1784 .slave = &omap44xx_gpio2_hwmod,
1785 .clk = "l4_div_ck",
1786 .addr = omap44xx_gpio2_addrs,
1787 .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
1788 .user = OCP_USER_MPU | OCP_USER_SDMA,
1789 };
1790
1791 /* gpio2 slave ports */
1792 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1793 &omap44xx_l4_per__gpio2,
1794 };
1795
1796 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1797 { .role = "dbclk", .clk = "gpio2_dbclk" },
1798 };
1799
1800 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1801 .name = "gpio2",
1802 .class = &omap44xx_gpio_hwmod_class,
1803 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1804 .mpu_irqs = omap44xx_gpio2_irqs,
1805 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
1806 .main_clk = "gpio2_ick",
1807 .prcm = {
1808 .omap4 = {
1809 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1810 },
1811 },
1812 .opt_clks = gpio2_opt_clks,
1813 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1814 .dev_attr = &gpio_dev_attr,
1815 .slaves = omap44xx_gpio2_slaves,
1816 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
1817 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1818 };
1819
1820 /* gpio3 */
1821 static struct omap_hwmod omap44xx_gpio3_hwmod;
1822 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1823 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1824 };
1825
1826 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1827 {
1828 .pa_start = 0x48057000,
1829 .pa_end = 0x480571ff,
1830 .flags = ADDR_TYPE_RT
1831 },
1832 };
1833
1834 /* l4_per -> gpio3 */
1835 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1836 .master = &omap44xx_l4_per_hwmod,
1837 .slave = &omap44xx_gpio3_hwmod,
1838 .clk = "l4_div_ck",
1839 .addr = omap44xx_gpio3_addrs,
1840 .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
1841 .user = OCP_USER_MPU | OCP_USER_SDMA,
1842 };
1843
1844 /* gpio3 slave ports */
1845 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1846 &omap44xx_l4_per__gpio3,
1847 };
1848
1849 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1850 { .role = "dbclk", .clk = "gpio3_dbclk" },
1851 };
1852
1853 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1854 .name = "gpio3",
1855 .class = &omap44xx_gpio_hwmod_class,
1856 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1857 .mpu_irqs = omap44xx_gpio3_irqs,
1858 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
1859 .main_clk = "gpio3_ick",
1860 .prcm = {
1861 .omap4 = {
1862 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1863 },
1864 },
1865 .opt_clks = gpio3_opt_clks,
1866 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1867 .dev_attr = &gpio_dev_attr,
1868 .slaves = omap44xx_gpio3_slaves,
1869 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
1870 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1871 };
1872
1873 /* gpio4 */
1874 static struct omap_hwmod omap44xx_gpio4_hwmod;
1875 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1876 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1877 };
1878
1879 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1880 {
1881 .pa_start = 0x48059000,
1882 .pa_end = 0x480591ff,
1883 .flags = ADDR_TYPE_RT
1884 },
1885 };
1886
1887 /* l4_per -> gpio4 */
1888 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1889 .master = &omap44xx_l4_per_hwmod,
1890 .slave = &omap44xx_gpio4_hwmod,
1891 .clk = "l4_div_ck",
1892 .addr = omap44xx_gpio4_addrs,
1893 .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
1894 .user = OCP_USER_MPU | OCP_USER_SDMA,
1895 };
1896
1897 /* gpio4 slave ports */
1898 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1899 &omap44xx_l4_per__gpio4,
1900 };
1901
1902 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1903 { .role = "dbclk", .clk = "gpio4_dbclk" },
1904 };
1905
1906 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1907 .name = "gpio4",
1908 .class = &omap44xx_gpio_hwmod_class,
1909 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1910 .mpu_irqs = omap44xx_gpio4_irqs,
1911 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
1912 .main_clk = "gpio4_ick",
1913 .prcm = {
1914 .omap4 = {
1915 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1916 },
1917 },
1918 .opt_clks = gpio4_opt_clks,
1919 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1920 .dev_attr = &gpio_dev_attr,
1921 .slaves = omap44xx_gpio4_slaves,
1922 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
1923 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1924 };
1925
1926 /* gpio5 */
1927 static struct omap_hwmod omap44xx_gpio5_hwmod;
1928 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1929 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1930 };
1931
1932 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1933 {
1934 .pa_start = 0x4805b000,
1935 .pa_end = 0x4805b1ff,
1936 .flags = ADDR_TYPE_RT
1937 },
1938 };
1939
1940 /* l4_per -> gpio5 */
1941 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1942 .master = &omap44xx_l4_per_hwmod,
1943 .slave = &omap44xx_gpio5_hwmod,
1944 .clk = "l4_div_ck",
1945 .addr = omap44xx_gpio5_addrs,
1946 .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
1947 .user = OCP_USER_MPU | OCP_USER_SDMA,
1948 };
1949
1950 /* gpio5 slave ports */
1951 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1952 &omap44xx_l4_per__gpio5,
1953 };
1954
1955 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1956 { .role = "dbclk", .clk = "gpio5_dbclk" },
1957 };
1958
1959 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1960 .name = "gpio5",
1961 .class = &omap44xx_gpio_hwmod_class,
1962 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1963 .mpu_irqs = omap44xx_gpio5_irqs,
1964 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
1965 .main_clk = "gpio5_ick",
1966 .prcm = {
1967 .omap4 = {
1968 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1969 },
1970 },
1971 .opt_clks = gpio5_opt_clks,
1972 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1973 .dev_attr = &gpio_dev_attr,
1974 .slaves = omap44xx_gpio5_slaves,
1975 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
1976 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1977 };
1978
1979 /* gpio6 */
1980 static struct omap_hwmod omap44xx_gpio6_hwmod;
1981 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1982 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1983 };
1984
1985 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1986 {
1987 .pa_start = 0x4805d000,
1988 .pa_end = 0x4805d1ff,
1989 .flags = ADDR_TYPE_RT
1990 },
1991 };
1992
1993 /* l4_per -> gpio6 */
1994 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1995 .master = &omap44xx_l4_per_hwmod,
1996 .slave = &omap44xx_gpio6_hwmod,
1997 .clk = "l4_div_ck",
1998 .addr = omap44xx_gpio6_addrs,
1999 .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
2000 .user = OCP_USER_MPU | OCP_USER_SDMA,
2001 };
2002
2003 /* gpio6 slave ports */
2004 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2005 &omap44xx_l4_per__gpio6,
2006 };
2007
2008 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2009 { .role = "dbclk", .clk = "gpio6_dbclk" },
2010 };
2011
2012 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2013 .name = "gpio6",
2014 .class = &omap44xx_gpio_hwmod_class,
2015 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2016 .mpu_irqs = omap44xx_gpio6_irqs,
2017 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
2018 .main_clk = "gpio6_ick",
2019 .prcm = {
2020 .omap4 = {
2021 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
2022 },
2023 },
2024 .opt_clks = gpio6_opt_clks,
2025 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2026 .dev_attr = &gpio_dev_attr,
2027 .slaves = omap44xx_gpio6_slaves,
2028 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
2029 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2030 };
2031
2032 /*
2033 * 'hsi' class
2034 * mipi high-speed synchronous serial interface (multichannel and full-duplex
2035 * serial if)
2036 */
2037
2038 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2039 .rev_offs = 0x0000,
2040 .sysc_offs = 0x0010,
2041 .syss_offs = 0x0014,
2042 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2043 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2044 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2045 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2046 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2047 MSTANDBY_SMART),
2048 .sysc_fields = &omap_hwmod_sysc_type1,
2049 };
2050
2051 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2052 .name = "hsi",
2053 .sysc = &omap44xx_hsi_sysc,
2054 };
2055
2056 /* hsi */
2057 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2058 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2059 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2060 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2061 };
2062
2063 /* hsi master ports */
2064 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2065 &omap44xx_hsi__l3_main_2,
2066 };
2067
2068 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2069 {
2070 .pa_start = 0x4a058000,
2071 .pa_end = 0x4a05bfff,
2072 .flags = ADDR_TYPE_RT
2073 },
2074 };
2075
2076 /* l4_cfg -> hsi */
2077 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2078 .master = &omap44xx_l4_cfg_hwmod,
2079 .slave = &omap44xx_hsi_hwmod,
2080 .clk = "l4_div_ck",
2081 .addr = omap44xx_hsi_addrs,
2082 .addr_cnt = ARRAY_SIZE(omap44xx_hsi_addrs),
2083 .user = OCP_USER_MPU | OCP_USER_SDMA,
2084 };
2085
2086 /* hsi slave ports */
2087 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2088 &omap44xx_l4_cfg__hsi,
2089 };
2090
2091 static struct omap_hwmod omap44xx_hsi_hwmod = {
2092 .name = "hsi",
2093 .class = &omap44xx_hsi_hwmod_class,
2094 .mpu_irqs = omap44xx_hsi_irqs,
2095 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs),
2096 .main_clk = "hsi_fck",
2097 .prcm = {
2098 .omap4 = {
2099 .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2100 },
2101 },
2102 .slaves = omap44xx_hsi_slaves,
2103 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2104 .masters = omap44xx_hsi_masters,
2105 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2106 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2107 };
2108
2109 /*
2110 * 'i2c' class
2111 * multimaster high-speed i2c controller
2112 */
2113
2114 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2115 .sysc_offs = 0x0010,
2116 .syss_offs = 0x0090,
2117 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2118 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2119 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2120 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2121 SIDLE_SMART_WKUP),
2122 .sysc_fields = &omap_hwmod_sysc_type1,
2123 };
2124
2125 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2126 .name = "i2c",
2127 .sysc = &omap44xx_i2c_sysc,
2128 };
2129
2130 /* i2c1 */
2131 static struct omap_hwmod omap44xx_i2c1_hwmod;
2132 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2133 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2134 };
2135
2136 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2137 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2138 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2139 };
2140
2141 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2142 {
2143 .pa_start = 0x48070000,
2144 .pa_end = 0x480700ff,
2145 .flags = ADDR_TYPE_RT
2146 },
2147 };
2148
2149 /* l4_per -> i2c1 */
2150 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2151 .master = &omap44xx_l4_per_hwmod,
2152 .slave = &omap44xx_i2c1_hwmod,
2153 .clk = "l4_div_ck",
2154 .addr = omap44xx_i2c1_addrs,
2155 .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
2156 .user = OCP_USER_MPU | OCP_USER_SDMA,
2157 };
2158
2159 /* i2c1 slave ports */
2160 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2161 &omap44xx_l4_per__i2c1,
2162 };
2163
2164 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2165 .name = "i2c1",
2166 .class = &omap44xx_i2c_hwmod_class,
2167 .flags = HWMOD_INIT_NO_RESET,
2168 .mpu_irqs = omap44xx_i2c1_irqs,
2169 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
2170 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
2171 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
2172 .main_clk = "i2c1_fck",
2173 .prcm = {
2174 .omap4 = {
2175 .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
2176 },
2177 },
2178 .slaves = omap44xx_i2c1_slaves,
2179 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
2180 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2181 };
2182
2183 /* i2c2 */
2184 static struct omap_hwmod omap44xx_i2c2_hwmod;
2185 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2186 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2187 };
2188
2189 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2190 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2191 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2192 };
2193
2194 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2195 {
2196 .pa_start = 0x48072000,
2197 .pa_end = 0x480720ff,
2198 .flags = ADDR_TYPE_RT
2199 },
2200 };
2201
2202 /* l4_per -> i2c2 */
2203 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2204 .master = &omap44xx_l4_per_hwmod,
2205 .slave = &omap44xx_i2c2_hwmod,
2206 .clk = "l4_div_ck",
2207 .addr = omap44xx_i2c2_addrs,
2208 .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
2209 .user = OCP_USER_MPU | OCP_USER_SDMA,
2210 };
2211
2212 /* i2c2 slave ports */
2213 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2214 &omap44xx_l4_per__i2c2,
2215 };
2216
2217 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2218 .name = "i2c2",
2219 .class = &omap44xx_i2c_hwmod_class,
2220 .flags = HWMOD_INIT_NO_RESET,
2221 .mpu_irqs = omap44xx_i2c2_irqs,
2222 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
2223 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
2224 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
2225 .main_clk = "i2c2_fck",
2226 .prcm = {
2227 .omap4 = {
2228 .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
2229 },
2230 },
2231 .slaves = omap44xx_i2c2_slaves,
2232 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
2233 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2234 };
2235
2236 /* i2c3 */
2237 static struct omap_hwmod omap44xx_i2c3_hwmod;
2238 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2239 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2240 };
2241
2242 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2243 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2244 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2245 };
2246
2247 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2248 {
2249 .pa_start = 0x48060000,
2250 .pa_end = 0x480600ff,
2251 .flags = ADDR_TYPE_RT
2252 },
2253 };
2254
2255 /* l4_per -> i2c3 */
2256 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2257 .master = &omap44xx_l4_per_hwmod,
2258 .slave = &omap44xx_i2c3_hwmod,
2259 .clk = "l4_div_ck",
2260 .addr = omap44xx_i2c3_addrs,
2261 .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
2262 .user = OCP_USER_MPU | OCP_USER_SDMA,
2263 };
2264
2265 /* i2c3 slave ports */
2266 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2267 &omap44xx_l4_per__i2c3,
2268 };
2269
2270 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2271 .name = "i2c3",
2272 .class = &omap44xx_i2c_hwmod_class,
2273 .flags = HWMOD_INIT_NO_RESET,
2274 .mpu_irqs = omap44xx_i2c3_irqs,
2275 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
2276 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
2277 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
2278 .main_clk = "i2c3_fck",
2279 .prcm = {
2280 .omap4 = {
2281 .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
2282 },
2283 },
2284 .slaves = omap44xx_i2c3_slaves,
2285 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
2286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2287 };
2288
2289 /* i2c4 */
2290 static struct omap_hwmod omap44xx_i2c4_hwmod;
2291 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2292 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2293 };
2294
2295 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2296 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2297 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2298 };
2299
2300 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2301 {
2302 .pa_start = 0x48350000,
2303 .pa_end = 0x483500ff,
2304 .flags = ADDR_TYPE_RT
2305 },
2306 };
2307
2308 /* l4_per -> i2c4 */
2309 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2310 .master = &omap44xx_l4_per_hwmod,
2311 .slave = &omap44xx_i2c4_hwmod,
2312 .clk = "l4_div_ck",
2313 .addr = omap44xx_i2c4_addrs,
2314 .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
2315 .user = OCP_USER_MPU | OCP_USER_SDMA,
2316 };
2317
2318 /* i2c4 slave ports */
2319 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2320 &omap44xx_l4_per__i2c4,
2321 };
2322
2323 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2324 .name = "i2c4",
2325 .class = &omap44xx_i2c_hwmod_class,
2326 .flags = HWMOD_INIT_NO_RESET,
2327 .mpu_irqs = omap44xx_i2c4_irqs,
2328 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
2329 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
2330 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
2331 .main_clk = "i2c4_fck",
2332 .prcm = {
2333 .omap4 = {
2334 .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
2335 },
2336 },
2337 .slaves = omap44xx_i2c4_slaves,
2338 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
2339 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2340 };
2341
2342 /*
2343 * 'ipu' class
2344 * imaging processor unit
2345 */
2346
2347 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2348 .name = "ipu",
2349 };
2350
2351 /* ipu */
2352 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2353 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2354 };
2355
2356 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2357 { .name = "cpu0", .rst_shift = 0 },
2358 };
2359
2360 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2361 { .name = "cpu1", .rst_shift = 1 },
2362 };
2363
2364 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2365 { .name = "mmu_cache", .rst_shift = 2 },
2366 };
2367
2368 /* ipu master ports */
2369 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2370 &omap44xx_ipu__l3_main_2,
2371 };
2372
2373 /* l3_main_2 -> ipu */
2374 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2375 .master = &omap44xx_l3_main_2_hwmod,
2376 .slave = &omap44xx_ipu_hwmod,
2377 .clk = "l3_div_ck",
2378 .user = OCP_USER_MPU | OCP_USER_SDMA,
2379 };
2380
2381 /* ipu slave ports */
2382 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2383 &omap44xx_l3_main_2__ipu,
2384 };
2385
2386 /* Pseudo hwmod for reset control purpose only */
2387 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2388 .name = "ipu_c0",
2389 .class = &omap44xx_ipu_hwmod_class,
2390 .flags = HWMOD_INIT_NO_RESET,
2391 .rst_lines = omap44xx_ipu_c0_resets,
2392 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2393 .prcm = {
2394 .omap4 = {
2395 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2396 },
2397 },
2398 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2399 };
2400
2401 /* Pseudo hwmod for reset control purpose only */
2402 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2403 .name = "ipu_c1",
2404 .class = &omap44xx_ipu_hwmod_class,
2405 .flags = HWMOD_INIT_NO_RESET,
2406 .rst_lines = omap44xx_ipu_c1_resets,
2407 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2408 .prcm = {
2409 .omap4 = {
2410 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2411 },
2412 },
2413 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2414 };
2415
2416 static struct omap_hwmod omap44xx_ipu_hwmod = {
2417 .name = "ipu",
2418 .class = &omap44xx_ipu_hwmod_class,
2419 .mpu_irqs = omap44xx_ipu_irqs,
2420 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs),
2421 .rst_lines = omap44xx_ipu_resets,
2422 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2423 .main_clk = "ipu_fck",
2424 .prcm = {
2425 .omap4 = {
2426 .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2427 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2428 },
2429 },
2430 .slaves = omap44xx_ipu_slaves,
2431 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2432 .masters = omap44xx_ipu_masters,
2433 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2434 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2435 };
2436
2437 /*
2438 * 'iss' class
2439 * external images sensor pixel data processor
2440 */
2441
2442 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2443 .rev_offs = 0x0000,
2444 .sysc_offs = 0x0010,
2445 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2446 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2447 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2448 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2449 MSTANDBY_SMART),
2450 .sysc_fields = &omap_hwmod_sysc_type2,
2451 };
2452
2453 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2454 .name = "iss",
2455 .sysc = &omap44xx_iss_sysc,
2456 };
2457
2458 /* iss */
2459 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2460 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2461 };
2462
2463 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2464 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2465 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2466 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2467 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2468 };
2469
2470 /* iss master ports */
2471 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2472 &omap44xx_iss__l3_main_2,
2473 };
2474
2475 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2476 {
2477 .pa_start = 0x52000000,
2478 .pa_end = 0x520000ff,
2479 .flags = ADDR_TYPE_RT
2480 },
2481 };
2482
2483 /* l3_main_2 -> iss */
2484 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2485 .master = &omap44xx_l3_main_2_hwmod,
2486 .slave = &omap44xx_iss_hwmod,
2487 .clk = "l3_div_ck",
2488 .addr = omap44xx_iss_addrs,
2489 .addr_cnt = ARRAY_SIZE(omap44xx_iss_addrs),
2490 .user = OCP_USER_MPU | OCP_USER_SDMA,
2491 };
2492
2493 /* iss slave ports */
2494 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2495 &omap44xx_l3_main_2__iss,
2496 };
2497
2498 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2499 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2500 };
2501
2502 static struct omap_hwmod omap44xx_iss_hwmod = {
2503 .name = "iss",
2504 .class = &omap44xx_iss_hwmod_class,
2505 .mpu_irqs = omap44xx_iss_irqs,
2506 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs),
2507 .sdma_reqs = omap44xx_iss_sdma_reqs,
2508 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
2509 .main_clk = "iss_fck",
2510 .prcm = {
2511 .omap4 = {
2512 .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2513 },
2514 },
2515 .opt_clks = iss_opt_clks,
2516 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2517 .slaves = omap44xx_iss_slaves,
2518 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2519 .masters = omap44xx_iss_masters,
2520 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2521 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2522 };
2523
2524 /*
2525 * 'iva' class
2526 * multi-standard video encoder/decoder hardware accelerator
2527 */
2528
2529 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2530 .name = "iva",
2531 };
2532
2533 /* iva */
2534 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2535 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2536 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2537 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2538 };
2539
2540 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2541 { .name = "logic", .rst_shift = 2 },
2542 };
2543
2544 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2545 { .name = "seq0", .rst_shift = 0 },
2546 };
2547
2548 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2549 { .name = "seq1", .rst_shift = 1 },
2550 };
2551
2552 /* iva master ports */
2553 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2554 &omap44xx_iva__l3_main_2,
2555 &omap44xx_iva__l3_instr,
2556 };
2557
2558 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2559 {
2560 .pa_start = 0x5a000000,
2561 .pa_end = 0x5a07ffff,
2562 .flags = ADDR_TYPE_RT
2563 },
2564 };
2565
2566 /* l3_main_2 -> iva */
2567 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2568 .master = &omap44xx_l3_main_2_hwmod,
2569 .slave = &omap44xx_iva_hwmod,
2570 .clk = "l3_div_ck",
2571 .addr = omap44xx_iva_addrs,
2572 .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs),
2573 .user = OCP_USER_MPU,
2574 };
2575
2576 /* iva slave ports */
2577 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2578 &omap44xx_dsp__iva,
2579 &omap44xx_l3_main_2__iva,
2580 };
2581
2582 /* Pseudo hwmod for reset control purpose only */
2583 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2584 .name = "iva_seq0",
2585 .class = &omap44xx_iva_hwmod_class,
2586 .flags = HWMOD_INIT_NO_RESET,
2587 .rst_lines = omap44xx_iva_seq0_resets,
2588 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2589 .prcm = {
2590 .omap4 = {
2591 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2592 },
2593 },
2594 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2595 };
2596
2597 /* Pseudo hwmod for reset control purpose only */
2598 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2599 .name = "iva_seq1",
2600 .class = &omap44xx_iva_hwmod_class,
2601 .flags = HWMOD_INIT_NO_RESET,
2602 .rst_lines = omap44xx_iva_seq1_resets,
2603 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2604 .prcm = {
2605 .omap4 = {
2606 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2607 },
2608 },
2609 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2610 };
2611
2612 static struct omap_hwmod omap44xx_iva_hwmod = {
2613 .name = "iva",
2614 .class = &omap44xx_iva_hwmod_class,
2615 .mpu_irqs = omap44xx_iva_irqs,
2616 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs),
2617 .rst_lines = omap44xx_iva_resets,
2618 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2619 .main_clk = "iva_fck",
2620 .prcm = {
2621 .omap4 = {
2622 .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2623 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2624 },
2625 },
2626 .slaves = omap44xx_iva_slaves,
2627 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2628 .masters = omap44xx_iva_masters,
2629 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2630 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2631 };
2632
2633 /*
2634 * 'kbd' class
2635 * keyboard controller
2636 */
2637
2638 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2639 .rev_offs = 0x0000,
2640 .sysc_offs = 0x0010,
2641 .syss_offs = 0x0014,
2642 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2643 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2644 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2645 SYSS_HAS_RESET_STATUS),
2646 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2647 .sysc_fields = &omap_hwmod_sysc_type1,
2648 };
2649
2650 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2651 .name = "kbd",
2652 .sysc = &omap44xx_kbd_sysc,
2653 };
2654
2655 /* kbd */
2656 static struct omap_hwmod omap44xx_kbd_hwmod;
2657 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2658 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2659 };
2660
2661 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2662 {
2663 .pa_start = 0x4a31c000,
2664 .pa_end = 0x4a31c07f,
2665 .flags = ADDR_TYPE_RT
2666 },
2667 };
2668
2669 /* l4_wkup -> kbd */
2670 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2671 .master = &omap44xx_l4_wkup_hwmod,
2672 .slave = &omap44xx_kbd_hwmod,
2673 .clk = "l4_wkup_clk_mux_ck",
2674 .addr = omap44xx_kbd_addrs,
2675 .addr_cnt = ARRAY_SIZE(omap44xx_kbd_addrs),
2676 .user = OCP_USER_MPU | OCP_USER_SDMA,
2677 };
2678
2679 /* kbd slave ports */
2680 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2681 &omap44xx_l4_wkup__kbd,
2682 };
2683
2684 static struct omap_hwmod omap44xx_kbd_hwmod = {
2685 .name = "kbd",
2686 .class = &omap44xx_kbd_hwmod_class,
2687 .mpu_irqs = omap44xx_kbd_irqs,
2688 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs),
2689 .main_clk = "kbd_fck",
2690 .prcm = {
2691 .omap4 = {
2692 .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2693 },
2694 },
2695 .slaves = omap44xx_kbd_slaves,
2696 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2697 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2698 };
2699
2700 /*
2701 * 'mailbox' class
2702 * mailbox module allowing communication between the on-chip processors using a
2703 * queued mailbox-interrupt mechanism.
2704 */
2705
2706 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2707 .rev_offs = 0x0000,
2708 .sysc_offs = 0x0010,
2709 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2710 SYSC_HAS_SOFTRESET),
2711 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2712 .sysc_fields = &omap_hwmod_sysc_type2,
2713 };
2714
2715 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2716 .name = "mailbox",
2717 .sysc = &omap44xx_mailbox_sysc,
2718 };
2719
2720 /* mailbox */
2721 static struct omap_hwmod omap44xx_mailbox_hwmod;
2722 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2723 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2724 };
2725
2726 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2727 {
2728 .pa_start = 0x4a0f4000,
2729 .pa_end = 0x4a0f41ff,
2730 .flags = ADDR_TYPE_RT
2731 },
2732 };
2733
2734 /* l4_cfg -> mailbox */
2735 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2736 .master = &omap44xx_l4_cfg_hwmod,
2737 .slave = &omap44xx_mailbox_hwmod,
2738 .clk = "l4_div_ck",
2739 .addr = omap44xx_mailbox_addrs,
2740 .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
2741 .user = OCP_USER_MPU | OCP_USER_SDMA,
2742 };
2743
2744 /* mailbox slave ports */
2745 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2746 &omap44xx_l4_cfg__mailbox,
2747 };
2748
2749 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2750 .name = "mailbox",
2751 .class = &omap44xx_mailbox_hwmod_class,
2752 .mpu_irqs = omap44xx_mailbox_irqs,
2753 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs),
2754 .prcm = {
2755 .omap4 = {
2756 .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2757 },
2758 },
2759 .slaves = omap44xx_mailbox_slaves,
2760 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2761 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2762 };
2763
2764 /*
2765 * 'mcbsp' class
2766 * multi channel buffered serial port controller
2767 */
2768
2769 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2770 .sysc_offs = 0x008c,
2771 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2772 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2773 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2774 .sysc_fields = &omap_hwmod_sysc_type1,
2775 };
2776
2777 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2778 .name = "mcbsp",
2779 .sysc = &omap44xx_mcbsp_sysc,
2780 .rev = MCBSP_CONFIG_TYPE4,
2781 };
2782
2783 /* mcbsp1 */
2784 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2785 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2786 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2787 };
2788
2789 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2790 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2791 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2792 };
2793
2794 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2795 {
2796 .name = "mpu",
2797 .pa_start = 0x40122000,
2798 .pa_end = 0x401220ff,
2799 .flags = ADDR_TYPE_RT
2800 },
2801 };
2802
2803 /* l4_abe -> mcbsp1 */
2804 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2805 .master = &omap44xx_l4_abe_hwmod,
2806 .slave = &omap44xx_mcbsp1_hwmod,
2807 .clk = "ocp_abe_iclk",
2808 .addr = omap44xx_mcbsp1_addrs,
2809 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
2810 .user = OCP_USER_MPU,
2811 };
2812
2813 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2814 {
2815 .name = "dma",
2816 .pa_start = 0x49022000,
2817 .pa_end = 0x490220ff,
2818 .flags = ADDR_TYPE_RT
2819 },
2820 };
2821
2822 /* l4_abe -> mcbsp1 (dma) */
2823 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2824 .master = &omap44xx_l4_abe_hwmod,
2825 .slave = &omap44xx_mcbsp1_hwmod,
2826 .clk = "ocp_abe_iclk",
2827 .addr = omap44xx_mcbsp1_dma_addrs,
2828 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
2829 .user = OCP_USER_SDMA,
2830 };
2831
2832 /* mcbsp1 slave ports */
2833 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2834 &omap44xx_l4_abe__mcbsp1,
2835 &omap44xx_l4_abe__mcbsp1_dma,
2836 };
2837
2838 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2839 .name = "mcbsp1",
2840 .class = &omap44xx_mcbsp_hwmod_class,
2841 .mpu_irqs = omap44xx_mcbsp1_irqs,
2842 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
2843 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
2844 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
2845 .main_clk = "mcbsp1_fck",
2846 .prcm = {
2847 .omap4 = {
2848 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2849 },
2850 },
2851 .slaves = omap44xx_mcbsp1_slaves,
2852 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2853 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2854 };
2855
2856 /* mcbsp2 */
2857 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2858 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2859 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2860 };
2861
2862 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2863 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2864 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2865 };
2866
2867 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2868 {
2869 .name = "mpu",
2870 .pa_start = 0x40124000,
2871 .pa_end = 0x401240ff,
2872 .flags = ADDR_TYPE_RT
2873 },
2874 };
2875
2876 /* l4_abe -> mcbsp2 */
2877 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2878 .master = &omap44xx_l4_abe_hwmod,
2879 .slave = &omap44xx_mcbsp2_hwmod,
2880 .clk = "ocp_abe_iclk",
2881 .addr = omap44xx_mcbsp2_addrs,
2882 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
2883 .user = OCP_USER_MPU,
2884 };
2885
2886 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2887 {
2888 .name = "dma",
2889 .pa_start = 0x49024000,
2890 .pa_end = 0x490240ff,
2891 .flags = ADDR_TYPE_RT
2892 },
2893 };
2894
2895 /* l4_abe -> mcbsp2 (dma) */
2896 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2897 .master = &omap44xx_l4_abe_hwmod,
2898 .slave = &omap44xx_mcbsp2_hwmod,
2899 .clk = "ocp_abe_iclk",
2900 .addr = omap44xx_mcbsp2_dma_addrs,
2901 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
2902 .user = OCP_USER_SDMA,
2903 };
2904
2905 /* mcbsp2 slave ports */
2906 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2907 &omap44xx_l4_abe__mcbsp2,
2908 &omap44xx_l4_abe__mcbsp2_dma,
2909 };
2910
2911 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2912 .name = "mcbsp2",
2913 .class = &omap44xx_mcbsp_hwmod_class,
2914 .mpu_irqs = omap44xx_mcbsp2_irqs,
2915 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
2916 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
2917 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
2918 .main_clk = "mcbsp2_fck",
2919 .prcm = {
2920 .omap4 = {
2921 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2922 },
2923 },
2924 .slaves = omap44xx_mcbsp2_slaves,
2925 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2926 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2927 };
2928
2929 /* mcbsp3 */
2930 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2931 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2932 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2933 };
2934
2935 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2936 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2937 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2938 };
2939
2940 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2941 {
2942 .name = "mpu",
2943 .pa_start = 0x40126000,
2944 .pa_end = 0x401260ff,
2945 .flags = ADDR_TYPE_RT
2946 },
2947 };
2948
2949 /* l4_abe -> mcbsp3 */
2950 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2951 .master = &omap44xx_l4_abe_hwmod,
2952 .slave = &omap44xx_mcbsp3_hwmod,
2953 .clk = "ocp_abe_iclk",
2954 .addr = omap44xx_mcbsp3_addrs,
2955 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
2956 .user = OCP_USER_MPU,
2957 };
2958
2959 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2960 {
2961 .name = "dma",
2962 .pa_start = 0x49026000,
2963 .pa_end = 0x490260ff,
2964 .flags = ADDR_TYPE_RT
2965 },
2966 };
2967
2968 /* l4_abe -> mcbsp3 (dma) */
2969 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2970 .master = &omap44xx_l4_abe_hwmod,
2971 .slave = &omap44xx_mcbsp3_hwmod,
2972 .clk = "ocp_abe_iclk",
2973 .addr = omap44xx_mcbsp3_dma_addrs,
2974 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
2975 .user = OCP_USER_SDMA,
2976 };
2977
2978 /* mcbsp3 slave ports */
2979 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
2980 &omap44xx_l4_abe__mcbsp3,
2981 &omap44xx_l4_abe__mcbsp3_dma,
2982 };
2983
2984 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2985 .name = "mcbsp3",
2986 .class = &omap44xx_mcbsp_hwmod_class,
2987 .mpu_irqs = omap44xx_mcbsp3_irqs,
2988 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
2989 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
2990 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
2991 .main_clk = "mcbsp3_fck",
2992 .prcm = {
2993 .omap4 = {
2994 .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2995 },
2996 },
2997 .slaves = omap44xx_mcbsp3_slaves,
2998 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
2999 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3000 };
3001
3002 /* mcbsp4 */
3003 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3004 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3005 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3006 };
3007
3008 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3009 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3010 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3011 };
3012
3013 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3014 {
3015 .pa_start = 0x48096000,
3016 .pa_end = 0x480960ff,
3017 .flags = ADDR_TYPE_RT
3018 },
3019 };
3020
3021 /* l4_per -> mcbsp4 */
3022 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3023 .master = &omap44xx_l4_per_hwmod,
3024 .slave = &omap44xx_mcbsp4_hwmod,
3025 .clk = "l4_div_ck",
3026 .addr = omap44xx_mcbsp4_addrs,
3027 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
3028 .user = OCP_USER_MPU | OCP_USER_SDMA,
3029 };
3030
3031 /* mcbsp4 slave ports */
3032 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3033 &omap44xx_l4_per__mcbsp4,
3034 };
3035
3036 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3037 .name = "mcbsp4",
3038 .class = &omap44xx_mcbsp_hwmod_class,
3039 .mpu_irqs = omap44xx_mcbsp4_irqs,
3040 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
3041 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
3042 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
3043 .main_clk = "mcbsp4_fck",
3044 .prcm = {
3045 .omap4 = {
3046 .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3047 },
3048 },
3049 .slaves = omap44xx_mcbsp4_slaves,
3050 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3051 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3052 };
3053
3054 /*
3055 * 'mcpdm' class
3056 * multi channel pdm controller (proprietary interface with phoenix power
3057 * ic)
3058 */
3059
3060 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3061 .rev_offs = 0x0000,
3062 .sysc_offs = 0x0010,
3063 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3064 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3065 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3066 SIDLE_SMART_WKUP),
3067 .sysc_fields = &omap_hwmod_sysc_type2,
3068 };
3069
3070 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3071 .name = "mcpdm",
3072 .sysc = &omap44xx_mcpdm_sysc,
3073 };
3074
3075 /* mcpdm */
3076 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3077 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3078 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3079 };
3080
3081 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3082 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3083 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3084 };
3085
3086 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3087 {
3088 .pa_start = 0x40132000,
3089 .pa_end = 0x4013207f,
3090 .flags = ADDR_TYPE_RT
3091 },
3092 };
3093
3094 /* l4_abe -> mcpdm */
3095 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3096 .master = &omap44xx_l4_abe_hwmod,
3097 .slave = &omap44xx_mcpdm_hwmod,
3098 .clk = "ocp_abe_iclk",
3099 .addr = omap44xx_mcpdm_addrs,
3100 .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_addrs),
3101 .user = OCP_USER_MPU,
3102 };
3103
3104 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3105 {
3106 .pa_start = 0x49032000,
3107 .pa_end = 0x4903207f,
3108 .flags = ADDR_TYPE_RT
3109 },
3110 };
3111
3112 /* l4_abe -> mcpdm (dma) */
3113 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3114 .master = &omap44xx_l4_abe_hwmod,
3115 .slave = &omap44xx_mcpdm_hwmod,
3116 .clk = "ocp_abe_iclk",
3117 .addr = omap44xx_mcpdm_dma_addrs,
3118 .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
3119 .user = OCP_USER_SDMA,
3120 };
3121
3122 /* mcpdm slave ports */
3123 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3124 &omap44xx_l4_abe__mcpdm,
3125 &omap44xx_l4_abe__mcpdm_dma,
3126 };
3127
3128 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3129 .name = "mcpdm",
3130 .class = &omap44xx_mcpdm_hwmod_class,
3131 .mpu_irqs = omap44xx_mcpdm_irqs,
3132 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs),
3133 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
3134 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
3135 .main_clk = "mcpdm_fck",
3136 .prcm = {
3137 .omap4 = {
3138 .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3139 },
3140 },
3141 .slaves = omap44xx_mcpdm_slaves,
3142 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3143 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3144 };
3145
3146 /*
3147 * 'mcspi' class
3148 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3149 * bus
3150 */
3151
3152 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3153 .rev_offs = 0x0000,
3154 .sysc_offs = 0x0010,
3155 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3156 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3157 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3158 SIDLE_SMART_WKUP),
3159 .sysc_fields = &omap_hwmod_sysc_type2,
3160 };
3161
3162 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3163 .name = "mcspi",
3164 .sysc = &omap44xx_mcspi_sysc,
3165 .rev = OMAP4_MCSPI_REV,
3166 };
3167
3168 /* mcspi1 */
3169 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3170 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3171 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3172 };
3173
3174 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3175 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3176 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3177 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3178 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3179 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3180 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3181 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3182 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3183 };
3184
3185 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3186 {
3187 .pa_start = 0x48098000,
3188 .pa_end = 0x480981ff,
3189 .flags = ADDR_TYPE_RT
3190 },
3191 };
3192
3193 /* l4_per -> mcspi1 */
3194 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3195 .master = &omap44xx_l4_per_hwmod,
3196 .slave = &omap44xx_mcspi1_hwmod,
3197 .clk = "l4_div_ck",
3198 .addr = omap44xx_mcspi1_addrs,
3199 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs),
3200 .user = OCP_USER_MPU | OCP_USER_SDMA,
3201 };
3202
3203 /* mcspi1 slave ports */
3204 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3205 &omap44xx_l4_per__mcspi1,
3206 };
3207
3208 /* mcspi1 dev_attr */
3209 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3210 .num_chipselect = 4,
3211 };
3212
3213 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3214 .name = "mcspi1",
3215 .class = &omap44xx_mcspi_hwmod_class,
3216 .mpu_irqs = omap44xx_mcspi1_irqs,
3217 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
3218 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
3219 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
3220 .main_clk = "mcspi1_fck",
3221 .prcm = {
3222 .omap4 = {
3223 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3224 },
3225 },
3226 .dev_attr = &mcspi1_dev_attr,
3227 .slaves = omap44xx_mcspi1_slaves,
3228 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3229 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3230 };
3231
3232 /* mcspi2 */
3233 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3234 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3235 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3236 };
3237
3238 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3239 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3240 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3241 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3242 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3243 };
3244
3245 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3246 {
3247 .pa_start = 0x4809a000,
3248 .pa_end = 0x4809a1ff,
3249 .flags = ADDR_TYPE_RT
3250 },
3251 };
3252
3253 /* l4_per -> mcspi2 */
3254 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3255 .master = &omap44xx_l4_per_hwmod,
3256 .slave = &omap44xx_mcspi2_hwmod,
3257 .clk = "l4_div_ck",
3258 .addr = omap44xx_mcspi2_addrs,
3259 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs),
3260 .user = OCP_USER_MPU | OCP_USER_SDMA,
3261 };
3262
3263 /* mcspi2 slave ports */
3264 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3265 &omap44xx_l4_per__mcspi2,
3266 };
3267
3268 /* mcspi2 dev_attr */
3269 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3270 .num_chipselect = 2,
3271 };
3272
3273 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3274 .name = "mcspi2",
3275 .class = &omap44xx_mcspi_hwmod_class,
3276 .mpu_irqs = omap44xx_mcspi2_irqs,
3277 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
3278 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
3279 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
3280 .main_clk = "mcspi2_fck",
3281 .prcm = {
3282 .omap4 = {
3283 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3284 },
3285 },
3286 .dev_attr = &mcspi2_dev_attr,
3287 .slaves = omap44xx_mcspi2_slaves,
3288 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3289 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3290 };
3291
3292 /* mcspi3 */
3293 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3294 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3295 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3296 };
3297
3298 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3299 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3300 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3301 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3302 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3303 };
3304
3305 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3306 {
3307 .pa_start = 0x480b8000,
3308 .pa_end = 0x480b81ff,
3309 .flags = ADDR_TYPE_RT
3310 },
3311 };
3312
3313 /* l4_per -> mcspi3 */
3314 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3315 .master = &omap44xx_l4_per_hwmod,
3316 .slave = &omap44xx_mcspi3_hwmod,
3317 .clk = "l4_div_ck",
3318 .addr = omap44xx_mcspi3_addrs,
3319 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs),
3320 .user = OCP_USER_MPU | OCP_USER_SDMA,
3321 };
3322
3323 /* mcspi3 slave ports */
3324 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3325 &omap44xx_l4_per__mcspi3,
3326 };
3327
3328 /* mcspi3 dev_attr */
3329 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3330 .num_chipselect = 2,
3331 };
3332
3333 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3334 .name = "mcspi3",
3335 .class = &omap44xx_mcspi_hwmod_class,
3336 .mpu_irqs = omap44xx_mcspi3_irqs,
3337 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
3338 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
3339 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
3340 .main_clk = "mcspi3_fck",
3341 .prcm = {
3342 .omap4 = {
3343 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3344 },
3345 },
3346 .dev_attr = &mcspi3_dev_attr,
3347 .slaves = omap44xx_mcspi3_slaves,
3348 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3349 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3350 };
3351
3352 /* mcspi4 */
3353 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3354 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3355 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3356 };
3357
3358 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3359 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3360 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3361 };
3362
3363 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3364 {
3365 .pa_start = 0x480ba000,
3366 .pa_end = 0x480ba1ff,
3367 .flags = ADDR_TYPE_RT
3368 },
3369 };
3370
3371 /* l4_per -> mcspi4 */
3372 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3373 .master = &omap44xx_l4_per_hwmod,
3374 .slave = &omap44xx_mcspi4_hwmod,
3375 .clk = "l4_div_ck",
3376 .addr = omap44xx_mcspi4_addrs,
3377 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs),
3378 .user = OCP_USER_MPU | OCP_USER_SDMA,
3379 };
3380
3381 /* mcspi4 slave ports */
3382 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3383 &omap44xx_l4_per__mcspi4,
3384 };
3385
3386 /* mcspi4 dev_attr */
3387 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3388 .num_chipselect = 1,
3389 };
3390
3391 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3392 .name = "mcspi4",
3393 .class = &omap44xx_mcspi_hwmod_class,
3394 .mpu_irqs = omap44xx_mcspi4_irqs,
3395 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
3396 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
3397 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
3398 .main_clk = "mcspi4_fck",
3399 .prcm = {
3400 .omap4 = {
3401 .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3402 },
3403 },
3404 .dev_attr = &mcspi4_dev_attr,
3405 .slaves = omap44xx_mcspi4_slaves,
3406 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3407 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3408 };
3409
3410 /*
3411 * 'mmc' class
3412 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3413 */
3414
3415 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3416 .rev_offs = 0x0000,
3417 .sysc_offs = 0x0010,
3418 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3419 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3420 SYSC_HAS_SOFTRESET),
3421 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3422 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3423 MSTANDBY_SMART),
3424 .sysc_fields = &omap_hwmod_sysc_type2,
3425 };
3426
3427 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3428 .name = "mmc",
3429 .sysc = &omap44xx_mmc_sysc,
3430 };
3431
3432 /* mmc1 */
3433
3434 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3435 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3436 };
3437
3438 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3439 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3440 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3441 };
3442
3443 /* mmc1 master ports */
3444 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3445 &omap44xx_mmc1__l3_main_1,
3446 };
3447
3448 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3449 {
3450 .pa_start = 0x4809c000,
3451 .pa_end = 0x4809c3ff,
3452 .flags = ADDR_TYPE_RT
3453 },
3454 };
3455
3456 /* l4_per -> mmc1 */
3457 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3458 .master = &omap44xx_l4_per_hwmod,
3459 .slave = &omap44xx_mmc1_hwmod,
3460 .clk = "l4_div_ck",
3461 .addr = omap44xx_mmc1_addrs,
3462 .addr_cnt = ARRAY_SIZE(omap44xx_mmc1_addrs),
3463 .user = OCP_USER_MPU | OCP_USER_SDMA,
3464 };
3465
3466 /* mmc1 slave ports */
3467 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3468 &omap44xx_l4_per__mmc1,
3469 };
3470
3471 /* mmc1 dev_attr */
3472 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3473 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3474 };
3475
3476 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3477 .name = "mmc1",
3478 .class = &omap44xx_mmc_hwmod_class,
3479 .mpu_irqs = omap44xx_mmc1_irqs,
3480 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs),
3481 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
3482 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
3483 .main_clk = "mmc1_fck",
3484 .prcm = {
3485 .omap4 = {
3486 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3487 },
3488 },
3489 .dev_attr = &mmc1_dev_attr,
3490 .slaves = omap44xx_mmc1_slaves,
3491 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3492 .masters = omap44xx_mmc1_masters,
3493 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3494 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3495 };
3496
3497 /* mmc2 */
3498 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3499 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3500 };
3501
3502 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3503 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3504 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3505 };
3506
3507 /* mmc2 master ports */
3508 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3509 &omap44xx_mmc2__l3_main_1,
3510 };
3511
3512 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3513 {
3514 .pa_start = 0x480b4000,
3515 .pa_end = 0x480b43ff,
3516 .flags = ADDR_TYPE_RT
3517 },
3518 };
3519
3520 /* l4_per -> mmc2 */
3521 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3522 .master = &omap44xx_l4_per_hwmod,
3523 .slave = &omap44xx_mmc2_hwmod,
3524 .clk = "l4_div_ck",
3525 .addr = omap44xx_mmc2_addrs,
3526 .addr_cnt = ARRAY_SIZE(omap44xx_mmc2_addrs),
3527 .user = OCP_USER_MPU | OCP_USER_SDMA,
3528 };
3529
3530 /* mmc2 slave ports */
3531 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3532 &omap44xx_l4_per__mmc2,
3533 };
3534
3535 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3536 .name = "mmc2",
3537 .class = &omap44xx_mmc_hwmod_class,
3538 .mpu_irqs = omap44xx_mmc2_irqs,
3539 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs),
3540 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
3541 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
3542 .main_clk = "mmc2_fck",
3543 .prcm = {
3544 .omap4 = {
3545 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3546 },
3547 },
3548 .slaves = omap44xx_mmc2_slaves,
3549 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3550 .masters = omap44xx_mmc2_masters,
3551 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3552 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3553 };
3554
3555 /* mmc3 */
3556 static struct omap_hwmod omap44xx_mmc3_hwmod;
3557 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3558 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3559 };
3560
3561 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3562 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3563 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3564 };
3565
3566 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3567 {
3568 .pa_start = 0x480ad000,
3569 .pa_end = 0x480ad3ff,
3570 .flags = ADDR_TYPE_RT
3571 },
3572 };
3573
3574 /* l4_per -> mmc3 */
3575 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3576 .master = &omap44xx_l4_per_hwmod,
3577 .slave = &omap44xx_mmc3_hwmod,
3578 .clk = "l4_div_ck",
3579 .addr = omap44xx_mmc3_addrs,
3580 .addr_cnt = ARRAY_SIZE(omap44xx_mmc3_addrs),
3581 .user = OCP_USER_MPU | OCP_USER_SDMA,
3582 };
3583
3584 /* mmc3 slave ports */
3585 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3586 &omap44xx_l4_per__mmc3,
3587 };
3588
3589 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3590 .name = "mmc3",
3591 .class = &omap44xx_mmc_hwmod_class,
3592 .mpu_irqs = omap44xx_mmc3_irqs,
3593 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs),
3594 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
3595 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
3596 .main_clk = "mmc3_fck",
3597 .prcm = {
3598 .omap4 = {
3599 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3600 },
3601 },
3602 .slaves = omap44xx_mmc3_slaves,
3603 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3604 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3605 };
3606
3607 /* mmc4 */
3608 static struct omap_hwmod omap44xx_mmc4_hwmod;
3609 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3610 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3611 };
3612
3613 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3614 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3615 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3616 };
3617
3618 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3619 {
3620 .pa_start = 0x480d1000,
3621 .pa_end = 0x480d13ff,
3622 .flags = ADDR_TYPE_RT
3623 },
3624 };
3625
3626 /* l4_per -> mmc4 */
3627 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3628 .master = &omap44xx_l4_per_hwmod,
3629 .slave = &omap44xx_mmc4_hwmod,
3630 .clk = "l4_div_ck",
3631 .addr = omap44xx_mmc4_addrs,
3632 .addr_cnt = ARRAY_SIZE(omap44xx_mmc4_addrs),
3633 .user = OCP_USER_MPU | OCP_USER_SDMA,
3634 };
3635
3636 /* mmc4 slave ports */
3637 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3638 &omap44xx_l4_per__mmc4,
3639 };
3640
3641 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3642 .name = "mmc4",
3643 .class = &omap44xx_mmc_hwmod_class,
3644 .mpu_irqs = omap44xx_mmc4_irqs,
3645 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs),
3646 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3647 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
3648 .main_clk = "mmc4_fck",
3649 .prcm = {
3650 .omap4 = {
3651 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3652 },
3653 },
3654 .slaves = omap44xx_mmc4_slaves,
3655 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3656 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3657 };
3658
3659 /* mmc5 */
3660 static struct omap_hwmod omap44xx_mmc5_hwmod;
3661 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3662 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3663 };
3664
3665 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3666 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3667 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3668 };
3669
3670 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3671 {
3672 .pa_start = 0x480d5000,
3673 .pa_end = 0x480d53ff,
3674 .flags = ADDR_TYPE_RT
3675 },
3676 };
3677
3678 /* l4_per -> mmc5 */
3679 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3680 .master = &omap44xx_l4_per_hwmod,
3681 .slave = &omap44xx_mmc5_hwmod,
3682 .clk = "l4_div_ck",
3683 .addr = omap44xx_mmc5_addrs,
3684 .addr_cnt = ARRAY_SIZE(omap44xx_mmc5_addrs),
3685 .user = OCP_USER_MPU | OCP_USER_SDMA,
3686 };
3687
3688 /* mmc5 slave ports */
3689 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3690 &omap44xx_l4_per__mmc5,
3691 };
3692
3693 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3694 .name = "mmc5",
3695 .class = &omap44xx_mmc_hwmod_class,
3696 .mpu_irqs = omap44xx_mmc5_irqs,
3697 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs),
3698 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
3699 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
3700 .main_clk = "mmc5_fck",
3701 .prcm = {
3702 .omap4 = {
3703 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3704 },
3705 },
3706 .slaves = omap44xx_mmc5_slaves,
3707 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3708 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3709 };
3710
3711 /*
3712 * 'mpu' class
3713 * mpu sub-system
3714 */
3715
3716 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3717 .name = "mpu",
3718 };
3719
3720 /* mpu */
3721 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3722 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3723 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3724 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3725 };
3726
3727 /* mpu master ports */
3728 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3729 &omap44xx_mpu__l3_main_1,
3730 &omap44xx_mpu__l4_abe,
3731 &omap44xx_mpu__dmm,
3732 };
3733
3734 static struct omap_hwmod omap44xx_mpu_hwmod = {
3735 .name = "mpu",
3736 .class = &omap44xx_mpu_hwmod_class,
3737 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
3738 .mpu_irqs = omap44xx_mpu_irqs,
3739 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
3740 .main_clk = "dpll_mpu_m2_ck",
3741 .prcm = {
3742 .omap4 = {
3743 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
3744 },
3745 },
3746 .masters = omap44xx_mpu_masters,
3747 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
3748 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3749 };
3750
3751 /*
3752 * 'smartreflex' class
3753 * smartreflex module (monitor silicon performance and outputs a measure of
3754 * performance error)
3755 */
3756
3757 /* The IP is not compliant to type1 / type2 scheme */
3758 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3759 .sidle_shift = 24,
3760 .enwkup_shift = 26,
3761 };
3762
3763 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3764 .sysc_offs = 0x0038,
3765 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3766 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3767 SIDLE_SMART_WKUP),
3768 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
3769 };
3770
3771 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3772 .name = "smartreflex",
3773 .sysc = &omap44xx_smartreflex_sysc,
3774 .rev = 2,
3775 };
3776
3777 /* smartreflex_core */
3778 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3779 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3780 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3781 };
3782
3783 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3784 {
3785 .pa_start = 0x4a0dd000,
3786 .pa_end = 0x4a0dd03f,
3787 .flags = ADDR_TYPE_RT
3788 },
3789 };
3790
3791 /* l4_cfg -> smartreflex_core */
3792 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3793 .master = &omap44xx_l4_cfg_hwmod,
3794 .slave = &omap44xx_smartreflex_core_hwmod,
3795 .clk = "l4_div_ck",
3796 .addr = omap44xx_smartreflex_core_addrs,
3797 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
3798 .user = OCP_USER_MPU | OCP_USER_SDMA,
3799 };
3800
3801 /* smartreflex_core slave ports */
3802 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3803 &omap44xx_l4_cfg__smartreflex_core,
3804 };
3805
3806 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3807 .name = "smartreflex_core",
3808 .class = &omap44xx_smartreflex_hwmod_class,
3809 .mpu_irqs = omap44xx_smartreflex_core_irqs,
3810 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
3811 .main_clk = "smartreflex_core_fck",
3812 .vdd_name = "core",
3813 .prcm = {
3814 .omap4 = {
3815 .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3816 },
3817 },
3818 .slaves = omap44xx_smartreflex_core_slaves,
3819 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3820 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3821 };
3822
3823 /* smartreflex_iva */
3824 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3825 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3826 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3827 };
3828
3829 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3830 {
3831 .pa_start = 0x4a0db000,
3832 .pa_end = 0x4a0db03f,
3833 .flags = ADDR_TYPE_RT
3834 },
3835 };
3836
3837 /* l4_cfg -> smartreflex_iva */
3838 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3839 .master = &omap44xx_l4_cfg_hwmod,
3840 .slave = &omap44xx_smartreflex_iva_hwmod,
3841 .clk = "l4_div_ck",
3842 .addr = omap44xx_smartreflex_iva_addrs,
3843 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
3844 .user = OCP_USER_MPU | OCP_USER_SDMA,
3845 };
3846
3847 /* smartreflex_iva slave ports */
3848 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3849 &omap44xx_l4_cfg__smartreflex_iva,
3850 };
3851
3852 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3853 .name = "smartreflex_iva",
3854 .class = &omap44xx_smartreflex_hwmod_class,
3855 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
3856 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
3857 .main_clk = "smartreflex_iva_fck",
3858 .vdd_name = "iva",
3859 .prcm = {
3860 .omap4 = {
3861 .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3862 },
3863 },
3864 .slaves = omap44xx_smartreflex_iva_slaves,
3865 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3866 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3867 };
3868
3869 /* smartreflex_mpu */
3870 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3871 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3872 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3873 };
3874
3875 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3876 {
3877 .pa_start = 0x4a0d9000,
3878 .pa_end = 0x4a0d903f,
3879 .flags = ADDR_TYPE_RT
3880 },
3881 };
3882
3883 /* l4_cfg -> smartreflex_mpu */
3884 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3885 .master = &omap44xx_l4_cfg_hwmod,
3886 .slave = &omap44xx_smartreflex_mpu_hwmod,
3887 .clk = "l4_div_ck",
3888 .addr = omap44xx_smartreflex_mpu_addrs,
3889 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
3890 .user = OCP_USER_MPU | OCP_USER_SDMA,
3891 };
3892
3893 /* smartreflex_mpu slave ports */
3894 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3895 &omap44xx_l4_cfg__smartreflex_mpu,
3896 };
3897
3898 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3899 .name = "smartreflex_mpu",
3900 .class = &omap44xx_smartreflex_hwmod_class,
3901 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
3902 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
3903 .main_clk = "smartreflex_mpu_fck",
3904 .vdd_name = "mpu",
3905 .prcm = {
3906 .omap4 = {
3907 .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
3908 },
3909 },
3910 .slaves = omap44xx_smartreflex_mpu_slaves,
3911 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
3912 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3913 };
3914
3915 /*
3916 * 'spinlock' class
3917 * spinlock provides hardware assistance for synchronizing the processes
3918 * running on multiple processors
3919 */
3920
3921 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3922 .rev_offs = 0x0000,
3923 .sysc_offs = 0x0010,
3924 .syss_offs = 0x0014,
3925 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3926 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3927 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3928 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3929 SIDLE_SMART_WKUP),
3930 .sysc_fields = &omap_hwmod_sysc_type1,
3931 };
3932
3933 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3934 .name = "spinlock",
3935 .sysc = &omap44xx_spinlock_sysc,
3936 };
3937
3938 /* spinlock */
3939 static struct omap_hwmod omap44xx_spinlock_hwmod;
3940 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3941 {
3942 .pa_start = 0x4a0f6000,
3943 .pa_end = 0x4a0f6fff,
3944 .flags = ADDR_TYPE_RT
3945 },
3946 };
3947
3948 /* l4_cfg -> spinlock */
3949 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3950 .master = &omap44xx_l4_cfg_hwmod,
3951 .slave = &omap44xx_spinlock_hwmod,
3952 .clk = "l4_div_ck",
3953 .addr = omap44xx_spinlock_addrs,
3954 .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs),
3955 .user = OCP_USER_MPU | OCP_USER_SDMA,
3956 };
3957
3958 /* spinlock slave ports */
3959 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
3960 &omap44xx_l4_cfg__spinlock,
3961 };
3962
3963 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3964 .name = "spinlock",
3965 .class = &omap44xx_spinlock_hwmod_class,
3966 .prcm = {
3967 .omap4 = {
3968 .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
3969 },
3970 },
3971 .slaves = omap44xx_spinlock_slaves,
3972 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
3973 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3974 };
3975
3976 /*
3977 * 'timer' class
3978 * general purpose timer module with accurate 1ms tick
3979 * This class contains several variants: ['timer_1ms', 'timer']
3980 */
3981
3982 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3983 .rev_offs = 0x0000,
3984 .sysc_offs = 0x0010,
3985 .syss_offs = 0x0014,
3986 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3987 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3988 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3989 SYSS_HAS_RESET_STATUS),
3990 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3991 .sysc_fields = &omap_hwmod_sysc_type1,
3992 };
3993
3994 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3995 .name = "timer",
3996 .sysc = &omap44xx_timer_1ms_sysc,
3997 };
3998
3999 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4000 .rev_offs = 0x0000,
4001 .sysc_offs = 0x0010,
4002 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4003 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4004 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4005 SIDLE_SMART_WKUP),
4006 .sysc_fields = &omap_hwmod_sysc_type2,
4007 };
4008
4009 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4010 .name = "timer",
4011 .sysc = &omap44xx_timer_sysc,
4012 };
4013
4014 /* timer1 */
4015 static struct omap_hwmod omap44xx_timer1_hwmod;
4016 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4017 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4018 };
4019
4020 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4021 {
4022 .pa_start = 0x4a318000,
4023 .pa_end = 0x4a31807f,
4024 .flags = ADDR_TYPE_RT
4025 },
4026 };
4027
4028 /* l4_wkup -> timer1 */
4029 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4030 .master = &omap44xx_l4_wkup_hwmod,
4031 .slave = &omap44xx_timer1_hwmod,
4032 .clk = "l4_wkup_clk_mux_ck",
4033 .addr = omap44xx_timer1_addrs,
4034 .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
4035 .user = OCP_USER_MPU | OCP_USER_SDMA,
4036 };
4037
4038 /* timer1 slave ports */
4039 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4040 &omap44xx_l4_wkup__timer1,
4041 };
4042
4043 static struct omap_hwmod omap44xx_timer1_hwmod = {
4044 .name = "timer1",
4045 .class = &omap44xx_timer_1ms_hwmod_class,
4046 .mpu_irqs = omap44xx_timer1_irqs,
4047 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
4048 .main_clk = "timer1_fck",
4049 .prcm = {
4050 .omap4 = {
4051 .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
4052 },
4053 },
4054 .slaves = omap44xx_timer1_slaves,
4055 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
4056 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4057 };
4058
4059 /* timer2 */
4060 static struct omap_hwmod omap44xx_timer2_hwmod;
4061 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4062 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4063 };
4064
4065 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4066 {
4067 .pa_start = 0x48032000,
4068 .pa_end = 0x4803207f,
4069 .flags = ADDR_TYPE_RT
4070 },
4071 };
4072
4073 /* l4_per -> timer2 */
4074 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4075 .master = &omap44xx_l4_per_hwmod,
4076 .slave = &omap44xx_timer2_hwmod,
4077 .clk = "l4_div_ck",
4078 .addr = omap44xx_timer2_addrs,
4079 .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
4080 .user = OCP_USER_MPU | OCP_USER_SDMA,
4081 };
4082
4083 /* timer2 slave ports */
4084 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4085 &omap44xx_l4_per__timer2,
4086 };
4087
4088 static struct omap_hwmod omap44xx_timer2_hwmod = {
4089 .name = "timer2",
4090 .class = &omap44xx_timer_1ms_hwmod_class,
4091 .mpu_irqs = omap44xx_timer2_irqs,
4092 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
4093 .main_clk = "timer2_fck",
4094 .prcm = {
4095 .omap4 = {
4096 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4097 },
4098 },
4099 .slaves = omap44xx_timer2_slaves,
4100 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4101 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4102 };
4103
4104 /* timer3 */
4105 static struct omap_hwmod omap44xx_timer3_hwmod;
4106 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4107 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4108 };
4109
4110 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4111 {
4112 .pa_start = 0x48034000,
4113 .pa_end = 0x4803407f,
4114 .flags = ADDR_TYPE_RT
4115 },
4116 };
4117
4118 /* l4_per -> timer3 */
4119 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4120 .master = &omap44xx_l4_per_hwmod,
4121 .slave = &omap44xx_timer3_hwmod,
4122 .clk = "l4_div_ck",
4123 .addr = omap44xx_timer3_addrs,
4124 .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs),
4125 .user = OCP_USER_MPU | OCP_USER_SDMA,
4126 };
4127
4128 /* timer3 slave ports */
4129 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4130 &omap44xx_l4_per__timer3,
4131 };
4132
4133 static struct omap_hwmod omap44xx_timer3_hwmod = {
4134 .name = "timer3",
4135 .class = &omap44xx_timer_hwmod_class,
4136 .mpu_irqs = omap44xx_timer3_irqs,
4137 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
4138 .main_clk = "timer3_fck",
4139 .prcm = {
4140 .omap4 = {
4141 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4142 },
4143 },
4144 .slaves = omap44xx_timer3_slaves,
4145 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4146 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4147 };
4148
4149 /* timer4 */
4150 static struct omap_hwmod omap44xx_timer4_hwmod;
4151 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4152 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4153 };
4154
4155 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4156 {
4157 .pa_start = 0x48036000,
4158 .pa_end = 0x4803607f,
4159 .flags = ADDR_TYPE_RT
4160 },
4161 };
4162
4163 /* l4_per -> timer4 */
4164 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4165 .master = &omap44xx_l4_per_hwmod,
4166 .slave = &omap44xx_timer4_hwmod,
4167 .clk = "l4_div_ck",
4168 .addr = omap44xx_timer4_addrs,
4169 .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs),
4170 .user = OCP_USER_MPU | OCP_USER_SDMA,
4171 };
4172
4173 /* timer4 slave ports */
4174 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4175 &omap44xx_l4_per__timer4,
4176 };
4177
4178 static struct omap_hwmod omap44xx_timer4_hwmod = {
4179 .name = "timer4",
4180 .class = &omap44xx_timer_hwmod_class,
4181 .mpu_irqs = omap44xx_timer4_irqs,
4182 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
4183 .main_clk = "timer4_fck",
4184 .prcm = {
4185 .omap4 = {
4186 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4187 },
4188 },
4189 .slaves = omap44xx_timer4_slaves,
4190 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4191 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4192 };
4193
4194 /* timer5 */
4195 static struct omap_hwmod omap44xx_timer5_hwmod;
4196 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4197 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4198 };
4199
4200 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4201 {
4202 .pa_start = 0x40138000,
4203 .pa_end = 0x4013807f,
4204 .flags = ADDR_TYPE_RT
4205 },
4206 };
4207
4208 /* l4_abe -> timer5 */
4209 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4210 .master = &omap44xx_l4_abe_hwmod,
4211 .slave = &omap44xx_timer5_hwmod,
4212 .clk = "ocp_abe_iclk",
4213 .addr = omap44xx_timer5_addrs,
4214 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs),
4215 .user = OCP_USER_MPU,
4216 };
4217
4218 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4219 {
4220 .pa_start = 0x49038000,
4221 .pa_end = 0x4903807f,
4222 .flags = ADDR_TYPE_RT
4223 },
4224 };
4225
4226 /* l4_abe -> timer5 (dma) */
4227 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4228 .master = &omap44xx_l4_abe_hwmod,
4229 .slave = &omap44xx_timer5_hwmod,
4230 .clk = "ocp_abe_iclk",
4231 .addr = omap44xx_timer5_dma_addrs,
4232 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
4233 .user = OCP_USER_SDMA,
4234 };
4235
4236 /* timer5 slave ports */
4237 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4238 &omap44xx_l4_abe__timer5,
4239 &omap44xx_l4_abe__timer5_dma,
4240 };
4241
4242 static struct omap_hwmod omap44xx_timer5_hwmod = {
4243 .name = "timer5",
4244 .class = &omap44xx_timer_hwmod_class,
4245 .mpu_irqs = omap44xx_timer5_irqs,
4246 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
4247 .main_clk = "timer5_fck",
4248 .prcm = {
4249 .omap4 = {
4250 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4251 },
4252 },
4253 .slaves = omap44xx_timer5_slaves,
4254 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4255 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4256 };
4257
4258 /* timer6 */
4259 static struct omap_hwmod omap44xx_timer6_hwmod;
4260 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4261 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4262 };
4263
4264 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4265 {
4266 .pa_start = 0x4013a000,
4267 .pa_end = 0x4013a07f,
4268 .flags = ADDR_TYPE_RT
4269 },
4270 };
4271
4272 /* l4_abe -> timer6 */
4273 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4274 .master = &omap44xx_l4_abe_hwmod,
4275 .slave = &omap44xx_timer6_hwmod,
4276 .clk = "ocp_abe_iclk",
4277 .addr = omap44xx_timer6_addrs,
4278 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs),
4279 .user = OCP_USER_MPU,
4280 };
4281
4282 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4283 {
4284 .pa_start = 0x4903a000,
4285 .pa_end = 0x4903a07f,
4286 .flags = ADDR_TYPE_RT
4287 },
4288 };
4289
4290 /* l4_abe -> timer6 (dma) */
4291 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4292 .master = &omap44xx_l4_abe_hwmod,
4293 .slave = &omap44xx_timer6_hwmod,
4294 .clk = "ocp_abe_iclk",
4295 .addr = omap44xx_timer6_dma_addrs,
4296 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
4297 .user = OCP_USER_SDMA,
4298 };
4299
4300 /* timer6 slave ports */
4301 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4302 &omap44xx_l4_abe__timer6,
4303 &omap44xx_l4_abe__timer6_dma,
4304 };
4305
4306 static struct omap_hwmod omap44xx_timer6_hwmod = {
4307 .name = "timer6",
4308 .class = &omap44xx_timer_hwmod_class,
4309 .mpu_irqs = omap44xx_timer6_irqs,
4310 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs),
4311 .main_clk = "timer6_fck",
4312 .prcm = {
4313 .omap4 = {
4314 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4315 },
4316 },
4317 .slaves = omap44xx_timer6_slaves,
4318 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4319 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4320 };
4321
4322 /* timer7 */
4323 static struct omap_hwmod omap44xx_timer7_hwmod;
4324 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4325 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4326 };
4327
4328 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4329 {
4330 .pa_start = 0x4013c000,
4331 .pa_end = 0x4013c07f,
4332 .flags = ADDR_TYPE_RT
4333 },
4334 };
4335
4336 /* l4_abe -> timer7 */
4337 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4338 .master = &omap44xx_l4_abe_hwmod,
4339 .slave = &omap44xx_timer7_hwmod,
4340 .clk = "ocp_abe_iclk",
4341 .addr = omap44xx_timer7_addrs,
4342 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs),
4343 .user = OCP_USER_MPU,
4344 };
4345
4346 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4347 {
4348 .pa_start = 0x4903c000,
4349 .pa_end = 0x4903c07f,
4350 .flags = ADDR_TYPE_RT
4351 },
4352 };
4353
4354 /* l4_abe -> timer7 (dma) */
4355 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4356 .master = &omap44xx_l4_abe_hwmod,
4357 .slave = &omap44xx_timer7_hwmod,
4358 .clk = "ocp_abe_iclk",
4359 .addr = omap44xx_timer7_dma_addrs,
4360 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
4361 .user = OCP_USER_SDMA,
4362 };
4363
4364 /* timer7 slave ports */
4365 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4366 &omap44xx_l4_abe__timer7,
4367 &omap44xx_l4_abe__timer7_dma,
4368 };
4369
4370 static struct omap_hwmod omap44xx_timer7_hwmod = {
4371 .name = "timer7",
4372 .class = &omap44xx_timer_hwmod_class,
4373 .mpu_irqs = omap44xx_timer7_irqs,
4374 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
4375 .main_clk = "timer7_fck",
4376 .prcm = {
4377 .omap4 = {
4378 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4379 },
4380 },
4381 .slaves = omap44xx_timer7_slaves,
4382 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4383 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4384 };
4385
4386 /* timer8 */
4387 static struct omap_hwmod omap44xx_timer8_hwmod;
4388 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4389 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4390 };
4391
4392 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4393 {
4394 .pa_start = 0x4013e000,
4395 .pa_end = 0x4013e07f,
4396 .flags = ADDR_TYPE_RT
4397 },
4398 };
4399
4400 /* l4_abe -> timer8 */
4401 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4402 .master = &omap44xx_l4_abe_hwmod,
4403 .slave = &omap44xx_timer8_hwmod,
4404 .clk = "ocp_abe_iclk",
4405 .addr = omap44xx_timer8_addrs,
4406 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs),
4407 .user = OCP_USER_MPU,
4408 };
4409
4410 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4411 {
4412 .pa_start = 0x4903e000,
4413 .pa_end = 0x4903e07f,
4414 .flags = ADDR_TYPE_RT
4415 },
4416 };
4417
4418 /* l4_abe -> timer8 (dma) */
4419 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4420 .master = &omap44xx_l4_abe_hwmod,
4421 .slave = &omap44xx_timer8_hwmod,
4422 .clk = "ocp_abe_iclk",
4423 .addr = omap44xx_timer8_dma_addrs,
4424 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
4425 .user = OCP_USER_SDMA,
4426 };
4427
4428 /* timer8 slave ports */
4429 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4430 &omap44xx_l4_abe__timer8,
4431 &omap44xx_l4_abe__timer8_dma,
4432 };
4433
4434 static struct omap_hwmod omap44xx_timer8_hwmod = {
4435 .name = "timer8",
4436 .class = &omap44xx_timer_hwmod_class,
4437 .mpu_irqs = omap44xx_timer8_irqs,
4438 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
4439 .main_clk = "timer8_fck",
4440 .prcm = {
4441 .omap4 = {
4442 .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4443 },
4444 },
4445 .slaves = omap44xx_timer8_slaves,
4446 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4447 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4448 };
4449
4450 /* timer9 */
4451 static struct omap_hwmod omap44xx_timer9_hwmod;
4452 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4453 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4454 };
4455
4456 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4457 {
4458 .pa_start = 0x4803e000,
4459 .pa_end = 0x4803e07f,
4460 .flags = ADDR_TYPE_RT
4461 },
4462 };
4463
4464 /* l4_per -> timer9 */
4465 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4466 .master = &omap44xx_l4_per_hwmod,
4467 .slave = &omap44xx_timer9_hwmod,
4468 .clk = "l4_div_ck",
4469 .addr = omap44xx_timer9_addrs,
4470 .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs),
4471 .user = OCP_USER_MPU | OCP_USER_SDMA,
4472 };
4473
4474 /* timer9 slave ports */
4475 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4476 &omap44xx_l4_per__timer9,
4477 };
4478
4479 static struct omap_hwmod omap44xx_timer9_hwmod = {
4480 .name = "timer9",
4481 .class = &omap44xx_timer_hwmod_class,
4482 .mpu_irqs = omap44xx_timer9_irqs,
4483 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
4484 .main_clk = "timer9_fck",
4485 .prcm = {
4486 .omap4 = {
4487 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4488 },
4489 },
4490 .slaves = omap44xx_timer9_slaves,
4491 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4492 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4493 };
4494
4495 /* timer10 */
4496 static struct omap_hwmod omap44xx_timer10_hwmod;
4497 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4498 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4499 };
4500
4501 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4502 {
4503 .pa_start = 0x48086000,
4504 .pa_end = 0x4808607f,
4505 .flags = ADDR_TYPE_RT
4506 },
4507 };
4508
4509 /* l4_per -> timer10 */
4510 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4511 .master = &omap44xx_l4_per_hwmod,
4512 .slave = &omap44xx_timer10_hwmod,
4513 .clk = "l4_div_ck",
4514 .addr = omap44xx_timer10_addrs,
4515 .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs),
4516 .user = OCP_USER_MPU | OCP_USER_SDMA,
4517 };
4518
4519 /* timer10 slave ports */
4520 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4521 &omap44xx_l4_per__timer10,
4522 };
4523
4524 static struct omap_hwmod omap44xx_timer10_hwmod = {
4525 .name = "timer10",
4526 .class = &omap44xx_timer_1ms_hwmod_class,
4527 .mpu_irqs = omap44xx_timer10_irqs,
4528 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
4529 .main_clk = "timer10_fck",
4530 .prcm = {
4531 .omap4 = {
4532 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4533 },
4534 },
4535 .slaves = omap44xx_timer10_slaves,
4536 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4537 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4538 };
4539
4540 /* timer11 */
4541 static struct omap_hwmod omap44xx_timer11_hwmod;
4542 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4543 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4544 };
4545
4546 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4547 {
4548 .pa_start = 0x48088000,
4549 .pa_end = 0x4808807f,
4550 .flags = ADDR_TYPE_RT
4551 },
4552 };
4553
4554 /* l4_per -> timer11 */
4555 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4556 .master = &omap44xx_l4_per_hwmod,
4557 .slave = &omap44xx_timer11_hwmod,
4558 .clk = "l4_div_ck",
4559 .addr = omap44xx_timer11_addrs,
4560 .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs),
4561 .user = OCP_USER_MPU | OCP_USER_SDMA,
4562 };
4563
4564 /* timer11 slave ports */
4565 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4566 &omap44xx_l4_per__timer11,
4567 };
4568
4569 static struct omap_hwmod omap44xx_timer11_hwmod = {
4570 .name = "timer11",
4571 .class = &omap44xx_timer_hwmod_class,
4572 .mpu_irqs = omap44xx_timer11_irqs,
4573 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
4574 .main_clk = "timer11_fck",
4575 .prcm = {
4576 .omap4 = {
4577 .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4578 },
4579 },
4580 .slaves = omap44xx_timer11_slaves,
4581 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4582 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4583 };
4584
4585 /*
4586 * 'uart' class
4587 * universal asynchronous receiver/transmitter (uart)
4588 */
4589
4590 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4591 .rev_offs = 0x0050,
4592 .sysc_offs = 0x0054,
4593 .syss_offs = 0x0058,
4594 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4595 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4596 SYSS_HAS_RESET_STATUS),
4597 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4598 SIDLE_SMART_WKUP),
4599 .sysc_fields = &omap_hwmod_sysc_type1,
4600 };
4601
4602 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4603 .name = "uart",
4604 .sysc = &omap44xx_uart_sysc,
4605 };
4606
4607 /* uart1 */
4608 static struct omap_hwmod omap44xx_uart1_hwmod;
4609 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4610 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4611 };
4612
4613 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4614 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4615 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4616 };
4617
4618 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4619 {
4620 .pa_start = 0x4806a000,
4621 .pa_end = 0x4806a0ff,
4622 .flags = ADDR_TYPE_RT
4623 },
4624 };
4625
4626 /* l4_per -> uart1 */
4627 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4628 .master = &omap44xx_l4_per_hwmod,
4629 .slave = &omap44xx_uart1_hwmod,
4630 .clk = "l4_div_ck",
4631 .addr = omap44xx_uart1_addrs,
4632 .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
4633 .user = OCP_USER_MPU | OCP_USER_SDMA,
4634 };
4635
4636 /* uart1 slave ports */
4637 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4638 &omap44xx_l4_per__uart1,
4639 };
4640
4641 static struct omap_hwmod omap44xx_uart1_hwmod = {
4642 .name = "uart1",
4643 .class = &omap44xx_uart_hwmod_class,
4644 .mpu_irqs = omap44xx_uart1_irqs,
4645 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
4646 .sdma_reqs = omap44xx_uart1_sdma_reqs,
4647 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
4648 .main_clk = "uart1_fck",
4649 .prcm = {
4650 .omap4 = {
4651 .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
4652 },
4653 },
4654 .slaves = omap44xx_uart1_slaves,
4655 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
4656 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4657 };
4658
4659 /* uart2 */
4660 static struct omap_hwmod omap44xx_uart2_hwmod;
4661 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4662 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4663 };
4664
4665 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4666 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4667 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4668 };
4669
4670 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4671 {
4672 .pa_start = 0x4806c000,
4673 .pa_end = 0x4806c0ff,
4674 .flags = ADDR_TYPE_RT
4675 },
4676 };
4677
4678 /* l4_per -> uart2 */
4679 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4680 .master = &omap44xx_l4_per_hwmod,
4681 .slave = &omap44xx_uart2_hwmod,
4682 .clk = "l4_div_ck",
4683 .addr = omap44xx_uart2_addrs,
4684 .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
4685 .user = OCP_USER_MPU | OCP_USER_SDMA,
4686 };
4687
4688 /* uart2 slave ports */
4689 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4690 &omap44xx_l4_per__uart2,
4691 };
4692
4693 static struct omap_hwmod omap44xx_uart2_hwmod = {
4694 .name = "uart2",
4695 .class = &omap44xx_uart_hwmod_class,
4696 .mpu_irqs = omap44xx_uart2_irqs,
4697 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
4698 .sdma_reqs = omap44xx_uart2_sdma_reqs,
4699 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
4700 .main_clk = "uart2_fck",
4701 .prcm = {
4702 .omap4 = {
4703 .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
4704 },
4705 },
4706 .slaves = omap44xx_uart2_slaves,
4707 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
4708 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4709 };
4710
4711 /* uart3 */
4712 static struct omap_hwmod omap44xx_uart3_hwmod;
4713 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4714 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4715 };
4716
4717 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4718 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4719 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4720 };
4721
4722 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4723 {
4724 .pa_start = 0x48020000,
4725 .pa_end = 0x480200ff,
4726 .flags = ADDR_TYPE_RT
4727 },
4728 };
4729
4730 /* l4_per -> uart3 */
4731 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4732 .master = &omap44xx_l4_per_hwmod,
4733 .slave = &omap44xx_uart3_hwmod,
4734 .clk = "l4_div_ck",
4735 .addr = omap44xx_uart3_addrs,
4736 .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
4737 .user = OCP_USER_MPU | OCP_USER_SDMA,
4738 };
4739
4740 /* uart3 slave ports */
4741 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4742 &omap44xx_l4_per__uart3,
4743 };
4744
4745 static struct omap_hwmod omap44xx_uart3_hwmod = {
4746 .name = "uart3",
4747 .class = &omap44xx_uart_hwmod_class,
4748 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
4749 .mpu_irqs = omap44xx_uart3_irqs,
4750 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
4751 .sdma_reqs = omap44xx_uart3_sdma_reqs,
4752 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
4753 .main_clk = "uart3_fck",
4754 .prcm = {
4755 .omap4 = {
4756 .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
4757 },
4758 },
4759 .slaves = omap44xx_uart3_slaves,
4760 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
4761 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4762 };
4763
4764 /* uart4 */
4765 static struct omap_hwmod omap44xx_uart4_hwmod;
4766 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4767 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4768 };
4769
4770 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4771 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4772 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4773 };
4774
4775 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4776 {
4777 .pa_start = 0x4806e000,
4778 .pa_end = 0x4806e0ff,
4779 .flags = ADDR_TYPE_RT
4780 },
4781 };
4782
4783 /* l4_per -> uart4 */
4784 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4785 .master = &omap44xx_l4_per_hwmod,
4786 .slave = &omap44xx_uart4_hwmod,
4787 .clk = "l4_div_ck",
4788 .addr = omap44xx_uart4_addrs,
4789 .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
4790 .user = OCP_USER_MPU | OCP_USER_SDMA,
4791 };
4792
4793 /* uart4 slave ports */
4794 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4795 &omap44xx_l4_per__uart4,
4796 };
4797
4798 static struct omap_hwmod omap44xx_uart4_hwmod = {
4799 .name = "uart4",
4800 .class = &omap44xx_uart_hwmod_class,
4801 .mpu_irqs = omap44xx_uart4_irqs,
4802 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
4803 .sdma_reqs = omap44xx_uart4_sdma_reqs,
4804 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
4805 .main_clk = "uart4_fck",
4806 .prcm = {
4807 .omap4 = {
4808 .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
4809 },
4810 },
4811 .slaves = omap44xx_uart4_slaves,
4812 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
4813 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4814 };
4815
4816 /*
4817 * 'usb_otg_hs' class
4818 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4819 */
4820
4821 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4822 .rev_offs = 0x0400,
4823 .sysc_offs = 0x0404,
4824 .syss_offs = 0x0408,
4825 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4826 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4827 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4828 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4829 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4830 MSTANDBY_SMART),
4831 .sysc_fields = &omap_hwmod_sysc_type1,
4832 };
4833
4834 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4835 .name = "usb_otg_hs",
4836 .sysc = &omap44xx_usb_otg_hs_sysc,
4837 };
4838
4839 /* usb_otg_hs */
4840 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4841 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4842 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4843 };
4844
4845 /* usb_otg_hs master ports */
4846 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4847 &omap44xx_usb_otg_hs__l3_main_2,
4848 };
4849
4850 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4851 {
4852 .pa_start = 0x4a0ab000,
4853 .pa_end = 0x4a0ab003,
4854 .flags = ADDR_TYPE_RT
4855 },
4856 };
4857
4858 /* l4_cfg -> usb_otg_hs */
4859 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4860 .master = &omap44xx_l4_cfg_hwmod,
4861 .slave = &omap44xx_usb_otg_hs_hwmod,
4862 .clk = "l4_div_ck",
4863 .addr = omap44xx_usb_otg_hs_addrs,
4864 .addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
4865 .user = OCP_USER_MPU | OCP_USER_SDMA,
4866 };
4867
4868 /* usb_otg_hs slave ports */
4869 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4870 &omap44xx_l4_cfg__usb_otg_hs,
4871 };
4872
4873 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4874 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4875 };
4876
4877 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4878 .name = "usb_otg_hs",
4879 .class = &omap44xx_usb_otg_hs_hwmod_class,
4880 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4881 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
4882 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
4883 .main_clk = "usb_otg_hs_ick",
4884 .prcm = {
4885 .omap4 = {
4886 .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
4887 },
4888 },
4889 .opt_clks = usb_otg_hs_opt_clks,
4890 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
4891 .slaves = omap44xx_usb_otg_hs_slaves,
4892 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4893 .masters = omap44xx_usb_otg_hs_masters,
4894 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
4895 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4896 };
4897
4898 /*
4899 * 'wd_timer' class
4900 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4901 * overflow condition
4902 */
4903
4904 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4905 .rev_offs = 0x0000,
4906 .sysc_offs = 0x0010,
4907 .syss_offs = 0x0014,
4908 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
4909 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4910 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4911 SIDLE_SMART_WKUP),
4912 .sysc_fields = &omap_hwmod_sysc_type1,
4913 };
4914
4915 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4916 .name = "wd_timer",
4917 .sysc = &omap44xx_wd_timer_sysc,
4918 .pre_shutdown = &omap2_wd_timer_disable,
4919 };
4920
4921 /* wd_timer2 */
4922 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4923 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4924 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4925 };
4926
4927 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
4928 {
4929 .pa_start = 0x4a314000,
4930 .pa_end = 0x4a31407f,
4931 .flags = ADDR_TYPE_RT
4932 },
4933 };
4934
4935 /* l4_wkup -> wd_timer2 */
4936 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4937 .master = &omap44xx_l4_wkup_hwmod,
4938 .slave = &omap44xx_wd_timer2_hwmod,
4939 .clk = "l4_wkup_clk_mux_ck",
4940 .addr = omap44xx_wd_timer2_addrs,
4941 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
4942 .user = OCP_USER_MPU | OCP_USER_SDMA,
4943 };
4944
4945 /* wd_timer2 slave ports */
4946 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
4947 &omap44xx_l4_wkup__wd_timer2,
4948 };
4949
4950 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4951 .name = "wd_timer2",
4952 .class = &omap44xx_wd_timer_hwmod_class,
4953 .mpu_irqs = omap44xx_wd_timer2_irqs,
4954 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
4955 .main_clk = "wd_timer2_fck",
4956 .prcm = {
4957 .omap4 = {
4958 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
4959 },
4960 },
4961 .slaves = omap44xx_wd_timer2_slaves,
4962 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
4963 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4964 };
4965
4966 /* wd_timer3 */
4967 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
4968 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
4969 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
4970 };
4971
4972 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4973 {
4974 .pa_start = 0x40130000,
4975 .pa_end = 0x4013007f,
4976 .flags = ADDR_TYPE_RT
4977 },
4978 };
4979
4980 /* l4_abe -> wd_timer3 */
4981 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4982 .master = &omap44xx_l4_abe_hwmod,
4983 .slave = &omap44xx_wd_timer3_hwmod,
4984 .clk = "ocp_abe_iclk",
4985 .addr = omap44xx_wd_timer3_addrs,
4986 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
4987 .user = OCP_USER_MPU,
4988 };
4989
4990 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4991 {
4992 .pa_start = 0x49030000,
4993 .pa_end = 0x4903007f,
4994 .flags = ADDR_TYPE_RT
4995 },
4996 };
4997
4998 /* l4_abe -> wd_timer3 (dma) */
4999 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5000 .master = &omap44xx_l4_abe_hwmod,
5001 .slave = &omap44xx_wd_timer3_hwmod,
5002 .clk = "ocp_abe_iclk",
5003 .addr = omap44xx_wd_timer3_dma_addrs,
5004 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
5005 .user = OCP_USER_SDMA,
5006 };
5007
5008 /* wd_timer3 slave ports */
5009 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5010 &omap44xx_l4_abe__wd_timer3,
5011 &omap44xx_l4_abe__wd_timer3_dma,
5012 };
5013
5014 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5015 .name = "wd_timer3",
5016 .class = &omap44xx_wd_timer_hwmod_class,
5017 .mpu_irqs = omap44xx_wd_timer3_irqs,
5018 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
5019 .main_clk = "wd_timer3_fck",
5020 .prcm = {
5021 .omap4 = {
5022 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
5023 },
5024 },
5025 .slaves = omap44xx_wd_timer3_slaves,
5026 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5027 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5028 };
5029
5030 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5031
5032 /* dmm class */
5033 &omap44xx_dmm_hwmod,
5034
5035 /* emif_fw class */
5036 &omap44xx_emif_fw_hwmod,
5037
5038 /* l3 class */
5039 &omap44xx_l3_instr_hwmod,
5040 &omap44xx_l3_main_1_hwmod,
5041 &omap44xx_l3_main_2_hwmod,
5042 &omap44xx_l3_main_3_hwmod,
5043
5044 /* l4 class */
5045 &omap44xx_l4_abe_hwmod,
5046 &omap44xx_l4_cfg_hwmod,
5047 &omap44xx_l4_per_hwmod,
5048 &omap44xx_l4_wkup_hwmod,
5049
5050 /* mpu_bus class */
5051 &omap44xx_mpu_private_hwmod,
5052
5053 /* aess class */
5054 /* &omap44xx_aess_hwmod, */
5055
5056 /* bandgap class */
5057 &omap44xx_bandgap_hwmod,
5058
5059 /* counter class */
5060 /* &omap44xx_counter_32k_hwmod, */
5061
5062 /* dma class */
5063 &omap44xx_dma_system_hwmod,
5064
5065 /* dmic class */
5066 &omap44xx_dmic_hwmod,
5067
5068 /* dsp class */
5069 &omap44xx_dsp_hwmod,
5070 &omap44xx_dsp_c0_hwmod,
5071
5072 /* dss class */
5073 &omap44xx_dss_hwmod,
5074 &omap44xx_dss_dispc_hwmod,
5075 &omap44xx_dss_dsi1_hwmod,
5076 &omap44xx_dss_dsi2_hwmod,
5077 &omap44xx_dss_hdmi_hwmod,
5078 &omap44xx_dss_rfbi_hwmod,
5079 &omap44xx_dss_venc_hwmod,
5080
5081 /* gpio class */
5082 &omap44xx_gpio1_hwmod,
5083 &omap44xx_gpio2_hwmod,
5084 &omap44xx_gpio3_hwmod,
5085 &omap44xx_gpio4_hwmod,
5086 &omap44xx_gpio5_hwmod,
5087 &omap44xx_gpio6_hwmod,
5088
5089 /* hsi class */
5090 /* &omap44xx_hsi_hwmod, */
5091
5092 /* i2c class */
5093 &omap44xx_i2c1_hwmod,
5094 &omap44xx_i2c2_hwmod,
5095 &omap44xx_i2c3_hwmod,
5096 &omap44xx_i2c4_hwmod,
5097
5098 /* ipu class */
5099 &omap44xx_ipu_hwmod,
5100 &omap44xx_ipu_c0_hwmod,
5101 &omap44xx_ipu_c1_hwmod,
5102
5103 /* iss class */
5104 /* &omap44xx_iss_hwmod, */
5105
5106 /* iva class */
5107 &omap44xx_iva_hwmod,
5108 &omap44xx_iva_seq0_hwmod,
5109 &omap44xx_iva_seq1_hwmod,
5110
5111 /* kbd class */
5112 /* &omap44xx_kbd_hwmod, */
5113
5114 /* mailbox class */
5115 &omap44xx_mailbox_hwmod,
5116
5117 /* mcbsp class */
5118 &omap44xx_mcbsp1_hwmod,
5119 &omap44xx_mcbsp2_hwmod,
5120 &omap44xx_mcbsp3_hwmod,
5121 &omap44xx_mcbsp4_hwmod,
5122
5123 /* mcpdm class */
5124 /* &omap44xx_mcpdm_hwmod, */
5125
5126 /* mcspi class */
5127 &omap44xx_mcspi1_hwmod,
5128 &omap44xx_mcspi2_hwmod,
5129 &omap44xx_mcspi3_hwmod,
5130 &omap44xx_mcspi4_hwmod,
5131
5132 /* mmc class */
5133 &omap44xx_mmc1_hwmod,
5134 &omap44xx_mmc2_hwmod,
5135 &omap44xx_mmc3_hwmod,
5136 &omap44xx_mmc4_hwmod,
5137 &omap44xx_mmc5_hwmod,
5138
5139 /* mpu class */
5140 &omap44xx_mpu_hwmod,
5141
5142 /* smartreflex class */
5143 &omap44xx_smartreflex_core_hwmod,
5144 &omap44xx_smartreflex_iva_hwmod,
5145 &omap44xx_smartreflex_mpu_hwmod,
5146
5147 /* spinlock class */
5148 &omap44xx_spinlock_hwmod,
5149
5150 /* timer class */
5151 &omap44xx_timer1_hwmod,
5152 &omap44xx_timer2_hwmod,
5153 &omap44xx_timer3_hwmod,
5154 &omap44xx_timer4_hwmod,
5155 &omap44xx_timer5_hwmod,
5156 &omap44xx_timer6_hwmod,
5157 &omap44xx_timer7_hwmod,
5158 &omap44xx_timer8_hwmod,
5159 &omap44xx_timer9_hwmod,
5160 &omap44xx_timer10_hwmod,
5161 &omap44xx_timer11_hwmod,
5162
5163 /* uart class */
5164 &omap44xx_uart1_hwmod,
5165 &omap44xx_uart2_hwmod,
5166 &omap44xx_uart3_hwmod,
5167 &omap44xx_uart4_hwmod,
5168
5169 /* usb_otg_hs class */
5170 &omap44xx_usb_otg_hs_hwmod,
5171
5172 /* wd_timer class */
5173 &omap44xx_wd_timer2_hwmod,
5174 &omap44xx_wd_timer3_hwmod,
5175
5176 NULL,
5177 };
5178
5179 int __init omap44xx_hwmod_init(void)
5180 {
5181 return omap_hwmod_register(omap44xx_hwmods);
5182 }
5183
Linux with added FPC-III support