arch/ia64/include/asm/processor.h

   1 #ifndef _ASM_IA64_PROCESSOR_H
   2 #define _ASM_IA64_PROCESSOR_H
   3
   4 /*
   5  * Copyright (C) 1998-2004 Hewlett-Packard Co
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  *      Stephane Eranian <eranian@hpl.hp.com>
   8  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
   9  * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
  10  *
  11  * 11/24/98     S.Eranian       added ia64_set_iva()
  12  * 12/03/99     D. Mosberger    implement thread_saved_pc() via kernel unwind API
  13  * 06/16/00     A. Mallick      added csd/ssd/tssd for ia32 support
  14  */
  15
  16
  17 #include <asm/intrinsics.h>
  18 #include <asm/kregs.h>
  19 #include <asm/ptrace.h>
  20 #include <asm/ustack.h>
  21
  22 #define __ARCH_WANT_UNLOCKED_CTXSW
  23 #define ARCH_HAS_PREFETCH_SWITCH_STACK
  24
  25 #define IA64_NUM_PHYS_STACK_REG 96
  26 #define IA64_NUM_DBG_REGS       8
  27
  28 #define DEFAULT_MAP_BASE        __IA64_UL_CONST(0x2000000000000000)
  29 #define DEFAULT_TASK_SIZE       __IA64_UL_CONST(0xa000000000000000)
  30
  31 /*
  32  * TASK_SIZE really is a mis-named.  It really is the maximum user
  33  * space address (plus one).  On IA-64, there are five regions of 2TB
  34  * each (assuming 8KB page size), for a total of 8TB of user virtual
  35  * address space.
  36  */
  37 #define TASK_SIZE               DEFAULT_TASK_SIZE
  38
  39 /*
  40  * This decides where the kernel will search for a free chunk of vm
  41  * space during mmap's.
  42  */
  43 #define TASK_UNMAPPED_BASE      (current->thread.map_base)
  44
  45 #define IA64_THREAD_FPH_VALID   (__IA64_UL(1) << 0)     /* floating-point high state valid? */
  46 #define IA64_THREAD_DBG_VALID   (__IA64_UL(1) << 1)     /* debug registers valid? */
  47 #define IA64_THREAD_PM_VALID    (__IA64_UL(1) << 2)     /* performance registers valid? */
  48 #define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3)     /* don't log unaligned accesses */
  49 #define IA64_THREAD_UAC_SIGBUS  (__IA64_UL(1) << 4)     /* generate SIGBUS on unaligned acc. */
  50 #define IA64_THREAD_MIGRATION   (__IA64_UL(1) << 5)     /* require migration
  51                                                            sync at ctx sw */
  52 #define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6)   /* don't log any fpswa faults */
  53 #define IA64_THREAD_FPEMU_SIGFPE  (__IA64_UL(1) << 7)   /* send a SIGFPE for fpswa faults */
  54
  55 #define IA64_THREAD_UAC_SHIFT   3
  56 #define IA64_THREAD_UAC_MASK    (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
  57 #define IA64_THREAD_FPEMU_SHIFT 6
  58 #define IA64_THREAD_FPEMU_MASK  (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
  59
  60
  61 /*
  62  * This shift should be large enough to be able to represent 1000000000/itc_freq with good
  63  * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
  64  * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
  65  */
  66 #define IA64_NSEC_PER_CYC_SHIFT 30
  67
  68 #ifndef __ASSEMBLY__
  69
  70 #include <linux/cache.h>
  71 #include <linux/compiler.h>
  72 #include <linux/threads.h>
  73 #include <linux/types.h>
  74 #include <linux/bitops.h>
  75
  76 #include <asm/fpu.h>
  77 #include <asm/page.h>
  78 #include <asm/percpu.h>
  79 #include <asm/rse.h>
  80 #include <asm/unwind.h>
  81 #include <linux/atomic.h>
  82 #ifdef CONFIG_NUMA
  83 #include <asm/nodedata.h>
  84 #endif
  85
  86 /* like above but expressed as bitfields for more efficient access: */
  87 struct ia64_psr {
  88         __u64 reserved0 : 1;
  89         __u64 be : 1;
  90         __u64 up : 1;
  91         __u64 ac : 1;
  92         __u64 mfl : 1;
  93         __u64 mfh : 1;
  94         __u64 reserved1 : 7;
  95         __u64 ic : 1;
  96         __u64 i : 1;
  97         __u64 pk : 1;
  98         __u64 reserved2 : 1;
  99         __u64 dt : 1;
 100         __u64 dfl : 1;
 101         __u64 dfh : 1;
 102         __u64 sp : 1;
 103         __u64 pp : 1;
 104         __u64 di : 1;
 105         __u64 si : 1;
 106         __u64 db : 1;
 107         __u64 lp : 1;
 108         __u64 tb : 1;
 109         __u64 rt : 1;
 110         __u64 reserved3 : 4;
 111         __u64 cpl : 2;
 112         __u64 is : 1;
 113         __u64 mc : 1;
 114         __u64 it : 1;
 115         __u64 id : 1;
 116         __u64 da : 1;
 117         __u64 dd : 1;
 118         __u64 ss : 1;
 119         __u64 ri : 2;
 120         __u64 ed : 1;
 121         __u64 bn : 1;
 122         __u64 reserved4 : 19;
 123 };
 124
 125 union ia64_isr {
 126         __u64  val;
 127         struct {
 128                 __u64 code : 16;
 129                 __u64 vector : 8;
 130                 __u64 reserved1 : 8;
 131                 __u64 x : 1;
 132                 __u64 w : 1;
 133                 __u64 r : 1;
 134                 __u64 na : 1;
 135                 __u64 sp : 1;
 136                 __u64 rs : 1;
 137                 __u64 ir : 1;
 138                 __u64 ni : 1;
 139                 __u64 so : 1;
 140                 __u64 ei : 2;
 141                 __u64 ed : 1;
 142                 __u64 reserved2 : 20;
 143         };
 144 };
 145
 146 union ia64_lid {
 147         __u64 val;
 148         struct {
 149                 __u64  rv  : 16;
 150                 __u64  eid : 8;
 151                 __u64  id  : 8;
 152                 __u64  ig  : 32;
 153         };
 154 };
 155
 156 union ia64_tpr {
 157         __u64 val;
 158         struct {
 159                 __u64 ig0 : 4;
 160                 __u64 mic : 4;
 161                 __u64 rsv : 8;
 162                 __u64 mmi : 1;
 163                 __u64 ig1 : 47;
 164         };
 165 };
 166
 167 union ia64_itir {
 168         __u64 val;
 169         struct {
 170                 __u64 rv3  :  2; /* 0-1 */
 171                 __u64 ps   :  6; /* 2-7 */
 172                 __u64 key  : 24; /* 8-31 */
 173                 __u64 rv4  : 32; /* 32-63 */
 174         };
 175 };
 176
 177 union  ia64_rr {
 178         __u64 val;
 179         struct {
 180                 __u64  ve       :  1;  /* enable hw walker */
 181                 __u64  reserved0:  1;  /* reserved */
 182                 __u64  ps       :  6;  /* log page size */
 183                 __u64  rid      : 24;  /* region id */
 184                 __u64  reserved1: 32;  /* reserved */
 185         };
 186 };
 187
 188 /*
 189  * CPU type, hardware bug flags, and per-CPU state.  Frequently used
 190  * state comes earlier:
 191  */
 192 struct cpuinfo_ia64 {
 193         unsigned int softirq_pending;
 194         unsigned long itm_delta;        /* # of clock cycles between clock ticks */
 195         unsigned long itm_next;         /* interval timer mask value to use for next clock tick */
 196         unsigned long nsec_per_cyc;     /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
 197         unsigned long unimpl_va_mask;   /* mask of unimplemented virtual address bits (from PAL) */
 198         unsigned long unimpl_pa_mask;   /* mask of unimplemented physical address bits (from PAL) */
 199         unsigned long itc_freq;         /* frequency of ITC counter */
 200         unsigned long proc_freq;        /* frequency of processor */
 201         unsigned long cyc_per_usec;     /* itc_freq/1000000 */
 202         unsigned long ptce_base;
 203         unsigned int ptce_count[2];
 204         unsigned int ptce_stride[2];
 205         struct task_struct *ksoftirqd;  /* kernel softirq daemon for this CPU */
 206
 207 #ifdef CONFIG_SMP
 208         unsigned long loops_per_jiffy;
 209         int cpu;
 210         unsigned int socket_id; /* physical processor socket id */
 211         unsigned short core_id; /* core id */
 212         unsigned short thread_id; /* thread id */
 213         unsigned short num_log; /* Total number of logical processors on
 214                                  * this socket that were successfully booted */
 215         unsigned char cores_per_socket; /* Cores per processor socket */
 216         unsigned char threads_per_core; /* Threads per core */
 217 #endif
 218
 219         /* CPUID-derived information: */
 220         unsigned long ppn;
 221         unsigned long features;
 222         unsigned char number;
 223         unsigned char revision;
 224         unsigned char model;
 225         unsigned char family;
 226         unsigned char archrev;
 227         char vendor[16];
 228         char *model_name;
 229
 230 #ifdef CONFIG_NUMA
 231         struct ia64_node_data *node_data;
 232 #endif
 233 };
 234
 235 DECLARE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info);
 236
 237 /*
 238  * The "local" data variable.  It refers to the per-CPU data of the currently executing
 239  * CPU, much like "current" points to the per-task data of the currently executing task.
 240  * Do not use the address of local_cpu_data, since it will be different from
 241  * cpu_data(smp_processor_id())!
 242  */
 243 #define local_cpu_data          (&__ia64_per_cpu_var(ia64_cpu_info))
 244 #define cpu_data(cpu)           (&per_cpu(ia64_cpu_info, cpu))
 245
 246 extern void print_cpu_info (struct cpuinfo_ia64 *);
 247
 248 typedef struct {
 249         unsigned long seg;
 250 } mm_segment_t;
 251
 252 #define SET_UNALIGN_CTL(task,value)                                                             \
 253 ({                                                                                              \
 254         (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK)                  \
 255                                 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
 256         0;                                                                                      \
 257 })
 258 #define GET_UNALIGN_CTL(task,addr)                                                              \
 259 ({                                                                                              \
 260         put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT,        \
 261                  (int __user *) (addr));                                                        \
 262 })
 263
 264 #define SET_FPEMU_CTL(task,value)                                                               \
 265 ({                                                                                              \
 266         (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK)                \
 267                           | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK));   \
 268         0;                                                                                      \
 269 })
 270 #define GET_FPEMU_CTL(task,addr)                                                                \
 271 ({                                                                                              \
 272         put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT,    \
 273                  (int __user *) (addr));                                                        \
 274 })
 275
 276 struct thread_struct {
 277         __u32 flags;                    /* various thread flags (see IA64_THREAD_*) */
 278         /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
 279         __u8 on_ustack;                 /* executing on user-stacks? */
 280         __u8 pad[3];
 281         __u64 ksp;                      /* kernel stack pointer */
 282         __u64 map_base;                 /* base address for get_unmapped_area() */
 283         __u64 rbs_bot;                  /* the base address for the RBS */
 284         int last_fph_cpu;               /* CPU that may hold the contents of f32-f127 */
 285
 286 #ifdef CONFIG_PERFMON
 287         void *pfm_context;                   /* pointer to detailed PMU context */
 288         unsigned long pfm_needs_checking;    /* when >0, pending perfmon work on kernel exit */
 289 # define INIT_THREAD_PM         .pfm_context =          NULL,     \
 290                                 .pfm_needs_checking =   0UL,
 291 #else
 292 # define INIT_THREAD_PM
 293 #endif
 294         unsigned long dbr[IA64_NUM_DBG_REGS];
 295         unsigned long ibr[IA64_NUM_DBG_REGS];
 296         struct ia64_fpreg fph[96];      /* saved/loaded on demand */
 297 };
 298
 299 #define INIT_THREAD {                                           \
 300         .flags =        0,                                      \
 301         .on_ustack =    0,                                      \
 302         .ksp =          0,                                      \
 303         .map_base =     DEFAULT_MAP_BASE,                       \
 304         .rbs_bot =      STACK_TOP - DEFAULT_USER_STACK_SIZE,    \
 305         .last_fph_cpu =  -1,                                    \
 306         INIT_THREAD_PM                                          \
 307         .dbr =          {0, },                                  \
 308         .ibr =          {0, },                                  \
 309         .fph =          {{{{0}}}, }                             \
 310 }
 311
 312 #define start_thread(regs,new_ip,new_sp) do {                                                   \
 313         regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL))                \
 314                          & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS));              \
 315         regs->cr_iip = new_ip;                                                                  \
 316         regs->ar_rsc = 0xf;             /* eager mode, privilege level 3 */                     \
 317         regs->ar_rnat = 0;                                                                      \
 318         regs->ar_bspstore = current->thread.rbs_bot;                                            \
 319         regs->ar_fpsr = FPSR_DEFAULT;                                                           \
 320         regs->loadrs = 0;                                                                       \
 321         regs->r8 = get_dumpable(current->mm);   /* set "don't zap registers" flag */            \
 322         regs->r12 = new_sp - 16;        /* allocate 16 byte scratch area */                     \
 323         if (unlikely(get_dumpable(current->mm) != SUID_DUMP_USER)) {    \
 324                 /*                                                                              \
 325                  * Zap scratch regs to avoid leaking bits between processes with different      \
 326                  * uid/privileges.                                                              \
 327                  */                                                                             \
 328                 regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0;                                   \
 329                 regs->r1 = 0; regs->r9  = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0;       \
 330         }                                                                                       \
 331 } while (0)
 332
 333 /* Forward declarations, a strange C thing... */
 334 struct mm_struct;
 335 struct task_struct;
 336
 337 /*
 338  * Free all resources held by a thread. This is called after the
 339  * parent of DEAD_TASK has collected the exit status of the task via
 340  * wait().
 341  */
 342 #define release_thread(dead_task)
 343
 344 /* Get wait channel for task P.  */
 345 extern unsigned long get_wchan (struct task_struct *p);
 346
 347 /* Return instruction pointer of blocked task TSK.  */
 348 #define KSTK_EIP(tsk)                                   \
 349   ({                                                    \
 350         struct pt_regs *_regs = task_pt_regs(tsk);      \
 351         _regs->cr_iip + ia64_psr(_regs)->ri;            \
 352   })
 353
 354 /* Return stack pointer of blocked task TSK.  */
 355 #define KSTK_ESP(tsk)  ((tsk)->thread.ksp)
 356
 357 extern void ia64_getreg_unknown_kr (void);
 358 extern void ia64_setreg_unknown_kr (void);
 359
 360 #define ia64_get_kr(regnum)                                     \
 361 ({                                                              \
 362         unsigned long r = 0;                                    \
 363                                                                 \
 364         switch (regnum) {                                       \
 365             case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break;   \
 366             case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break;   \
 367             case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break;   \
 368             case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break;   \
 369             case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break;   \
 370             case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break;   \
 371             case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break;   \
 372             case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break;   \
 373             default: ia64_getreg_unknown_kr(); break;           \
 374         }                                                       \
 375         r;                                                      \
 376 })
 377
 378 #define ia64_set_kr(regnum, r)                                  \
 379 ({                                                              \
 380         switch (regnum) {                                       \
 381             case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break;    \
 382             case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break;    \
 383             case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break;    \
 384             case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break;    \
 385             case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break;    \
 386             case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break;    \
 387             case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break;    \
 388             case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break;    \
 389             default: ia64_setreg_unknown_kr(); break;           \
 390         }                                                       \
 391 })
 392
 393 /*
 394  * The following three macros can't be inline functions because we don't have struct
 395  * task_struct at this point.
 396  */
 397
 398 /*
 399  * Return TRUE if task T owns the fph partition of the CPU we're running on.
 400  * Must be called from code that has preemption disabled.
 401  */
 402 #define ia64_is_local_fpu_owner(t)                                                              \
 403 ({                                                                                              \
 404         struct task_struct *__ia64_islfo_task = (t);                                            \
 405         (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id()                           \
 406          && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER));        \
 407 })
 408
 409 /*
 410  * Mark task T as owning the fph partition of the CPU we're running on.
 411  * Must be called from code that has preemption disabled.
 412  */
 413 #define ia64_set_local_fpu_owner(t) do {                                                \
 414         struct task_struct *__ia64_slfo_task = (t);                                     \
 415         __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id();                     \
 416         ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task);               \
 417 } while (0)
 418
 419 /* Mark the fph partition of task T as being invalid on all CPUs.  */
 420 #define ia64_drop_fpu(t)        ((t)->thread.last_fph_cpu = -1)
 421
 422 extern void __ia64_init_fpu (void);
 423 extern void __ia64_save_fpu (struct ia64_fpreg *fph);
 424 extern void __ia64_load_fpu (struct ia64_fpreg *fph);
 425 extern void ia64_save_debug_regs (unsigned long *save_area);
 426 extern void ia64_load_debug_regs (unsigned long *save_area);
 427
 428 #define ia64_fph_enable()       do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
 429 #define ia64_fph_disable()      do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
 430
 431 /* load fp 0.0 into fph */
 432 static inline void
 433 ia64_init_fpu (void) {
 434         ia64_fph_enable();
 435         __ia64_init_fpu();
 436         ia64_fph_disable();
 437 }
 438
 439 /* save f32-f127 at FPH */
 440 static inline void
 441 ia64_save_fpu (struct ia64_fpreg *fph) {
 442         ia64_fph_enable();
 443         __ia64_save_fpu(fph);
 444         ia64_fph_disable();
 445 }
 446
 447 /* load f32-f127 from FPH */
 448 static inline void
 449 ia64_load_fpu (struct ia64_fpreg *fph) {
 450         ia64_fph_enable();
 451         __ia64_load_fpu(fph);
 452         ia64_fph_disable();
 453 }
 454
 455 static inline __u64
 456 ia64_clear_ic (void)
 457 {
 458         __u64 psr;
 459         psr = ia64_getreg(_IA64_REG_PSR);
 460         ia64_stop();
 461         ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
 462         ia64_srlz_i();
 463         return psr;
 464 }
 465
 466 /*
 467  * Restore the psr.
 468  */
 469 static inline void
 470 ia64_set_psr (__u64 psr)
 471 {
 472         ia64_stop();
 473         ia64_setreg(_IA64_REG_PSR_L, psr);
 474         ia64_srlz_i();
 475 }
 476
 477 /*
 478  * Insert a translation into an instruction and/or data translation
 479  * register.
 480  */
 481 static inline void
 482 ia64_itr (__u64 target_mask, __u64 tr_num,
 483           __u64 vmaddr, __u64 pte,
 484           __u64 log_page_size)
 485 {
 486         ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
 487         ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
 488         ia64_stop();
 489         if (target_mask & 0x1)
 490                 ia64_itri(tr_num, pte);
 491         if (target_mask & 0x2)
 492                 ia64_itrd(tr_num, pte);
 493 }
 494
 495 /*
 496  * Insert a translation into the instruction and/or data translation
 497  * cache.
 498  */
 499 static inline void
 500 ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
 501           __u64 log_page_size)
 502 {
 503         ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
 504         ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
 505         ia64_stop();
 506         /* as per EAS2.6, itc must be the last instruction in an instruction group */
 507         if (target_mask & 0x1)
 508                 ia64_itci(pte);
 509         if (target_mask & 0x2)
 510                 ia64_itcd(pte);
 511 }
 512
 513 /*
 514  * Purge a range of addresses from instruction and/or data translation
 515  * register(s).
 516  */
 517 static inline void
 518 ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
 519 {
 520         if (target_mask & 0x1)
 521                 ia64_ptri(vmaddr, (log_size << 2));
 522         if (target_mask & 0x2)
 523                 ia64_ptrd(vmaddr, (log_size << 2));
 524 }
 525
 526 /* Set the interrupt vector address.  The address must be suitably aligned (32KB).  */
 527 static inline void
 528 ia64_set_iva (void *ivt_addr)
 529 {
 530         ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
 531         ia64_srlz_i();
 532 }
 533
 534 /* Set the page table address and control bits.  */
 535 static inline void
 536 ia64_set_pta (__u64 pta)
 537 {
 538         /* Note: srlz.i implies srlz.d */
 539         ia64_setreg(_IA64_REG_CR_PTA, pta);
 540         ia64_srlz_i();
 541 }
 542
 543 static inline void
 544 ia64_eoi (void)
 545 {
 546         ia64_setreg(_IA64_REG_CR_EOI, 0);
 547         ia64_srlz_d();
 548 }
 549
 550 #define cpu_relax()     ia64_hint(ia64_hint_pause)
 551
 552 static inline int
 553 ia64_get_irr(unsigned int vector)
 554 {
 555         unsigned int reg = vector / 64;
 556         unsigned int bit = vector % 64;
 557         u64 irr;
 558
 559         switch (reg) {
 560         case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break;
 561         case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break;
 562         case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break;
 563         case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break;
 564         }
 565
 566         return test_bit(bit, &irr);
 567 }
 568
 569 static inline void
 570 ia64_set_lrr0 (unsigned long val)
 571 {
 572         ia64_setreg(_IA64_REG_CR_LRR0, val);
 573         ia64_srlz_d();
 574 }
 575
 576 static inline void
 577 ia64_set_lrr1 (unsigned long val)
 578 {
 579         ia64_setreg(_IA64_REG_CR_LRR1, val);
 580         ia64_srlz_d();
 581 }
 582
 583
 584 /*
 585  * Given the address to which a spill occurred, return the unat bit
 586  * number that corresponds to this address.
 587  */
 588 static inline __u64
 589 ia64_unat_pos (void *spill_addr)
 590 {
 591         return ((__u64) spill_addr >> 3) & 0x3f;
 592 }
 593
 594 /*
 595  * Set the NaT bit of an integer register which was spilled at address
 596  * SPILL_ADDR.  UNAT is the mask to be updated.
 597  */
 598 static inline void
 599 ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
 600 {
 601         __u64 bit = ia64_unat_pos(spill_addr);
 602         __u64 mask = 1UL << bit;
 603
 604         *unat = (*unat & ~mask) | (nat << bit);
 605 }
 606
 607 /*
 608  * Return saved PC of a blocked thread.
 609  * Note that the only way T can block is through a call to schedule() -> switch_to().
 610  */
 611 static inline unsigned long
 612 thread_saved_pc (struct task_struct *t)
 613 {
 614         struct unw_frame_info info;
 615         unsigned long ip;
 616
 617         unw_init_from_blocked_task(&info, t);
 618         if (unw_unwind(&info) < 0)
 619                 return 0;
 620         unw_get_ip(&info, &ip);
 621         return ip;
 622 }
 623
 624 /*
 625  * Get the current instruction/program counter value.
 626  */
 627 #define current_text_addr() \
 628         ({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })
 629
 630 static inline __u64
 631 ia64_get_ivr (void)
 632 {
 633         __u64 r;
 634         ia64_srlz_d();
 635         r = ia64_getreg(_IA64_REG_CR_IVR);
 636         ia64_srlz_d();
 637         return r;
 638 }
 639
 640 static inline void
 641 ia64_set_dbr (__u64 regnum, __u64 value)
 642 {
 643         __ia64_set_dbr(regnum, value);
 644 #ifdef CONFIG_ITANIUM
 645         ia64_srlz_d();
 646 #endif
 647 }
 648
 649 static inline __u64
 650 ia64_get_dbr (__u64 regnum)
 651 {
 652         __u64 retval;
 653
 654         retval = __ia64_get_dbr(regnum);
 655 #ifdef CONFIG_ITANIUM
 656         ia64_srlz_d();
 657 #endif
 658         return retval;
 659 }
 660
 661 static inline __u64
 662 ia64_rotr (__u64 w, __u64 n)
 663 {
 664         return (w >> n) | (w << (64 - n));
 665 }
 666
 667 #define ia64_rotl(w,n)  ia64_rotr((w), (64) - (n))
 668
 669 /*
 670  * Take a mapped kernel address and return the equivalent address
 671  * in the region 7 identity mapped virtual area.
 672  */
 673 static inline void *
 674 ia64_imva (void *addr)
 675 {
 676         void *result;
 677         result = (void *) ia64_tpa(addr);
 678         return __va(result);
 679 }
 680
 681 #define ARCH_HAS_PREFETCH
 682 #define ARCH_HAS_PREFETCHW
 683 #define ARCH_HAS_SPINLOCK_PREFETCH
 684 #define PREFETCH_STRIDE                 L1_CACHE_BYTES
 685
 686 static inline void
 687 prefetch (const void *x)
 688 {
 689          ia64_lfetch(ia64_lfhint_none, x);
 690 }
 691
 692 static inline void
 693 prefetchw (const void *x)
 694 {
 695         ia64_lfetch_excl(ia64_lfhint_none, x);
 696 }
 697
 698 #define spin_lock_prefetch(x)   prefetchw(x)
 699
 700 extern unsigned long boot_option_idle_override;
 701
 702 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT,
 703                          IDLE_NOMWAIT, IDLE_POLL};
 704
 705 void default_idle(void);
 706
 707 #define ia64_platform_is(x) (strcmp(x, ia64_platform_name) == 0)
 708
 709 #endif /* !__ASSEMBLY__ */
 710
 711 #endif /* _ASM_IA64_PROCESSOR_H */