2 * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc.
4 * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
6 * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/of_platform.h>
28 #include "fsl_85xx_cache_ctlr.h"
30 static char *sram_size
;
31 static char *sram_offset
;
32 struct mpc85xx_l2ctlr __iomem
*l2ctlr
;
34 static int get_cache_sram_params(struct sram_parameters
*sram_params
)
36 unsigned long long addr
;
39 if (!sram_size
|| (kstrtouint(sram_size
, 0, &size
) < 0))
42 if (!sram_offset
|| (kstrtoull(sram_offset
, 0, &addr
) < 0))
45 sram_params
->sram_offset
= addr
;
46 sram_params
->sram_size
= size
;
51 static int __init
get_size_from_cmdline(char *str
)
60 static int __init
get_offset_from_cmdline(char *str
)
69 __setup("cache-sram-size=", get_size_from_cmdline
);
70 __setup("cache-sram-offset=", get_offset_from_cmdline
);
72 static int mpc85xx_l2ctlr_of_probe(struct platform_device
*dev
)
77 const unsigned int *prop
;
78 unsigned int l2cache_size
;
79 struct sram_parameters sram_params
;
81 if (!dev
->dev
.of_node
) {
82 dev_err(&dev
->dev
, "Device's OF-node is NULL\n");
86 prop
= of_get_property(dev
->dev
.of_node
, "cache-size", NULL
);
88 dev_err(&dev
->dev
, "Missing L2 cache-size\n");
93 if (get_cache_sram_params(&sram_params
)) {
95 "Entire L2 as cache, provide valid sram offset and size\n");
100 rem
= l2cache_size
% sram_params
.sram_size
;
101 ways
= LOCK_WAYS_FULL
* sram_params
.sram_size
/ l2cache_size
;
102 if (rem
|| (ways
& (ways
- 1))) {
103 dev_err(&dev
->dev
, "Illegal cache-sram-size in command line\n");
107 l2ctlr
= of_iomap(dev
->dev
.of_node
, 0);
109 dev_err(&dev
->dev
, "Can't map L2 controller\n");
114 * Write bits[0-17] to srbar0
116 out_be32(&l2ctlr
->srbar0
,
117 lower_32_bits(sram_params
.sram_offset
) & L2SRAM_BAR_MSK_LO18
);
120 * Write bits[18-21] to srbare0
122 #ifdef CONFIG_PHYS_64BIT
123 out_be32(&l2ctlr
->srbarea0
,
124 upper_32_bits(sram_params
.sram_offset
) & L2SRAM_BARE_MSK_HI4
);
127 clrsetbits_be32(&l2ctlr
->ctl
, L2CR_L2E
, L2CR_L2FI
);
130 case LOCK_WAYS_EIGHTH
:
131 setbits32(&l2ctlr
->ctl
,
132 L2CR_L2E
| L2CR_L2FI
| L2CR_SRAM_EIGHTH
);
135 case LOCK_WAYS_TWO_EIGHTH
:
136 setbits32(&l2ctlr
->ctl
,
137 L2CR_L2E
| L2CR_L2FI
| L2CR_SRAM_QUART
);
141 setbits32(&l2ctlr
->ctl
,
142 L2CR_L2E
| L2CR_L2FI
| L2CR_SRAM_HALF
);
147 setbits32(&l2ctlr
->ctl
,
148 L2CR_L2E
| L2CR_L2FI
| L2CR_SRAM_FULL
);
153 rval
= instantiate_cache_sram(dev
, sram_params
);
155 dev_err(&dev
->dev
, "Can't instantiate Cache-SRAM\n");
163 static int mpc85xx_l2ctlr_of_remove(struct platform_device
*dev
)
168 remove_cache_sram(dev
);
169 dev_info(&dev
->dev
, "MPC85xx L2 controller unloaded\n");
174 static struct of_device_id mpc85xx_l2ctlr_of_match
[] = {
176 .compatible
= "fsl,p2020-l2-cache-controller",
179 .compatible
= "fsl,p2010-l2-cache-controller",
182 .compatible
= "fsl,p1020-l2-cache-controller",
185 .compatible
= "fsl,p1011-l2-cache-controller",
188 .compatible
= "fsl,p1013-l2-cache-controller",
191 .compatible
= "fsl,p1022-l2-cache-controller",
194 .compatible
= "fsl,mpc8548-l2-cache-controller",
196 { .compatible
= "fsl,mpc8544-l2-cache-controller",},
197 { .compatible
= "fsl,mpc8572-l2-cache-controller",},
198 { .compatible
= "fsl,mpc8536-l2-cache-controller",},
199 { .compatible
= "fsl,p1021-l2-cache-controller",},
200 { .compatible
= "fsl,p1012-l2-cache-controller",},
201 { .compatible
= "fsl,p1025-l2-cache-controller",},
202 { .compatible
= "fsl,p1016-l2-cache-controller",},
203 { .compatible
= "fsl,p1024-l2-cache-controller",},
204 { .compatible
= "fsl,p1015-l2-cache-controller",},
205 { .compatible
= "fsl,p1010-l2-cache-controller",},
206 { .compatible
= "fsl,bsc9131-l2-cache-controller",},
210 static struct platform_driver mpc85xx_l2ctlr_of_platform_driver
= {
212 .name
= "fsl-l2ctlr",
213 .owner
= THIS_MODULE
,
214 .of_match_table
= mpc85xx_l2ctlr_of_match
,
216 .probe
= mpc85xx_l2ctlr_of_probe
,
217 .remove
= mpc85xx_l2ctlr_of_remove
,
220 static __init
int mpc85xx_l2ctlr_of_init(void)
222 return platform_driver_register(&mpc85xx_l2ctlr_of_platform_driver
);
225 static void __exit
mpc85xx_l2ctlr_of_exit(void)
227 platform_driver_unregister(&mpc85xx_l2ctlr_of_platform_driver
);
230 subsys_initcall(mpc85xx_l2ctlr_of_init
);
231 module_exit(mpc85xx_l2ctlr_of_exit
);
233 MODULE_DESCRIPTION("Freescale MPC85xx L2 controller init");
234 MODULE_LICENSE("GPL v2");