drivers/platform/x86/intel_pmic_gpio.c

   1 /* Moorestown PMIC GPIO (access through IPC) driver
   2  * Copyright (c) 2008 - 2009, Intel Corporation.
   3  *
   4  * Author: Alek Du <alek.du@intel.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 /* Supports:
  21  * Moorestown platform PMIC chip
  22  */
  23
  24 #define pr_fmt(fmt) "%s: " fmt, __func__
  25
  26 #include <linux/kernel.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <linux/stddef.h>
  30 #include <linux/slab.h>
  31 #include <linux/ioport.h>
  32 #include <linux/init.h>
  33 #include <linux/io.h>
  34 #include <linux/gpio/driver.h>
  35 #include <asm/intel_scu_ipc.h>
  36 #include <linux/device.h>
  37 #include <linux/intel_pmic_gpio.h>
  38 #include <linux/platform_device.h>
  39
  40 #define DRIVER_NAME "pmic_gpio"
  41
  42 /* register offset that IPC driver should use
  43  * 8 GPIO + 8 GPOSW (6 controllable) + 8GPO
  44  */
  45 enum pmic_gpio_register {
  46         GPIO0           = 0xE0,
  47         GPIO7           = 0xE7,
  48         GPIOINT         = 0xE8,
  49         GPOSWCTL0       = 0xEC,
  50         GPOSWCTL5       = 0xF1,
  51         GPO             = 0xF4,
  52 };
  53
  54 /* bits definition for GPIO & GPOSW */
  55 #define GPIO_DRV 0x01
  56 #define GPIO_DIR 0x02
  57 #define GPIO_DIN 0x04
  58 #define GPIO_DOU 0x08
  59 #define GPIO_INTCTL 0x30
  60 #define GPIO_DBC 0xc0
  61
  62 #define GPOSW_DRV 0x01
  63 #define GPOSW_DOU 0x08
  64 #define GPOSW_RDRV 0x30
  65
  66 #define GPIO_UPDATE_TYPE        0x80000000
  67
  68 #define NUM_GPIO 24
  69
  70 struct pmic_gpio {
  71         struct mutex            buslock;
  72         struct gpio_chip        chip;
  73         void                    *gpiointr;
  74         int                     irq;
  75         unsigned                irq_base;
  76         unsigned int            update_type;
  77         u32                     trigger_type;
  78 };
  79
  80 static void pmic_program_irqtype(int gpio, int type)
  81 {
  82         if (type & IRQ_TYPE_EDGE_RISING)
  83                 intel_scu_ipc_update_register(GPIO0 + gpio, 0x20, 0x20);
  84         else
  85                 intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x20);
  86
  87         if (type & IRQ_TYPE_EDGE_FALLING)
  88                 intel_scu_ipc_update_register(GPIO0 + gpio, 0x10, 0x10);
  89         else
  90                 intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x10);
  91 };
  92
  93 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  94 {
  95         if (offset >= 8) {
  96                 pr_err("only pin 0-7 support input\n");
  97                 return -1;/* we only have 8 GPIO can use as input */
  98         }
  99         return intel_scu_ipc_update_register(GPIO0 + offset,
 100                                                         GPIO_DIR, GPIO_DIR);
 101 }
 102
 103 static int pmic_gpio_direction_output(struct gpio_chip *chip,
 104                         unsigned offset, int value)
 105 {
 106         int rc = 0;
 107
 108         if (offset < 8)/* it is GPIO */
 109                 rc = intel_scu_ipc_update_register(GPIO0 + offset,
 110                                 GPIO_DRV | (value ? GPIO_DOU : 0),
 111                                 GPIO_DRV | GPIO_DOU | GPIO_DIR);
 112         else if (offset < 16)/* it is GPOSW */
 113                 rc = intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
 114                                 GPOSW_DRV | (value ? GPOSW_DOU : 0),
 115                                 GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
 116         else if (offset > 15 && offset < 24)/* it is GPO */
 117                 rc = intel_scu_ipc_update_register(GPO,
 118                                 value ? 1 << (offset - 16) : 0,
 119                                 1 << (offset - 16));
 120         else {
 121                 pr_err("invalid PMIC GPIO pin %d!\n", offset);
 122                 WARN_ON(1);
 123         }
 124
 125         return rc;
 126 }
 127
 128 static int pmic_gpio_get(struct gpio_chip *chip, unsigned offset)
 129 {
 130         u8 r;
 131         int ret;
 132
 133         /* we only have 8 GPIO pins we can use as input */
 134         if (offset >= 8)
 135                 return -EOPNOTSUPP;
 136         ret = intel_scu_ipc_ioread8(GPIO0 + offset, &r);
 137         if (ret < 0)
 138                 return ret;
 139         return r & GPIO_DIN;
 140 }
 141
 142 static void pmic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 143 {
 144         if (offset < 8)/* it is GPIO */
 145                 intel_scu_ipc_update_register(GPIO0 + offset,
 146                         GPIO_DRV | (value ? GPIO_DOU : 0),
 147                         GPIO_DRV | GPIO_DOU);
 148         else if (offset < 16)/* it is GPOSW */
 149                 intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
 150                         GPOSW_DRV | (value ? GPOSW_DOU : 0),
 151                         GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
 152         else if (offset > 15 && offset < 24) /* it is GPO */
 153                 intel_scu_ipc_update_register(GPO,
 154                         value ? 1 << (offset - 16) : 0,
 155                         1 << (offset - 16));
 156 }
 157
 158 /*
 159  * This is called from genirq with pg->buslock locked and
 160  * irq_desc->lock held. We can not access the scu bus here, so we
 161  * store the change and update in the bus_sync_unlock() function below
 162  */
 163 static int pmic_irq_type(struct irq_data *data, unsigned type)
 164 {
 165         struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
 166         u32 gpio = data->irq - pg->irq_base;
 167
 168         if (gpio >= pg->chip.ngpio)
 169                 return -EINVAL;
 170
 171         pg->trigger_type = type;
 172         pg->update_type = gpio | GPIO_UPDATE_TYPE;
 173         return 0;
 174 }
 175
 176 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 177 {
 178         struct pmic_gpio *pg = gpiochip_get_data(chip);
 179
 180         return pg->irq_base + offset;
 181 }
 182
 183 static void pmic_bus_lock(struct irq_data *data)
 184 {
 185         struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
 186
 187         mutex_lock(&pg->buslock);
 188 }
 189
 190 static void pmic_bus_sync_unlock(struct irq_data *data)
 191 {
 192         struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
 193
 194         if (pg->update_type) {
 195                 unsigned int gpio = pg->update_type & ~GPIO_UPDATE_TYPE;
 196
 197                 pmic_program_irqtype(gpio, pg->trigger_type);
 198                 pg->update_type = 0;
 199         }
 200         mutex_unlock(&pg->buslock);
 201 }
 202
 203 /* the gpiointr register is read-clear, so just do nothing. */
 204 static void pmic_irq_unmask(struct irq_data *data) { }
 205
 206 static void pmic_irq_mask(struct irq_data *data) { }
 207
 208 static struct irq_chip pmic_irqchip = {
 209         .name                   = "PMIC-GPIO",
 210         .irq_mask               = pmic_irq_mask,
 211         .irq_unmask             = pmic_irq_unmask,
 212         .irq_set_type           = pmic_irq_type,
 213         .irq_bus_lock           = pmic_bus_lock,
 214         .irq_bus_sync_unlock    = pmic_bus_sync_unlock,
 215 };
 216
 217 static irqreturn_t pmic_irq_handler(int irq, void *data)
 218 {
 219         struct pmic_gpio *pg = data;
 220         u8 intsts = *((u8 *)pg->gpiointr + 4);
 221         int gpio;
 222         irqreturn_t ret = IRQ_NONE;
 223
 224         for (gpio = 0; gpio < 8; gpio++) {
 225                 if (intsts & (1 << gpio)) {
 226                         pr_debug("pmic pin %d triggered\n", gpio);
 227                         generic_handle_irq(pg->irq_base + gpio);
 228                         ret = IRQ_HANDLED;
 229                 }
 230         }
 231         return ret;
 232 }
 233
 234 static int platform_pmic_gpio_probe(struct platform_device *pdev)
 235 {
 236         struct device *dev = &pdev->dev;
 237         int irq = platform_get_irq(pdev, 0);
 238         struct intel_pmic_gpio_platform_data *pdata = dev->platform_data;
 239
 240         struct pmic_gpio *pg;
 241         int retval;
 242         int i;
 243
 244         if (irq < 0) {
 245                 dev_dbg(dev, "no IRQ line\n");
 246                 return -EINVAL;
 247         }
 248
 249         if (!pdata || !pdata->gpio_base || !pdata->irq_base) {
 250                 dev_dbg(dev, "incorrect or missing platform data\n");
 251                 return -EINVAL;
 252         }
 253
 254         pg = kzalloc(sizeof(*pg), GFP_KERNEL);
 255         if (!pg)
 256                 return -ENOMEM;
 257
 258         dev_set_drvdata(dev, pg);
 259
 260         pg->irq = irq;
 261         /* setting up SRAM mapping for GPIOINT register */
 262         pg->gpiointr = ioremap_nocache(pdata->gpiointr, 8);
 263         if (!pg->gpiointr) {
 264                 pr_err("Can not map GPIOINT\n");
 265                 retval = -EINVAL;
 266                 goto err2;
 267         }
 268         pg->irq_base = pdata->irq_base;
 269         pg->chip.label = "intel_pmic";
 270         pg->chip.direction_input = pmic_gpio_direction_input;
 271         pg->chip.direction_output = pmic_gpio_direction_output;
 272         pg->chip.get = pmic_gpio_get;
 273         pg->chip.set = pmic_gpio_set;
 274         pg->chip.to_irq = pmic_gpio_to_irq;
 275         pg->chip.base = pdata->gpio_base;
 276         pg->chip.ngpio = NUM_GPIO;
 277         pg->chip.can_sleep = 1;
 278         pg->chip.parent = dev;
 279
 280         mutex_init(&pg->buslock);
 281
 282         pg->chip.parent = dev;
 283         retval = gpiochip_add_data(&pg->chip, pg);
 284         if (retval) {
 285                 pr_err("Can not add pmic gpio chip\n");
 286                 goto err;
 287         }
 288
 289         retval = request_irq(pg->irq, pmic_irq_handler, 0, "pmic", pg);
 290         if (retval) {
 291                 pr_warn("Interrupt request failed\n");
 292                 goto fail_request_irq;
 293         }
 294
 295         for (i = 0; i < 8; i++) {
 296                 irq_set_chip_and_handler_name(i + pg->irq_base,
 297                                               &pmic_irqchip,
 298                                               handle_simple_irq,
 299                                               "demux");
 300                 irq_set_chip_data(i + pg->irq_base, pg);
 301         }
 302         return 0;
 303
 304 fail_request_irq:
 305         gpiochip_remove(&pg->chip);
 306 err:
 307         iounmap(pg->gpiointr);
 308 err2:
 309         kfree(pg);
 310         return retval;
 311 }
 312
 313 /* at the same time, register a platform driver
 314  * this supports the sfi 0.81 fw */
 315 static struct platform_driver platform_pmic_gpio_driver = {
 316         .driver = {
 317                 .name           = DRIVER_NAME,
 318         },
 319         .probe          = platform_pmic_gpio_probe,
 320 };
 321
 322 static int __init platform_pmic_gpio_init(void)
 323 {
 324         return platform_driver_register(&platform_pmic_gpio_driver);
 325 }
 326 subsys_initcall(platform_pmic_gpio_init);