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of/platform: Initialise default DMA masks
[linux/fpc-iii.git] / drivers / iommu / amd_iommu.c
blob596b95c50051dcb75adb67496579af4b501d0ace
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dma-direct.h>
32 #include <linux/iommu-helper.h>
33 #include <linux/iommu.h>
34 #include <linux/delay.h>
35 #include <linux/amd-iommu.h>
36 #include <linux/notifier.h>
37 #include <linux/export.h>
38 #include <linux/irq.h>
39 #include <linux/msi.h>
40 #include <linux/dma-contiguous.h>
41 #include <linux/irqdomain.h>
42 #include <linux/percpu.h>
43 #include <linux/iova.h>
44 #include <asm/irq_remapping.h>
45 #include <asm/io_apic.h>
46 #include <asm/apic.h>
47 #include <asm/hw_irq.h>
48 #include <asm/msidef.h>
49 #include <asm/proto.h>
50 #include <asm/iommu.h>
51 #include <asm/gart.h>
52 #include <asm/dma.h>
53
54 #include "amd_iommu_proto.h"
55 #include "amd_iommu_types.h"
56 #include "irq_remapping.h"
57
58 #define AMD_IOMMU_MAPPING_ERROR 0
59
60 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
61
62 #define LOOP_TIMEOUT 100000
63
64 /* IO virtual address start page frame number */
65 #define IOVA_START_PFN (1)
66 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
67
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
73
74 /*
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
78 * that we support.
79 *
80 * 512GB Pages are not supported due to a hardware bug
81 */
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
83
84 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
85 static DEFINE_SPINLOCK(pd_bitmap_lock);
86
87 /* List of all available dev_data structures */
88 static LLIST_HEAD(dev_data_list);
89
90 LIST_HEAD(ioapic_map);
91 LIST_HEAD(hpet_map);
92 LIST_HEAD(acpihid_map);
93
94 /*
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
97 */
98 const struct iommu_ops amd_iommu_ops;
99
100 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
101 int amd_iommu_max_glx_val = -1;
102
103 static const struct dma_map_ops amd_iommu_dma_ops;
104
105 /*
106 * general struct to manage commands send to an IOMMU
107 */
108 struct iommu_cmd {
109 u32 data[4];
110 };
111
112 struct kmem_cache *amd_iommu_irq_cache;
113
114 static void update_domain(struct protection_domain *domain);
115 static int protection_domain_init(struct protection_domain *domain);
116 static void detach_device(struct device *dev);
117 static void iova_domain_flush_tlb(struct iova_domain *iovad);
118
119 /*
120 * Data container for a dma_ops specific protection domain
121 */
122 struct dma_ops_domain {
123 /* generic protection domain information */
124 struct protection_domain domain;
125
126 /* IOVA RB-Tree */
127 struct iova_domain iovad;
128 };
129
130 static struct iova_domain reserved_iova_ranges;
131 static struct lock_class_key reserved_rbtree_key;
132
133 /****************************************************************************
134 *
135 * Helper functions
136 *
137 ****************************************************************************/
138
139 static inline int match_hid_uid(struct device *dev,
140 struct acpihid_map_entry *entry)
141 {
142 const char *hid, *uid;
143
144 hid = acpi_device_hid(ACPI_COMPANION(dev));
145 uid = acpi_device_uid(ACPI_COMPANION(dev));
146
147 if (!hid || !(*hid))
148 return -ENODEV;
149
150 if (!uid || !(*uid))
151 return strcmp(hid, entry->hid);
152
153 if (!(*entry->uid))
154 return strcmp(hid, entry->hid);
155
156 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
157 }
158
159 static inline u16 get_pci_device_id(struct device *dev)
160 {
161 struct pci_dev *pdev = to_pci_dev(dev);
162
163 return PCI_DEVID(pdev->bus->number, pdev->devfn);
164 }
165
166 static inline int get_acpihid_device_id(struct device *dev,
167 struct acpihid_map_entry **entry)
168 {
169 struct acpihid_map_entry *p;
170
171 list_for_each_entry(p, &acpihid_map, list) {
172 if (!match_hid_uid(dev, p)) {
173 if (entry)
174 *entry = p;
175 return p->devid;
176 }
177 }
178 return -EINVAL;
179 }
180
181 static inline int get_device_id(struct device *dev)
182 {
183 int devid;
184
185 if (dev_is_pci(dev))
186 devid = get_pci_device_id(dev);
187 else
188 devid = get_acpihid_device_id(dev, NULL);
189
190 return devid;
191 }
192
193 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
194 {
195 return container_of(dom, struct protection_domain, domain);
196 }
197
198 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
199 {
200 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
201 return container_of(domain, struct dma_ops_domain, domain);
202 }
203
204 static struct iommu_dev_data *alloc_dev_data(u16 devid)
205 {
206 struct iommu_dev_data *dev_data;
207
208 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
209 if (!dev_data)
210 return NULL;
211
212 dev_data->devid = devid;
213 ratelimit_default_init(&dev_data->rs);
214
215 llist_add(&dev_data->dev_data_list, &dev_data_list);
216 return dev_data;
217 }
218
219 static struct iommu_dev_data *search_dev_data(u16 devid)
220 {
221 struct iommu_dev_data *dev_data;
222 struct llist_node *node;
223
224 if (llist_empty(&dev_data_list))
225 return NULL;
226
227 node = dev_data_list.first;
228 llist_for_each_entry(dev_data, node, dev_data_list) {
229 if (dev_data->devid == devid)
230 return dev_data;
231 }
232
233 return NULL;
234 }
235
236 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
237 {
238 *(u16 *)data = alias;
239 return 0;
240 }
241
242 static u16 get_alias(struct device *dev)
243 {
244 struct pci_dev *pdev = to_pci_dev(dev);
245 u16 devid, ivrs_alias, pci_alias;
246
247 /* The callers make sure that get_device_id() does not fail here */
248 devid = get_device_id(dev);
249 ivrs_alias = amd_iommu_alias_table[devid];
250 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
251
252 if (ivrs_alias == pci_alias)
253 return ivrs_alias;
254
255 /*
256 * DMA alias showdown
257 *
258 * The IVRS is fairly reliable in telling us about aliases, but it
259 * can't know about every screwy device. If we don't have an IVRS
260 * reported alias, use the PCI reported alias. In that case we may
261 * still need to initialize the rlookup and dev_table entries if the
262 * alias is to a non-existent device.
263 */
264 if (ivrs_alias == devid) {
265 if (!amd_iommu_rlookup_table[pci_alias]) {
266 amd_iommu_rlookup_table[pci_alias] =
267 amd_iommu_rlookup_table[devid];
268 memcpy(amd_iommu_dev_table[pci_alias].data,
269 amd_iommu_dev_table[devid].data,
270 sizeof(amd_iommu_dev_table[pci_alias].data));
271 }
272
273 return pci_alias;
274 }
275
276 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
277 "for device %s[%04x:%04x], kernel reported alias "
278 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
279 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
280 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
281 PCI_FUNC(pci_alias));
282
283 /*
284 * If we don't have a PCI DMA alias and the IVRS alias is on the same
285 * bus, then the IVRS table may know about a quirk that we don't.
286 */
287 if (pci_alias == devid &&
288 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
289 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
290 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
291 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
292 dev_name(dev));
293 }
294
295 return ivrs_alias;
296 }
297
298 static struct iommu_dev_data *find_dev_data(u16 devid)
299 {
300 struct iommu_dev_data *dev_data;
301 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
302
303 dev_data = search_dev_data(devid);
304
305 if (dev_data == NULL) {
306 dev_data = alloc_dev_data(devid);
307 if (!dev_data)
308 return NULL;
309
310 if (translation_pre_enabled(iommu))
311 dev_data->defer_attach = true;
312 }
313
314 return dev_data;
315 }
316
317 struct iommu_dev_data *get_dev_data(struct device *dev)
318 {
319 return dev->archdata.iommu;
320 }
321 EXPORT_SYMBOL(get_dev_data);
322
323 /*
324 * Find or create an IOMMU group for a acpihid device.
325 */
326 static struct iommu_group *acpihid_device_group(struct device *dev)
327 {
328 struct acpihid_map_entry *p, *entry = NULL;
329 int devid;
330
331 devid = get_acpihid_device_id(dev, &entry);
332 if (devid < 0)
333 return ERR_PTR(devid);
334
335 list_for_each_entry(p, &acpihid_map, list) {
336 if ((devid == p->devid) && p->group)
337 entry->group = p->group;
338 }
339
340 if (!entry->group)
341 entry->group = generic_device_group(dev);
342 else
343 iommu_group_ref_get(entry->group);
344
345 return entry->group;
346 }
347
348 static bool pci_iommuv2_capable(struct pci_dev *pdev)
349 {
350 static const int caps[] = {
351 PCI_EXT_CAP_ID_ATS,
352 PCI_EXT_CAP_ID_PRI,
353 PCI_EXT_CAP_ID_PASID,
354 };
355 int i, pos;
356
357 if (pci_ats_disabled())
358 return false;
359
360 for (i = 0; i < 3; ++i) {
361 pos = pci_find_ext_capability(pdev, caps[i]);
362 if (pos == 0)
363 return false;
364 }
365
366 return true;
367 }
368
369 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
370 {
371 struct iommu_dev_data *dev_data;
372
373 dev_data = get_dev_data(&pdev->dev);
374
375 return dev_data->errata & (1 << erratum) ? true : false;
376 }
377
378 /*
379 * This function checks if the driver got a valid device from the caller to
380 * avoid dereferencing invalid pointers.
381 */
382 static bool check_device(struct device *dev)
383 {
384 int devid;
385
386 if (!dev || !dev->dma_mask)
387 return false;
388
389 devid = get_device_id(dev);
390 if (devid < 0)
391 return false;
392
393 /* Out of our scope? */
394 if (devid > amd_iommu_last_bdf)
395 return false;
396
397 if (amd_iommu_rlookup_table[devid] == NULL)
398 return false;
399
400 return true;
401 }
402
403 static void init_iommu_group(struct device *dev)
404 {
405 struct iommu_group *group;
406
407 group = iommu_group_get_for_dev(dev);
408 if (IS_ERR(group))
409 return;
410
411 iommu_group_put(group);
412 }
413
414 static int iommu_init_device(struct device *dev)
415 {
416 struct iommu_dev_data *dev_data;
417 struct amd_iommu *iommu;
418 int devid;
419
420 if (dev->archdata.iommu)
421 return 0;
422
423 devid = get_device_id(dev);
424 if (devid < 0)
425 return devid;
426
427 iommu = amd_iommu_rlookup_table[devid];
428
429 dev_data = find_dev_data(devid);
430 if (!dev_data)
431 return -ENOMEM;
432
433 dev_data->alias = get_alias(dev);
434
435 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
436 struct amd_iommu *iommu;
437
438 iommu = amd_iommu_rlookup_table[dev_data->devid];
439 dev_data->iommu_v2 = iommu->is_iommu_v2;
440 }
441
442 dev->archdata.iommu = dev_data;
443
444 iommu_device_link(&iommu->iommu, dev);
445
446 return 0;
447 }
448
449 static void iommu_ignore_device(struct device *dev)
450 {
451 u16 alias;
452 int devid;
453
454 devid = get_device_id(dev);
455 if (devid < 0)
456 return;
457
458 alias = get_alias(dev);
459
460 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
461 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
462
463 amd_iommu_rlookup_table[devid] = NULL;
464 amd_iommu_rlookup_table[alias] = NULL;
465 }
466
467 static void iommu_uninit_device(struct device *dev)
468 {
469 struct iommu_dev_data *dev_data;
470 struct amd_iommu *iommu;
471 int devid;
472
473 devid = get_device_id(dev);
474 if (devid < 0)
475 return;
476
477 iommu = amd_iommu_rlookup_table[devid];
478
479 dev_data = search_dev_data(devid);
480 if (!dev_data)
481 return;
482
483 if (dev_data->domain)
484 detach_device(dev);
485
486 iommu_device_unlink(&iommu->iommu, dev);
487
488 iommu_group_remove_device(dev);
489
490 /* Remove dma-ops */
491 dev->dma_ops = NULL;
492
493 /*
494 * We keep dev_data around for unplugged devices and reuse it when the
495 * device is re-plugged - not doing so would introduce a ton of races.
496 */
497 }
498
499 /****************************************************************************
500 *
501 * Interrupt handling functions
502 *
503 ****************************************************************************/
504
505 static void dump_dte_entry(u16 devid)
506 {
507 int i;
508
509 for (i = 0; i < 4; ++i)
510 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
511 amd_iommu_dev_table[devid].data[i]);
512 }
513
514 static void dump_command(unsigned long phys_addr)
515 {
516 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
517 int i;
518
519 for (i = 0; i < 4; ++i)
520 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
521 }
522
523 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
524 u64 address, int flags)
525 {
526 struct iommu_dev_data *dev_data = NULL;
527 struct pci_dev *pdev;
528
529 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
530 devid & 0xff);
531 if (pdev)
532 dev_data = get_dev_data(&pdev->dev);
533
534 if (dev_data && __ratelimit(&dev_data->rs)) {
535 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
536 domain_id, address, flags);
537 } else if (printk_ratelimit()) {
538 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
539 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
540 domain_id, address, flags);
541 }
542
543 if (pdev)
544 pci_dev_put(pdev);
545 }
546
547 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
548 {
549 struct device *dev = iommu->iommu.dev;
550 int type, devid, pasid, flags, tag;
551 volatile u32 *event = __evt;
552 int count = 0;
553 u64 address;
554
555 retry:
556 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
557 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
558 pasid = PPR_PASID(*(u64 *)&event[0]);
559 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
560 address = (u64)(((u64)event[3]) << 32) | event[2];
561
562 if (type == 0) {
563 /* Did we hit the erratum? */
564 if (++count == LOOP_TIMEOUT) {
565 pr_err("AMD-Vi: No event written to event log\n");
566 return;
567 }
568 udelay(1);
569 goto retry;
570 }
571
572 if (type == EVENT_TYPE_IO_FAULT) {
573 amd_iommu_report_page_fault(devid, pasid, address, flags);
574 return;
575 } else {
576 dev_err(dev, "AMD-Vi: Event logged [");
577 }
578
579 switch (type) {
580 case EVENT_TYPE_ILL_DEV:
581 dev_err(dev, "ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
582 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
583 pasid, address, flags);
584 dump_dte_entry(devid);
585 break;
586 case EVENT_TYPE_DEV_TAB_ERR:
587 dev_err(dev, "DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
588 "address=0x%016llx flags=0x%04x]\n",
589 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
590 address, flags);
591 break;
592 case EVENT_TYPE_PAGE_TAB_ERR:
593 dev_err(dev, "PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
594 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
595 pasid, address, flags);
596 break;
597 case EVENT_TYPE_ILL_CMD:
598 dev_err(dev, "ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
599 dump_command(address);
600 break;
601 case EVENT_TYPE_CMD_HARD_ERR:
602 dev_err(dev, "COMMAND_HARDWARE_ERROR address=0x%016llx flags=0x%04x]\n",
603 address, flags);
604 break;
605 case EVENT_TYPE_IOTLB_INV_TO:
606 dev_err(dev, "IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%016llx]\n",
607 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
608 address);
609 break;
610 case EVENT_TYPE_INV_DEV_REQ:
611 dev_err(dev, "INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
612 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
613 pasid, address, flags);
614 break;
615 case EVENT_TYPE_INV_PPR_REQ:
616 pasid = ((event[0] >> 16) & 0xFFFF)
617 | ((event[1] << 6) & 0xF0000);
618 tag = event[1] & 0x03FF;
619 dev_err(dev, "INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
620 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
621 pasid, address, flags);
622 break;
623 default:
624 dev_err(dev, "UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
625 event[0], event[1], event[2], event[3]);
626 }
627
628 memset(__evt, 0, 4 * sizeof(u32));
629 }
630
631 static void iommu_poll_events(struct amd_iommu *iommu)
632 {
633 u32 head, tail;
634
635 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
636 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
637
638 while (head != tail) {
639 iommu_print_event(iommu, iommu->evt_buf + head);
640 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
641 }
642
643 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
644 }
645
646 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
647 {
648 struct amd_iommu_fault fault;
649
650 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
651 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
652 return;
653 }
654
655 fault.address = raw[1];
656 fault.pasid = PPR_PASID(raw[0]);
657 fault.device_id = PPR_DEVID(raw[0]);
658 fault.tag = PPR_TAG(raw[0]);
659 fault.flags = PPR_FLAGS(raw[0]);
660
661 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
662 }
663
664 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
665 {
666 u32 head, tail;
667
668 if (iommu->ppr_log == NULL)
669 return;
670
671 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
672 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
673
674 while (head != tail) {
675 volatile u64 *raw;
676 u64 entry[2];
677 int i;
678
679 raw = (u64 *)(iommu->ppr_log + head);
680
681 /*
682 * Hardware bug: Interrupt may arrive before the entry is
683 * written to memory. If this happens we need to wait for the
684 * entry to arrive.
685 */
686 for (i = 0; i < LOOP_TIMEOUT; ++i) {
687 if (PPR_REQ_TYPE(raw[0]) != 0)
688 break;
689 udelay(1);
690 }
691
692 /* Avoid memcpy function-call overhead */
693 entry[0] = raw[0];
694 entry[1] = raw[1];
695
696 /*
697 * To detect the hardware bug we need to clear the entry
698 * back to zero.
699 */
700 raw[0] = raw[1] = 0UL;
701
702 /* Update head pointer of hardware ring-buffer */
703 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
704 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
705
706 /* Handle PPR entry */
707 iommu_handle_ppr_entry(iommu, entry);
708
709 /* Refresh ring-buffer information */
710 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
711 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
712 }
713 }
714
715 #ifdef CONFIG_IRQ_REMAP
716 static int (*iommu_ga_log_notifier)(u32);
717
718 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
719 {
720 iommu_ga_log_notifier = notifier;
721
722 return 0;
723 }
724 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
725
726 static void iommu_poll_ga_log(struct amd_iommu *iommu)
727 {
728 u32 head, tail, cnt = 0;
729
730 if (iommu->ga_log == NULL)
731 return;
732
733 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
734 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
735
736 while (head != tail) {
737 volatile u64 *raw;
738 u64 log_entry;
739
740 raw = (u64 *)(iommu->ga_log + head);
741 cnt++;
742
743 /* Avoid memcpy function-call overhead */
744 log_entry = *raw;
745
746 /* Update head pointer of hardware ring-buffer */
747 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
748 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
749
750 /* Handle GA entry */
751 switch (GA_REQ_TYPE(log_entry)) {
752 case GA_GUEST_NR:
753 if (!iommu_ga_log_notifier)
754 break;
755
756 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
757 __func__, GA_DEVID(log_entry),
758 GA_TAG(log_entry));
759
760 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
761 pr_err("AMD-Vi: GA log notifier failed.\n");
762 break;
763 default:
764 break;
765 }
766 }
767 }
768 #endif /* CONFIG_IRQ_REMAP */
769
770 #define AMD_IOMMU_INT_MASK \
771 (MMIO_STATUS_EVT_INT_MASK | \
772 MMIO_STATUS_PPR_INT_MASK | \
773 MMIO_STATUS_GALOG_INT_MASK)
774
775 irqreturn_t amd_iommu_int_thread(int irq, void *data)
776 {
777 struct amd_iommu *iommu = (struct amd_iommu *) data;
778 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
779
780 while (status & AMD_IOMMU_INT_MASK) {
781 /* Enable EVT and PPR and GA interrupts again */
782 writel(AMD_IOMMU_INT_MASK,
783 iommu->mmio_base + MMIO_STATUS_OFFSET);
784
785 if (status & MMIO_STATUS_EVT_INT_MASK) {
786 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
787 iommu_poll_events(iommu);
788 }
789
790 if (status & MMIO_STATUS_PPR_INT_MASK) {
791 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
792 iommu_poll_ppr_log(iommu);
793 }
794
795 #ifdef CONFIG_IRQ_REMAP
796 if (status & MMIO_STATUS_GALOG_INT_MASK) {
797 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
798 iommu_poll_ga_log(iommu);
799 }
800 #endif
801
802 /*
803 * Hardware bug: ERBT1312
804 * When re-enabling interrupt (by writing 1
805 * to clear the bit), the hardware might also try to set
806 * the interrupt bit in the event status register.
807 * In this scenario, the bit will be set, and disable
808 * subsequent interrupts.
809 *
810 * Workaround: The IOMMU driver should read back the
811 * status register and check if the interrupt bits are cleared.
812 * If not, driver will need to go through the interrupt handler
813 * again and re-clear the bits
814 */
815 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
816 }
817 return IRQ_HANDLED;
818 }
819
820 irqreturn_t amd_iommu_int_handler(int irq, void *data)
821 {
822 return IRQ_WAKE_THREAD;
823 }
824
825 /****************************************************************************
826 *
827 * IOMMU command queuing functions
828 *
829 ****************************************************************************/
830
831 static int wait_on_sem(volatile u64 *sem)
832 {
833 int i = 0;
834
835 while (*sem == 0 && i < LOOP_TIMEOUT) {
836 udelay(1);
837 i += 1;
838 }
839
840 if (i == LOOP_TIMEOUT) {
841 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
842 return -EIO;
843 }
844
845 return 0;
846 }
847
848 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
849 struct iommu_cmd *cmd)
850 {
851 u8 *target;
852
853 target = iommu->cmd_buf + iommu->cmd_buf_tail;
854
855 iommu->cmd_buf_tail += sizeof(*cmd);
856 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
857
858 /* Copy command to buffer */
859 memcpy(target, cmd, sizeof(*cmd));
860
861 /* Tell the IOMMU about it */
862 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
863 }
864
865 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
866 {
867 u64 paddr = iommu_virt_to_phys((void *)address);
868
869 WARN_ON(address & 0x7ULL);
870
871 memset(cmd, 0, sizeof(*cmd));
872 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
873 cmd->data[1] = upper_32_bits(paddr);
874 cmd->data[2] = 1;
875 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
876 }
877
878 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
879 {
880 memset(cmd, 0, sizeof(*cmd));
881 cmd->data[0] = devid;
882 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
883 }
884
885 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
886 size_t size, u16 domid, int pde)
887 {
888 u64 pages;
889 bool s;
890
891 pages = iommu_num_pages(address, size, PAGE_SIZE);
892 s = false;
893
894 if (pages > 1) {
895 /*
896 * If we have to flush more than one page, flush all
897 * TLB entries for this domain
898 */
899 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
900 s = true;
901 }
902
903 address &= PAGE_MASK;
904
905 memset(cmd, 0, sizeof(*cmd));
906 cmd->data[1] |= domid;
907 cmd->data[2] = lower_32_bits(address);
908 cmd->data[3] = upper_32_bits(address);
909 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
910 if (s) /* size bit - we flush more than one 4kb page */
911 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
912 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
913 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
914 }
915
916 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
917 u64 address, size_t size)
918 {
919 u64 pages;
920 bool s;
921
922 pages = iommu_num_pages(address, size, PAGE_SIZE);
923 s = false;
924
925 if (pages > 1) {
926 /*
927 * If we have to flush more than one page, flush all
928 * TLB entries for this domain
929 */
930 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
931 s = true;
932 }
933
934 address &= PAGE_MASK;
935
936 memset(cmd, 0, sizeof(*cmd));
937 cmd->data[0] = devid;
938 cmd->data[0] |= (qdep & 0xff) << 24;
939 cmd->data[1] = devid;
940 cmd->data[2] = lower_32_bits(address);
941 cmd->data[3] = upper_32_bits(address);
942 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
943 if (s)
944 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
945 }
946
947 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
948 u64 address, bool size)
949 {
950 memset(cmd, 0, sizeof(*cmd));
951
952 address &= ~(0xfffULL);
953
954 cmd->data[0] = pasid;
955 cmd->data[1] = domid;
956 cmd->data[2] = lower_32_bits(address);
957 cmd->data[3] = upper_32_bits(address);
958 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
959 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
960 if (size)
961 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
962 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
963 }
964
965 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
966 int qdep, u64 address, bool size)
967 {
968 memset(cmd, 0, sizeof(*cmd));
969
970 address &= ~(0xfffULL);
971
972 cmd->data[0] = devid;
973 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
974 cmd->data[0] |= (qdep & 0xff) << 24;
975 cmd->data[1] = devid;
976 cmd->data[1] |= (pasid & 0xff) << 16;
977 cmd->data[2] = lower_32_bits(address);
978 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
979 cmd->data[3] = upper_32_bits(address);
980 if (size)
981 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
982 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
983 }
984
985 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
986 int status, int tag, bool gn)
987 {
988 memset(cmd, 0, sizeof(*cmd));
989
990 cmd->data[0] = devid;
991 if (gn) {
992 cmd->data[1] = pasid;
993 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
994 }
995 cmd->data[3] = tag & 0x1ff;
996 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
997
998 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
999 }
1000
1001 static void build_inv_all(struct iommu_cmd *cmd)
1002 {
1003 memset(cmd, 0, sizeof(*cmd));
1004 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1005 }
1006
1007 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1008 {
1009 memset(cmd, 0, sizeof(*cmd));
1010 cmd->data[0] = devid;
1011 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1012 }
1013
1014 /*
1015 * Writes the command to the IOMMUs command buffer and informs the
1016 * hardware about the new command.
1017 */
1018 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1019 struct iommu_cmd *cmd,
1020 bool sync)
1021 {
1022 unsigned int count = 0;
1023 u32 left, next_tail;
1024
1025 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1026 again:
1027 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1028
1029 if (left <= 0x20) {
1030 /* Skip udelay() the first time around */
1031 if (count++) {
1032 if (count == LOOP_TIMEOUT) {
1033 pr_err("AMD-Vi: Command buffer timeout\n");
1034 return -EIO;
1035 }
1036
1037 udelay(1);
1038 }
1039
1040 /* Update head and recheck remaining space */
1041 iommu->cmd_buf_head = readl(iommu->mmio_base +
1042 MMIO_CMD_HEAD_OFFSET);
1043
1044 goto again;
1045 }
1046
1047 copy_cmd_to_buffer(iommu, cmd);
1048
1049 /* Do we need to make sure all commands are processed? */
1050 iommu->need_sync = sync;
1051
1052 return 0;
1053 }
1054
1055 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1056 struct iommu_cmd *cmd,
1057 bool sync)
1058 {
1059 unsigned long flags;
1060 int ret;
1061
1062 raw_spin_lock_irqsave(&iommu->lock, flags);
1063 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1064 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1065
1066 return ret;
1067 }
1068
1069 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1070 {
1071 return iommu_queue_command_sync(iommu, cmd, true);
1072 }
1073
1074 /*
1075 * This function queues a completion wait command into the command
1076 * buffer of an IOMMU
1077 */
1078 static int iommu_completion_wait(struct amd_iommu *iommu)
1079 {
1080 struct iommu_cmd cmd;
1081 unsigned long flags;
1082 int ret;
1083
1084 if (!iommu->need_sync)
1085 return 0;
1086
1087
1088 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1089
1090 raw_spin_lock_irqsave(&iommu->lock, flags);
1091
1092 iommu->cmd_sem = 0;
1093
1094 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1095 if (ret)
1096 goto out_unlock;
1097
1098 ret = wait_on_sem(&iommu->cmd_sem);
1099
1100 out_unlock:
1101 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1102
1103 return ret;
1104 }
1105
1106 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1107 {
1108 struct iommu_cmd cmd;
1109
1110 build_inv_dte(&cmd, devid);
1111
1112 return iommu_queue_command(iommu, &cmd);
1113 }
1114
1115 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1116 {
1117 u32 devid;
1118
1119 for (devid = 0; devid <= 0xffff; ++devid)
1120 iommu_flush_dte(iommu, devid);
1121
1122 iommu_completion_wait(iommu);
1123 }
1124
1125 /*
1126 * This function uses heavy locking and may disable irqs for some time. But
1127 * this is no issue because it is only called during resume.
1128 */
1129 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1130 {
1131 u32 dom_id;
1132
1133 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1134 struct iommu_cmd cmd;
1135 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1136 dom_id, 1);
1137 iommu_queue_command(iommu, &cmd);
1138 }
1139
1140 iommu_completion_wait(iommu);
1141 }
1142
1143 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1144 {
1145 struct iommu_cmd cmd;
1146
1147 build_inv_all(&cmd);
1148
1149 iommu_queue_command(iommu, &cmd);
1150 iommu_completion_wait(iommu);
1151 }
1152
1153 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1154 {
1155 struct iommu_cmd cmd;
1156
1157 build_inv_irt(&cmd, devid);
1158
1159 iommu_queue_command(iommu, &cmd);
1160 }
1161
1162 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1163 {
1164 u32 devid;
1165
1166 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1167 iommu_flush_irt(iommu, devid);
1168
1169 iommu_completion_wait(iommu);
1170 }
1171
1172 void iommu_flush_all_caches(struct amd_iommu *iommu)
1173 {
1174 if (iommu_feature(iommu, FEATURE_IA)) {
1175 amd_iommu_flush_all(iommu);
1176 } else {
1177 amd_iommu_flush_dte_all(iommu);
1178 amd_iommu_flush_irt_all(iommu);
1179 amd_iommu_flush_tlb_all(iommu);
1180 }
1181 }
1182
1183 /*
1184 * Command send function for flushing on-device TLB
1185 */
1186 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1187 u64 address, size_t size)
1188 {
1189 struct amd_iommu *iommu;
1190 struct iommu_cmd cmd;
1191 int qdep;
1192
1193 qdep = dev_data->ats.qdep;
1194 iommu = amd_iommu_rlookup_table[dev_data->devid];
1195
1196 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1197
1198 return iommu_queue_command(iommu, &cmd);
1199 }
1200
1201 /*
1202 * Command send function for invalidating a device table entry
1203 */
1204 static int device_flush_dte(struct iommu_dev_data *dev_data)
1205 {
1206 struct amd_iommu *iommu;
1207 u16 alias;
1208 int ret;
1209
1210 iommu = amd_iommu_rlookup_table[dev_data->devid];
1211 alias = dev_data->alias;
1212
1213 ret = iommu_flush_dte(iommu, dev_data->devid);
1214 if (!ret && alias != dev_data->devid)
1215 ret = iommu_flush_dte(iommu, alias);
1216 if (ret)
1217 return ret;
1218
1219 if (dev_data->ats.enabled)
1220 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1221
1222 return ret;
1223 }
1224
1225 /*
1226 * TLB invalidation function which is called from the mapping functions.
1227 * It invalidates a single PTE if the range to flush is within a single
1228 * page. Otherwise it flushes the whole TLB of the IOMMU.
1229 */
1230 static void __domain_flush_pages(struct protection_domain *domain,
1231 u64 address, size_t size, int pde)
1232 {
1233 struct iommu_dev_data *dev_data;
1234 struct iommu_cmd cmd;
1235 int ret = 0, i;
1236
1237 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1238
1239 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1240 if (!domain->dev_iommu[i])
1241 continue;
1242
1243 /*
1244 * Devices of this domain are behind this IOMMU
1245 * We need a TLB flush
1246 */
1247 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1248 }
1249
1250 list_for_each_entry(dev_data, &domain->dev_list, list) {
1251
1252 if (!dev_data->ats.enabled)
1253 continue;
1254
1255 ret |= device_flush_iotlb(dev_data, address, size);
1256 }
1257
1258 WARN_ON(ret);
1259 }
1260
1261 static void domain_flush_pages(struct protection_domain *domain,
1262 u64 address, size_t size)
1263 {
1264 __domain_flush_pages(domain, address, size, 0);
1265 }
1266
1267 /* Flush the whole IO/TLB for a given protection domain */
1268 static void domain_flush_tlb(struct protection_domain *domain)
1269 {
1270 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1271 }
1272
1273 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1274 static void domain_flush_tlb_pde(struct protection_domain *domain)
1275 {
1276 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1277 }
1278
1279 static void domain_flush_complete(struct protection_domain *domain)
1280 {
1281 int i;
1282
1283 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1284 if (domain && !domain->dev_iommu[i])
1285 continue;
1286
1287 /*
1288 * Devices of this domain are behind this IOMMU
1289 * We need to wait for completion of all commands.
1290 */
1291 iommu_completion_wait(amd_iommus[i]);
1292 }
1293 }
1294
1295
1296 /*
1297 * This function flushes the DTEs for all devices in domain
1298 */
1299 static void domain_flush_devices(struct protection_domain *domain)
1300 {
1301 struct iommu_dev_data *dev_data;
1302
1303 list_for_each_entry(dev_data, &domain->dev_list, list)
1304 device_flush_dte(dev_data);
1305 }
1306
1307 /****************************************************************************
1308 *
1309 * The functions below are used the create the page table mappings for
1310 * unity mapped regions.
1311 *
1312 ****************************************************************************/
1313
1314 /*
1315 * This function is used to add another level to an IO page table. Adding
1316 * another level increases the size of the address space by 9 bits to a size up
1317 * to 64 bits.
1318 */
1319 static bool increase_address_space(struct protection_domain *domain,
1320 gfp_t gfp)
1321 {
1322 u64 *pte;
1323
1324 if (domain->mode == PAGE_MODE_6_LEVEL)
1325 /* address space already 64 bit large */
1326 return false;
1327
1328 pte = (void *)get_zeroed_page(gfp);
1329 if (!pte)
1330 return false;
1331
1332 *pte = PM_LEVEL_PDE(domain->mode,
1333 iommu_virt_to_phys(domain->pt_root));
1334 domain->pt_root = pte;
1335 domain->mode += 1;
1336 domain->updated = true;
1337
1338 return true;
1339 }
1340
1341 static u64 *alloc_pte(struct protection_domain *domain,
1342 unsigned long address,
1343 unsigned long page_size,
1344 u64 **pte_page,
1345 gfp_t gfp)
1346 {
1347 int level, end_lvl;
1348 u64 *pte, *page;
1349
1350 BUG_ON(!is_power_of_2(page_size));
1351
1352 while (address > PM_LEVEL_SIZE(domain->mode))
1353 increase_address_space(domain, gfp);
1354
1355 level = domain->mode - 1;
1356 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1357 address = PAGE_SIZE_ALIGN(address, page_size);
1358 end_lvl = PAGE_SIZE_LEVEL(page_size);
1359
1360 while (level > end_lvl) {
1361 u64 __pte, __npte;
1362
1363 __pte = *pte;
1364
1365 if (!IOMMU_PTE_PRESENT(__pte)) {
1366 page = (u64 *)get_zeroed_page(gfp);
1367 if (!page)
1368 return NULL;
1369
1370 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1371
1372 /* pte could have been changed somewhere. */
1373 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1374 free_page((unsigned long)page);
1375 continue;
1376 }
1377 }
1378
1379 /* No level skipping support yet */
1380 if (PM_PTE_LEVEL(*pte) != level)
1381 return NULL;
1382
1383 level -= 1;
1384
1385 pte = IOMMU_PTE_PAGE(*pte);
1386
1387 if (pte_page && level == end_lvl)
1388 *pte_page = pte;
1389
1390 pte = &pte[PM_LEVEL_INDEX(level, address)];
1391 }
1392
1393 return pte;
1394 }
1395
1396 /*
1397 * This function checks if there is a PTE for a given dma address. If
1398 * there is one, it returns the pointer to it.
1399 */
1400 static u64 *fetch_pte(struct protection_domain *domain,
1401 unsigned long address,
1402 unsigned long *page_size)
1403 {
1404 int level;
1405 u64 *pte;
1406
1407 if (address > PM_LEVEL_SIZE(domain->mode))
1408 return NULL;
1409
1410 level = domain->mode - 1;
1411 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1412 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1413
1414 while (level > 0) {
1415
1416 /* Not Present */
1417 if (!IOMMU_PTE_PRESENT(*pte))
1418 return NULL;
1419
1420 /* Large PTE */
1421 if (PM_PTE_LEVEL(*pte) == 7 ||
1422 PM_PTE_LEVEL(*pte) == 0)
1423 break;
1424
1425 /* No level skipping support yet */
1426 if (PM_PTE_LEVEL(*pte) != level)
1427 return NULL;
1428
1429 level -= 1;
1430
1431 /* Walk to the next level */
1432 pte = IOMMU_PTE_PAGE(*pte);
1433 pte = &pte[PM_LEVEL_INDEX(level, address)];
1434 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1435 }
1436
1437 if (PM_PTE_LEVEL(*pte) == 0x07) {
1438 unsigned long pte_mask;
1439
1440 /*
1441 * If we have a series of large PTEs, make
1442 * sure to return a pointer to the first one.
1443 */
1444 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1445 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1446 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1447 }
1448
1449 return pte;
1450 }
1451
1452 /*
1453 * Generic mapping functions. It maps a physical address into a DMA
1454 * address space. It allocates the page table pages if necessary.
1455 * In the future it can be extended to a generic mapping function
1456 * supporting all features of AMD IOMMU page tables like level skipping
1457 * and full 64 bit address spaces.
1458 */
1459 static int iommu_map_page(struct protection_domain *dom,
1460 unsigned long bus_addr,
1461 unsigned long phys_addr,
1462 unsigned long page_size,
1463 int prot,
1464 gfp_t gfp)
1465 {
1466 u64 __pte, *pte;
1467 int i, count;
1468
1469 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1470 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1471
1472 if (!(prot & IOMMU_PROT_MASK))
1473 return -EINVAL;
1474
1475 count = PAGE_SIZE_PTE_COUNT(page_size);
1476 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1477
1478 if (!pte)
1479 return -ENOMEM;
1480
1481 for (i = 0; i < count; ++i)
1482 if (IOMMU_PTE_PRESENT(pte[i]))
1483 return -EBUSY;
1484
1485 if (count > 1) {
1486 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1487 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1488 } else
1489 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1490
1491 if (prot & IOMMU_PROT_IR)
1492 __pte |= IOMMU_PTE_IR;
1493 if (prot & IOMMU_PROT_IW)
1494 __pte |= IOMMU_PTE_IW;
1495
1496 for (i = 0; i < count; ++i)
1497 pte[i] = __pte;
1498
1499 update_domain(dom);
1500
1501 return 0;
1502 }
1503
1504 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1505 unsigned long bus_addr,
1506 unsigned long page_size)
1507 {
1508 unsigned long long unmapped;
1509 unsigned long unmap_size;
1510 u64 *pte;
1511
1512 BUG_ON(!is_power_of_2(page_size));
1513
1514 unmapped = 0;
1515
1516 while (unmapped < page_size) {
1517
1518 pte = fetch_pte(dom, bus_addr, &unmap_size);
1519
1520 if (pte) {
1521 int i, count;
1522
1523 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1524 for (i = 0; i < count; i++)
1525 pte[i] = 0ULL;
1526 }
1527
1528 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1529 unmapped += unmap_size;
1530 }
1531
1532 BUG_ON(unmapped && !is_power_of_2(unmapped));
1533
1534 return unmapped;
1535 }
1536
1537 /****************************************************************************
1538 *
1539 * The next functions belong to the address allocator for the dma_ops
1540 * interface functions.
1541 *
1542 ****************************************************************************/
1543
1544
1545 static unsigned long dma_ops_alloc_iova(struct device *dev,
1546 struct dma_ops_domain *dma_dom,
1547 unsigned int pages, u64 dma_mask)
1548 {
1549 unsigned long pfn = 0;
1550
1551 pages = __roundup_pow_of_two(pages);
1552
1553 if (dma_mask > DMA_BIT_MASK(32))
1554 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1555 IOVA_PFN(DMA_BIT_MASK(32)), false);
1556
1557 if (!pfn)
1558 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1559 IOVA_PFN(dma_mask), true);
1560
1561 return (pfn << PAGE_SHIFT);
1562 }
1563
1564 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1565 unsigned long address,
1566 unsigned int pages)
1567 {
1568 pages = __roundup_pow_of_two(pages);
1569 address >>= PAGE_SHIFT;
1570
1571 free_iova_fast(&dma_dom->iovad, address, pages);
1572 }
1573
1574 /****************************************************************************
1575 *
1576 * The next functions belong to the domain allocation. A domain is
1577 * allocated for every IOMMU as the default domain. If device isolation
1578 * is enabled, every device get its own domain. The most important thing
1579 * about domains is the page table mapping the DMA address space they
1580 * contain.
1581 *
1582 ****************************************************************************/
1583
1584 /*
1585 * This function adds a protection domain to the global protection domain list
1586 */
1587 static void add_domain_to_list(struct protection_domain *domain)
1588 {
1589 unsigned long flags;
1590
1591 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1592 list_add(&domain->list, &amd_iommu_pd_list);
1593 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1594 }
1595
1596 /*
1597 * This function removes a protection domain to the global
1598 * protection domain list
1599 */
1600 static void del_domain_from_list(struct protection_domain *domain)
1601 {
1602 unsigned long flags;
1603
1604 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1605 list_del(&domain->list);
1606 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1607 }
1608
1609 static u16 domain_id_alloc(void)
1610 {
1611 int id;
1612
1613 spin_lock(&pd_bitmap_lock);
1614 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1615 BUG_ON(id == 0);
1616 if (id > 0 && id < MAX_DOMAIN_ID)
1617 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1618 else
1619 id = 0;
1620 spin_unlock(&pd_bitmap_lock);
1621
1622 return id;
1623 }
1624
1625 static void domain_id_free(int id)
1626 {
1627 spin_lock(&pd_bitmap_lock);
1628 if (id > 0 && id < MAX_DOMAIN_ID)
1629 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1630 spin_unlock(&pd_bitmap_lock);
1631 }
1632
1633 #define DEFINE_FREE_PT_FN(LVL, FN) \
1634 static void free_pt_##LVL (unsigned long __pt) \
1635 { \
1636 unsigned long p; \
1637 u64 *pt; \
1638 int i; \
1639 \
1640 pt = (u64 *)__pt; \
1641 \
1642 for (i = 0; i < 512; ++i) { \
1643 /* PTE present? */ \
1644 if (!IOMMU_PTE_PRESENT(pt[i])) \
1645 continue; \
1646 \
1647 /* Large PTE? */ \
1648 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1649 PM_PTE_LEVEL(pt[i]) == 7) \
1650 continue; \
1651 \
1652 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1653 FN(p); \
1654 } \
1655 free_page((unsigned long)pt); \
1656 }
1657
1658 DEFINE_FREE_PT_FN(l2, free_page)
1659 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1660 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1661 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1662 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1663
1664 static void free_pagetable(struct protection_domain *domain)
1665 {
1666 unsigned long root = (unsigned long)domain->pt_root;
1667
1668 switch (domain->mode) {
1669 case PAGE_MODE_NONE:
1670 break;
1671 case PAGE_MODE_1_LEVEL:
1672 free_page(root);
1673 break;
1674 case PAGE_MODE_2_LEVEL:
1675 free_pt_l2(root);
1676 break;
1677 case PAGE_MODE_3_LEVEL:
1678 free_pt_l3(root);
1679 break;
1680 case PAGE_MODE_4_LEVEL:
1681 free_pt_l4(root);
1682 break;
1683 case PAGE_MODE_5_LEVEL:
1684 free_pt_l5(root);
1685 break;
1686 case PAGE_MODE_6_LEVEL:
1687 free_pt_l6(root);
1688 break;
1689 default:
1690 BUG();
1691 }
1692 }
1693
1694 static void free_gcr3_tbl_level1(u64 *tbl)
1695 {
1696 u64 *ptr;
1697 int i;
1698
1699 for (i = 0; i < 512; ++i) {
1700 if (!(tbl[i] & GCR3_VALID))
1701 continue;
1702
1703 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1704
1705 free_page((unsigned long)ptr);
1706 }
1707 }
1708
1709 static void free_gcr3_tbl_level2(u64 *tbl)
1710 {
1711 u64 *ptr;
1712 int i;
1713
1714 for (i = 0; i < 512; ++i) {
1715 if (!(tbl[i] & GCR3_VALID))
1716 continue;
1717
1718 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1719
1720 free_gcr3_tbl_level1(ptr);
1721 }
1722 }
1723
1724 static void free_gcr3_table(struct protection_domain *domain)
1725 {
1726 if (domain->glx == 2)
1727 free_gcr3_tbl_level2(domain->gcr3_tbl);
1728 else if (domain->glx == 1)
1729 free_gcr3_tbl_level1(domain->gcr3_tbl);
1730 else
1731 BUG_ON(domain->glx != 0);
1732
1733 free_page((unsigned long)domain->gcr3_tbl);
1734 }
1735
1736 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1737 {
1738 domain_flush_tlb(&dom->domain);
1739 domain_flush_complete(&dom->domain);
1740 }
1741
1742 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1743 {
1744 struct dma_ops_domain *dom;
1745
1746 dom = container_of(iovad, struct dma_ops_domain, iovad);
1747
1748 dma_ops_domain_flush_tlb(dom);
1749 }
1750
1751 /*
1752 * Free a domain, only used if something went wrong in the
1753 * allocation path and we need to free an already allocated page table
1754 */
1755 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1756 {
1757 if (!dom)
1758 return;
1759
1760 del_domain_from_list(&dom->domain);
1761
1762 put_iova_domain(&dom->iovad);
1763
1764 free_pagetable(&dom->domain);
1765
1766 if (dom->domain.id)
1767 domain_id_free(dom->domain.id);
1768
1769 kfree(dom);
1770 }
1771
1772 /*
1773 * Allocates a new protection domain usable for the dma_ops functions.
1774 * It also initializes the page table and the address allocator data
1775 * structures required for the dma_ops interface
1776 */
1777 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1778 {
1779 struct dma_ops_domain *dma_dom;
1780
1781 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1782 if (!dma_dom)
1783 return NULL;
1784
1785 if (protection_domain_init(&dma_dom->domain))
1786 goto free_dma_dom;
1787
1788 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1789 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1790 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1791 if (!dma_dom->domain.pt_root)
1792 goto free_dma_dom;
1793
1794 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1795
1796 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1797 goto free_dma_dom;
1798
1799 /* Initialize reserved ranges */
1800 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1801
1802 add_domain_to_list(&dma_dom->domain);
1803
1804 return dma_dom;
1805
1806 free_dma_dom:
1807 dma_ops_domain_free(dma_dom);
1808
1809 return NULL;
1810 }
1811
1812 /*
1813 * little helper function to check whether a given protection domain is a
1814 * dma_ops domain
1815 */
1816 static bool dma_ops_domain(struct protection_domain *domain)
1817 {
1818 return domain->flags & PD_DMA_OPS_MASK;
1819 }
1820
1821 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1822 bool ats, bool ppr)
1823 {
1824 u64 pte_root = 0;
1825 u64 flags = 0;
1826
1827 if (domain->mode != PAGE_MODE_NONE)
1828 pte_root = iommu_virt_to_phys(domain->pt_root);
1829
1830 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1831 << DEV_ENTRY_MODE_SHIFT;
1832 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1833
1834 flags = amd_iommu_dev_table[devid].data[1];
1835
1836 if (ats)
1837 flags |= DTE_FLAG_IOTLB;
1838
1839 if (ppr) {
1840 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1841
1842 if (iommu_feature(iommu, FEATURE_EPHSUP))
1843 pte_root |= 1ULL << DEV_ENTRY_PPR;
1844 }
1845
1846 if (domain->flags & PD_IOMMUV2_MASK) {
1847 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1848 u64 glx = domain->glx;
1849 u64 tmp;
1850
1851 pte_root |= DTE_FLAG_GV;
1852 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1853
1854 /* First mask out possible old values for GCR3 table */
1855 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1856 flags &= ~tmp;
1857
1858 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1859 flags &= ~tmp;
1860
1861 /* Encode GCR3 table into DTE */
1862 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1863 pte_root |= tmp;
1864
1865 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1866 flags |= tmp;
1867
1868 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1869 flags |= tmp;
1870 }
1871
1872 flags &= ~DEV_DOMID_MASK;
1873 flags |= domain->id;
1874
1875 amd_iommu_dev_table[devid].data[1] = flags;
1876 amd_iommu_dev_table[devid].data[0] = pte_root;
1877 }
1878
1879 static void clear_dte_entry(u16 devid)
1880 {
1881 /* remove entry from the device table seen by the hardware */
1882 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1883 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1884
1885 amd_iommu_apply_erratum_63(devid);
1886 }
1887
1888 static void do_attach(struct iommu_dev_data *dev_data,
1889 struct protection_domain *domain)
1890 {
1891 struct amd_iommu *iommu;
1892 u16 alias;
1893 bool ats;
1894
1895 iommu = amd_iommu_rlookup_table[dev_data->devid];
1896 alias = dev_data->alias;
1897 ats = dev_data->ats.enabled;
1898
1899 /* Update data structures */
1900 dev_data->domain = domain;
1901 list_add(&dev_data->list, &domain->dev_list);
1902
1903 /* Do reference counting */
1904 domain->dev_iommu[iommu->index] += 1;
1905 domain->dev_cnt += 1;
1906
1907 /* Update device table */
1908 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1909 if (alias != dev_data->devid)
1910 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1911
1912 device_flush_dte(dev_data);
1913 }
1914
1915 static void do_detach(struct iommu_dev_data *dev_data)
1916 {
1917 struct amd_iommu *iommu;
1918 u16 alias;
1919
1920 iommu = amd_iommu_rlookup_table[dev_data->devid];
1921 alias = dev_data->alias;
1922
1923 /* decrease reference counters */
1924 dev_data->domain->dev_iommu[iommu->index] -= 1;
1925 dev_data->domain->dev_cnt -= 1;
1926
1927 /* Update data structures */
1928 dev_data->domain = NULL;
1929 list_del(&dev_data->list);
1930 clear_dte_entry(dev_data->devid);
1931 if (alias != dev_data->devid)
1932 clear_dte_entry(alias);
1933
1934 /* Flush the DTE entry */
1935 device_flush_dte(dev_data);
1936 }
1937
1938 /*
1939 * If a device is not yet associated with a domain, this function makes the
1940 * device visible in the domain
1941 */
1942 static int __attach_device(struct iommu_dev_data *dev_data,
1943 struct protection_domain *domain)
1944 {
1945 int ret;
1946
1947 /*
1948 * Must be called with IRQs disabled. Warn here to detect early
1949 * when its not.
1950 */
1951 WARN_ON(!irqs_disabled());
1952
1953 /* lock domain */
1954 spin_lock(&domain->lock);
1955
1956 ret = -EBUSY;
1957 if (dev_data->domain != NULL)
1958 goto out_unlock;
1959
1960 /* Attach alias group root */
1961 do_attach(dev_data, domain);
1962
1963 ret = 0;
1964
1965 out_unlock:
1966
1967 /* ready */
1968 spin_unlock(&domain->lock);
1969
1970 return ret;
1971 }
1972
1973
1974 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1975 {
1976 pci_disable_ats(pdev);
1977 pci_disable_pri(pdev);
1978 pci_disable_pasid(pdev);
1979 }
1980
1981 /* FIXME: Change generic reset-function to do the same */
1982 static int pri_reset_while_enabled(struct pci_dev *pdev)
1983 {
1984 u16 control;
1985 int pos;
1986
1987 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1988 if (!pos)
1989 return -EINVAL;
1990
1991 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1992 control |= PCI_PRI_CTRL_RESET;
1993 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1994
1995 return 0;
1996 }
1997
1998 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1999 {
2000 bool reset_enable;
2001 int reqs, ret;
2002
2003 /* FIXME: Hardcode number of outstanding requests for now */
2004 reqs = 32;
2005 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2006 reqs = 1;
2007 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2008
2009 /* Only allow access to user-accessible pages */
2010 ret = pci_enable_pasid(pdev, 0);
2011 if (ret)
2012 goto out_err;
2013
2014 /* First reset the PRI state of the device */
2015 ret = pci_reset_pri(pdev);
2016 if (ret)
2017 goto out_err;
2018
2019 /* Enable PRI */
2020 ret = pci_enable_pri(pdev, reqs);
2021 if (ret)
2022 goto out_err;
2023
2024 if (reset_enable) {
2025 ret = pri_reset_while_enabled(pdev);
2026 if (ret)
2027 goto out_err;
2028 }
2029
2030 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2031 if (ret)
2032 goto out_err;
2033
2034 return 0;
2035
2036 out_err:
2037 pci_disable_pri(pdev);
2038 pci_disable_pasid(pdev);
2039
2040 return ret;
2041 }
2042
2043 /* FIXME: Move this to PCI code */
2044 #define PCI_PRI_TLP_OFF (1 << 15)
2045
2046 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2047 {
2048 u16 status;
2049 int pos;
2050
2051 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2052 if (!pos)
2053 return false;
2054
2055 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2056
2057 return (status & PCI_PRI_TLP_OFF) ? true : false;
2058 }
2059
2060 /*
2061 * If a device is not yet associated with a domain, this function makes the
2062 * device visible in the domain
2063 */
2064 static int attach_device(struct device *dev,
2065 struct protection_domain *domain)
2066 {
2067 struct pci_dev *pdev;
2068 struct iommu_dev_data *dev_data;
2069 unsigned long flags;
2070 int ret;
2071
2072 dev_data = get_dev_data(dev);
2073
2074 if (!dev_is_pci(dev))
2075 goto skip_ats_check;
2076
2077 pdev = to_pci_dev(dev);
2078 if (domain->flags & PD_IOMMUV2_MASK) {
2079 if (!dev_data->passthrough)
2080 return -EINVAL;
2081
2082 if (dev_data->iommu_v2) {
2083 if (pdev_iommuv2_enable(pdev) != 0)
2084 return -EINVAL;
2085
2086 dev_data->ats.enabled = true;
2087 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2088 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2089 }
2090 } else if (amd_iommu_iotlb_sup &&
2091 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2092 dev_data->ats.enabled = true;
2093 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2094 }
2095
2096 skip_ats_check:
2097 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2098 ret = __attach_device(dev_data, domain);
2099 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2100
2101 /*
2102 * We might boot into a crash-kernel here. The crashed kernel
2103 * left the caches in the IOMMU dirty. So we have to flush
2104 * here to evict all dirty stuff.
2105 */
2106 domain_flush_tlb_pde(domain);
2107
2108 return ret;
2109 }
2110
2111 /*
2112 * Removes a device from a protection domain (unlocked)
2113 */
2114 static void __detach_device(struct iommu_dev_data *dev_data)
2115 {
2116 struct protection_domain *domain;
2117
2118 /*
2119 * Must be called with IRQs disabled. Warn here to detect early
2120 * when its not.
2121 */
2122 WARN_ON(!irqs_disabled());
2123
2124 domain = dev_data->domain;
2125
2126 spin_lock(&domain->lock);
2127
2128 do_detach(dev_data);
2129
2130 spin_unlock(&domain->lock);
2131 }
2132
2133 /*
2134 * Removes a device from a protection domain (with devtable_lock held)
2135 */
2136 static void detach_device(struct device *dev)
2137 {
2138 struct protection_domain *domain;
2139 struct iommu_dev_data *dev_data;
2140 unsigned long flags;
2141
2142 dev_data = get_dev_data(dev);
2143 domain = dev_data->domain;
2144
2145 /*
2146 * First check if the device is still attached. It might already
2147 * be detached from its domain because the generic
2148 * iommu_detach_group code detached it and we try again here in
2149 * our alias handling.
2150 */
2151 if (WARN_ON(!dev_data->domain))
2152 return;
2153
2154 /* lock device table */
2155 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2156 __detach_device(dev_data);
2157 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2158
2159 if (!dev_is_pci(dev))
2160 return;
2161
2162 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2163 pdev_iommuv2_disable(to_pci_dev(dev));
2164 else if (dev_data->ats.enabled)
2165 pci_disable_ats(to_pci_dev(dev));
2166
2167 dev_data->ats.enabled = false;
2168 }
2169
2170 static int amd_iommu_add_device(struct device *dev)
2171 {
2172 struct iommu_dev_data *dev_data;
2173 struct iommu_domain *domain;
2174 struct amd_iommu *iommu;
2175 int ret, devid;
2176
2177 if (!check_device(dev) || get_dev_data(dev))
2178 return 0;
2179
2180 devid = get_device_id(dev);
2181 if (devid < 0)
2182 return devid;
2183
2184 iommu = amd_iommu_rlookup_table[devid];
2185
2186 ret = iommu_init_device(dev);
2187 if (ret) {
2188 if (ret != -ENOTSUPP)
2189 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2190 dev_name(dev));
2191
2192 iommu_ignore_device(dev);
2193 dev->dma_ops = &dma_direct_ops;
2194 goto out;
2195 }
2196 init_iommu_group(dev);
2197
2198 dev_data = get_dev_data(dev);
2199
2200 BUG_ON(!dev_data);
2201
2202 if (iommu_pass_through || dev_data->iommu_v2)
2203 iommu_request_dm_for_dev(dev);
2204
2205 /* Domains are initialized for this device - have a look what we ended up with */
2206 domain = iommu_get_domain_for_dev(dev);
2207 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2208 dev_data->passthrough = true;
2209 else
2210 dev->dma_ops = &amd_iommu_dma_ops;
2211
2212 out:
2213 iommu_completion_wait(iommu);
2214
2215 return 0;
2216 }
2217
2218 static void amd_iommu_remove_device(struct device *dev)
2219 {
2220 struct amd_iommu *iommu;
2221 int devid;
2222
2223 if (!check_device(dev))
2224 return;
2225
2226 devid = get_device_id(dev);
2227 if (devid < 0)
2228 return;
2229
2230 iommu = amd_iommu_rlookup_table[devid];
2231
2232 iommu_uninit_device(dev);
2233 iommu_completion_wait(iommu);
2234 }
2235
2236 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2237 {
2238 if (dev_is_pci(dev))
2239 return pci_device_group(dev);
2240
2241 return acpihid_device_group(dev);
2242 }
2243
2244 /*****************************************************************************
2245 *
2246 * The next functions belong to the dma_ops mapping/unmapping code.
2247 *
2248 *****************************************************************************/
2249
2250 /*
2251 * In the dma_ops path we only have the struct device. This function
2252 * finds the corresponding IOMMU, the protection domain and the
2253 * requestor id for a given device.
2254 * If the device is not yet associated with a domain this is also done
2255 * in this function.
2256 */
2257 static struct protection_domain *get_domain(struct device *dev)
2258 {
2259 struct protection_domain *domain;
2260 struct iommu_domain *io_domain;
2261
2262 if (!check_device(dev))
2263 return ERR_PTR(-EINVAL);
2264
2265 domain = get_dev_data(dev)->domain;
2266 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2267 get_dev_data(dev)->defer_attach = false;
2268 io_domain = iommu_get_domain_for_dev(dev);
2269 domain = to_pdomain(io_domain);
2270 attach_device(dev, domain);
2271 }
2272 if (domain == NULL)
2273 return ERR_PTR(-EBUSY);
2274
2275 if (!dma_ops_domain(domain))
2276 return ERR_PTR(-EBUSY);
2277
2278 return domain;
2279 }
2280
2281 static void update_device_table(struct protection_domain *domain)
2282 {
2283 struct iommu_dev_data *dev_data;
2284
2285 list_for_each_entry(dev_data, &domain->dev_list, list) {
2286 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2287 dev_data->iommu_v2);
2288
2289 if (dev_data->devid == dev_data->alias)
2290 continue;
2291
2292 /* There is an alias, update device table entry for it */
2293 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2294 dev_data->iommu_v2);
2295 }
2296 }
2297
2298 static void update_domain(struct protection_domain *domain)
2299 {
2300 if (!domain->updated)
2301 return;
2302
2303 update_device_table(domain);
2304
2305 domain_flush_devices(domain);
2306 domain_flush_tlb_pde(domain);
2307
2308 domain->updated = false;
2309 }
2310
2311 static int dir2prot(enum dma_data_direction direction)
2312 {
2313 if (direction == DMA_TO_DEVICE)
2314 return IOMMU_PROT_IR;
2315 else if (direction == DMA_FROM_DEVICE)
2316 return IOMMU_PROT_IW;
2317 else if (direction == DMA_BIDIRECTIONAL)
2318 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2319 else
2320 return 0;
2321 }
2322
2323 /*
2324 * This function contains common code for mapping of a physically
2325 * contiguous memory region into DMA address space. It is used by all
2326 * mapping functions provided with this IOMMU driver.
2327 * Must be called with the domain lock held.
2328 */
2329 static dma_addr_t __map_single(struct device *dev,
2330 struct dma_ops_domain *dma_dom,
2331 phys_addr_t paddr,
2332 size_t size,
2333 enum dma_data_direction direction,
2334 u64 dma_mask)
2335 {
2336 dma_addr_t offset = paddr & ~PAGE_MASK;
2337 dma_addr_t address, start, ret;
2338 unsigned int pages;
2339 int prot = 0;
2340 int i;
2341
2342 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2343 paddr &= PAGE_MASK;
2344
2345 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2346 if (address == AMD_IOMMU_MAPPING_ERROR)
2347 goto out;
2348
2349 prot = dir2prot(direction);
2350
2351 start = address;
2352 for (i = 0; i < pages; ++i) {
2353 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2354 PAGE_SIZE, prot, GFP_ATOMIC);
2355 if (ret)
2356 goto out_unmap;
2357
2358 paddr += PAGE_SIZE;
2359 start += PAGE_SIZE;
2360 }
2361 address += offset;
2362
2363 if (unlikely(amd_iommu_np_cache)) {
2364 domain_flush_pages(&dma_dom->domain, address, size);
2365 domain_flush_complete(&dma_dom->domain);
2366 }
2367
2368 out:
2369 return address;
2370
2371 out_unmap:
2372
2373 for (--i; i >= 0; --i) {
2374 start -= PAGE_SIZE;
2375 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2376 }
2377
2378 domain_flush_tlb(&dma_dom->domain);
2379 domain_flush_complete(&dma_dom->domain);
2380
2381 dma_ops_free_iova(dma_dom, address, pages);
2382
2383 return AMD_IOMMU_MAPPING_ERROR;
2384 }
2385
2386 /*
2387 * Does the reverse of the __map_single function. Must be called with
2388 * the domain lock held too
2389 */
2390 static void __unmap_single(struct dma_ops_domain *dma_dom,
2391 dma_addr_t dma_addr,
2392 size_t size,
2393 int dir)
2394 {
2395 dma_addr_t i, start;
2396 unsigned int pages;
2397
2398 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2399 dma_addr &= PAGE_MASK;
2400 start = dma_addr;
2401
2402 for (i = 0; i < pages; ++i) {
2403 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2404 start += PAGE_SIZE;
2405 }
2406
2407 if (amd_iommu_unmap_flush) {
2408 dma_ops_free_iova(dma_dom, dma_addr, pages);
2409 domain_flush_tlb(&dma_dom->domain);
2410 domain_flush_complete(&dma_dom->domain);
2411 } else {
2412 pages = __roundup_pow_of_two(pages);
2413 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2414 }
2415 }
2416
2417 /*
2418 * The exported map_single function for dma_ops.
2419 */
2420 static dma_addr_t map_page(struct device *dev, struct page *page,
2421 unsigned long offset, size_t size,
2422 enum dma_data_direction dir,
2423 unsigned long attrs)
2424 {
2425 phys_addr_t paddr = page_to_phys(page) + offset;
2426 struct protection_domain *domain;
2427 struct dma_ops_domain *dma_dom;
2428 u64 dma_mask;
2429
2430 domain = get_domain(dev);
2431 if (PTR_ERR(domain) == -EINVAL)
2432 return (dma_addr_t)paddr;
2433 else if (IS_ERR(domain))
2434 return AMD_IOMMU_MAPPING_ERROR;
2435
2436 dma_mask = *dev->dma_mask;
2437 dma_dom = to_dma_ops_domain(domain);
2438
2439 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2440 }
2441
2442 /*
2443 * The exported unmap_single function for dma_ops.
2444 */
2445 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2446 enum dma_data_direction dir, unsigned long attrs)
2447 {
2448 struct protection_domain *domain;
2449 struct dma_ops_domain *dma_dom;
2450
2451 domain = get_domain(dev);
2452 if (IS_ERR(domain))
2453 return;
2454
2455 dma_dom = to_dma_ops_domain(domain);
2456
2457 __unmap_single(dma_dom, dma_addr, size, dir);
2458 }
2459
2460 static int sg_num_pages(struct device *dev,
2461 struct scatterlist *sglist,
2462 int nelems)
2463 {
2464 unsigned long mask, boundary_size;
2465 struct scatterlist *s;
2466 int i, npages = 0;
2467
2468 mask = dma_get_seg_boundary(dev);
2469 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2470 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2471
2472 for_each_sg(sglist, s, nelems, i) {
2473 int p, n;
2474
2475 s->dma_address = npages << PAGE_SHIFT;
2476 p = npages % boundary_size;
2477 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2478 if (p + n > boundary_size)
2479 npages += boundary_size - p;
2480 npages += n;
2481 }
2482
2483 return npages;
2484 }
2485
2486 /*
2487 * The exported map_sg function for dma_ops (handles scatter-gather
2488 * lists).
2489 */
2490 static int map_sg(struct device *dev, struct scatterlist *sglist,
2491 int nelems, enum dma_data_direction direction,
2492 unsigned long attrs)
2493 {
2494 int mapped_pages = 0, npages = 0, prot = 0, i;
2495 struct protection_domain *domain;
2496 struct dma_ops_domain *dma_dom;
2497 struct scatterlist *s;
2498 unsigned long address;
2499 u64 dma_mask;
2500
2501 domain = get_domain(dev);
2502 if (IS_ERR(domain))
2503 return 0;
2504
2505 dma_dom = to_dma_ops_domain(domain);
2506 dma_mask = *dev->dma_mask;
2507
2508 npages = sg_num_pages(dev, sglist, nelems);
2509
2510 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2511 if (address == AMD_IOMMU_MAPPING_ERROR)
2512 goto out_err;
2513
2514 prot = dir2prot(direction);
2515
2516 /* Map all sg entries */
2517 for_each_sg(sglist, s, nelems, i) {
2518 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2519
2520 for (j = 0; j < pages; ++j) {
2521 unsigned long bus_addr, phys_addr;
2522 int ret;
2523
2524 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2525 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2526 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2527 if (ret)
2528 goto out_unmap;
2529
2530 mapped_pages += 1;
2531 }
2532 }
2533
2534 /* Everything is mapped - write the right values into s->dma_address */
2535 for_each_sg(sglist, s, nelems, i) {
2536 s->dma_address += address + s->offset;
2537 s->dma_length = s->length;
2538 }
2539
2540 return nelems;
2541
2542 out_unmap:
2543 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2544 dev_name(dev), npages);
2545
2546 for_each_sg(sglist, s, nelems, i) {
2547 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2548
2549 for (j = 0; j < pages; ++j) {
2550 unsigned long bus_addr;
2551
2552 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2553 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2554
2555 if (--mapped_pages)
2556 goto out_free_iova;
2557 }
2558 }
2559
2560 out_free_iova:
2561 free_iova_fast(&dma_dom->iovad, address, npages);
2562
2563 out_err:
2564 return 0;
2565 }
2566
2567 /*
2568 * The exported map_sg function for dma_ops (handles scatter-gather
2569 * lists).
2570 */
2571 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2572 int nelems, enum dma_data_direction dir,
2573 unsigned long attrs)
2574 {
2575 struct protection_domain *domain;
2576 struct dma_ops_domain *dma_dom;
2577 unsigned long startaddr;
2578 int npages = 2;
2579
2580 domain = get_domain(dev);
2581 if (IS_ERR(domain))
2582 return;
2583
2584 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2585 dma_dom = to_dma_ops_domain(domain);
2586 npages = sg_num_pages(dev, sglist, nelems);
2587
2588 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2589 }
2590
2591 /*
2592 * The exported alloc_coherent function for dma_ops.
2593 */
2594 static void *alloc_coherent(struct device *dev, size_t size,
2595 dma_addr_t *dma_addr, gfp_t flag,
2596 unsigned long attrs)
2597 {
2598 u64 dma_mask = dev->coherent_dma_mask;
2599 struct protection_domain *domain;
2600 struct dma_ops_domain *dma_dom;
2601 struct page *page;
2602
2603 domain = get_domain(dev);
2604 if (PTR_ERR(domain) == -EINVAL) {
2605 page = alloc_pages(flag, get_order(size));
2606 *dma_addr = page_to_phys(page);
2607 return page_address(page);
2608 } else if (IS_ERR(domain))
2609 return NULL;
2610
2611 dma_dom = to_dma_ops_domain(domain);
2612 size = PAGE_ALIGN(size);
2613 dma_mask = dev->coherent_dma_mask;
2614 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2615 flag |= __GFP_ZERO;
2616
2617 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2618 if (!page) {
2619 if (!gfpflags_allow_blocking(flag))
2620 return NULL;
2621
2622 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2623 get_order(size), flag);
2624 if (!page)
2625 return NULL;
2626 }
2627
2628 if (!dma_mask)
2629 dma_mask = *dev->dma_mask;
2630
2631 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2632 size, DMA_BIDIRECTIONAL, dma_mask);
2633
2634 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2635 goto out_free;
2636
2637 return page_address(page);
2638
2639 out_free:
2640
2641 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2642 __free_pages(page, get_order(size));
2643
2644 return NULL;
2645 }
2646
2647 /*
2648 * The exported free_coherent function for dma_ops.
2649 */
2650 static void free_coherent(struct device *dev, size_t size,
2651 void *virt_addr, dma_addr_t dma_addr,
2652 unsigned long attrs)
2653 {
2654 struct protection_domain *domain;
2655 struct dma_ops_domain *dma_dom;
2656 struct page *page;
2657
2658 page = virt_to_page(virt_addr);
2659 size = PAGE_ALIGN(size);
2660
2661 domain = get_domain(dev);
2662 if (IS_ERR(domain))
2663 goto free_mem;
2664
2665 dma_dom = to_dma_ops_domain(domain);
2666
2667 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2668
2669 free_mem:
2670 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2671 __free_pages(page, get_order(size));
2672 }
2673
2674 /*
2675 * This function is called by the DMA layer to find out if we can handle a
2676 * particular device. It is part of the dma_ops.
2677 */
2678 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2679 {
2680 if (!dma_direct_supported(dev, mask))
2681 return 0;
2682 return check_device(dev);
2683 }
2684
2685 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2686 {
2687 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2688 }
2689
2690 static const struct dma_map_ops amd_iommu_dma_ops = {
2691 .alloc = alloc_coherent,
2692 .free = free_coherent,
2693 .map_page = map_page,
2694 .unmap_page = unmap_page,
2695 .map_sg = map_sg,
2696 .unmap_sg = unmap_sg,
2697 .dma_supported = amd_iommu_dma_supported,
2698 .mapping_error = amd_iommu_mapping_error,
2699 };
2700
2701 static int init_reserved_iova_ranges(void)
2702 {
2703 struct pci_dev *pdev = NULL;
2704 struct iova *val;
2705
2706 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2707
2708 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2709 &reserved_rbtree_key);
2710
2711 /* MSI memory range */
2712 val = reserve_iova(&reserved_iova_ranges,
2713 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2714 if (!val) {
2715 pr_err("Reserving MSI range failed\n");
2716 return -ENOMEM;
2717 }
2718
2719 /* HT memory range */
2720 val = reserve_iova(&reserved_iova_ranges,
2721 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2722 if (!val) {
2723 pr_err("Reserving HT range failed\n");
2724 return -ENOMEM;
2725 }
2726
2727 /*
2728 * Memory used for PCI resources
2729 * FIXME: Check whether we can reserve the PCI-hole completly
2730 */
2731 for_each_pci_dev(pdev) {
2732 int i;
2733
2734 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2735 struct resource *r = &pdev->resource[i];
2736
2737 if (!(r->flags & IORESOURCE_MEM))
2738 continue;
2739
2740 val = reserve_iova(&reserved_iova_ranges,
2741 IOVA_PFN(r->start),
2742 IOVA_PFN(r->end));
2743 if (!val) {
2744 pr_err("Reserve pci-resource range failed\n");
2745 return -ENOMEM;
2746 }
2747 }
2748 }
2749
2750 return 0;
2751 }
2752
2753 int __init amd_iommu_init_api(void)
2754 {
2755 int ret, err = 0;
2756
2757 ret = iova_cache_get();
2758 if (ret)
2759 return ret;
2760
2761 ret = init_reserved_iova_ranges();
2762 if (ret)
2763 return ret;
2764
2765 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2766 if (err)
2767 return err;
2768 #ifdef CONFIG_ARM_AMBA
2769 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2770 if (err)
2771 return err;
2772 #endif
2773 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2774 if (err)
2775 return err;
2776
2777 return 0;
2778 }
2779
2780 int __init amd_iommu_init_dma_ops(void)
2781 {
2782 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2783 iommu_detected = 1;
2784
2785 /*
2786 * In case we don't initialize SWIOTLB (actually the common case
2787 * when AMD IOMMU is enabled and SME is not active), make sure there
2788 * are global dma_ops set as a fall-back for devices not handled by
2789 * this driver (for example non-PCI devices). When SME is active,
2790 * make sure that swiotlb variable remains set so the global dma_ops
2791 * continue to be SWIOTLB.
2792 */
2793 if (!swiotlb)
2794 dma_ops = &dma_direct_ops;
2795
2796 if (amd_iommu_unmap_flush)
2797 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2798 else
2799 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2800
2801 return 0;
2802
2803 }
2804
2805 /*****************************************************************************
2806 *
2807 * The following functions belong to the exported interface of AMD IOMMU
2808 *
2809 * This interface allows access to lower level functions of the IOMMU
2810 * like protection domain handling and assignement of devices to domains
2811 * which is not possible with the dma_ops interface.
2812 *
2813 *****************************************************************************/
2814
2815 static void cleanup_domain(struct protection_domain *domain)
2816 {
2817 struct iommu_dev_data *entry;
2818 unsigned long flags;
2819
2820 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2821
2822 while (!list_empty(&domain->dev_list)) {
2823 entry = list_first_entry(&domain->dev_list,
2824 struct iommu_dev_data, list);
2825 BUG_ON(!entry->domain);
2826 __detach_device(entry);
2827 }
2828
2829 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2830 }
2831
2832 static void protection_domain_free(struct protection_domain *domain)
2833 {
2834 if (!domain)
2835 return;
2836
2837 del_domain_from_list(domain);
2838
2839 if (domain->id)
2840 domain_id_free(domain->id);
2841
2842 kfree(domain);
2843 }
2844
2845 static int protection_domain_init(struct protection_domain *domain)
2846 {
2847 spin_lock_init(&domain->lock);
2848 mutex_init(&domain->api_lock);
2849 domain->id = domain_id_alloc();
2850 if (!domain->id)
2851 return -ENOMEM;
2852 INIT_LIST_HEAD(&domain->dev_list);
2853
2854 return 0;
2855 }
2856
2857 static struct protection_domain *protection_domain_alloc(void)
2858 {
2859 struct protection_domain *domain;
2860
2861 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2862 if (!domain)
2863 return NULL;
2864
2865 if (protection_domain_init(domain))
2866 goto out_err;
2867
2868 add_domain_to_list(domain);
2869
2870 return domain;
2871
2872 out_err:
2873 kfree(domain);
2874
2875 return NULL;
2876 }
2877
2878 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2879 {
2880 struct protection_domain *pdomain;
2881 struct dma_ops_domain *dma_domain;
2882
2883 switch (type) {
2884 case IOMMU_DOMAIN_UNMANAGED:
2885 pdomain = protection_domain_alloc();
2886 if (!pdomain)
2887 return NULL;
2888
2889 pdomain->mode = PAGE_MODE_3_LEVEL;
2890 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2891 if (!pdomain->pt_root) {
2892 protection_domain_free(pdomain);
2893 return NULL;
2894 }
2895
2896 pdomain->domain.geometry.aperture_start = 0;
2897 pdomain->domain.geometry.aperture_end = ~0ULL;
2898 pdomain->domain.geometry.force_aperture = true;
2899
2900 break;
2901 case IOMMU_DOMAIN_DMA:
2902 dma_domain = dma_ops_domain_alloc();
2903 if (!dma_domain) {
2904 pr_err("AMD-Vi: Failed to allocate\n");
2905 return NULL;
2906 }
2907 pdomain = &dma_domain->domain;
2908 break;
2909 case IOMMU_DOMAIN_IDENTITY:
2910 pdomain = protection_domain_alloc();
2911 if (!pdomain)
2912 return NULL;
2913
2914 pdomain->mode = PAGE_MODE_NONE;
2915 break;
2916 default:
2917 return NULL;
2918 }
2919
2920 return &pdomain->domain;
2921 }
2922
2923 static void amd_iommu_domain_free(struct iommu_domain *dom)
2924 {
2925 struct protection_domain *domain;
2926 struct dma_ops_domain *dma_dom;
2927
2928 domain = to_pdomain(dom);
2929
2930 if (domain->dev_cnt > 0)
2931 cleanup_domain(domain);
2932
2933 BUG_ON(domain->dev_cnt != 0);
2934
2935 if (!dom)
2936 return;
2937
2938 switch (dom->type) {
2939 case IOMMU_DOMAIN_DMA:
2940 /* Now release the domain */
2941 dma_dom = to_dma_ops_domain(domain);
2942 dma_ops_domain_free(dma_dom);
2943 break;
2944 default:
2945 if (domain->mode != PAGE_MODE_NONE)
2946 free_pagetable(domain);
2947
2948 if (domain->flags & PD_IOMMUV2_MASK)
2949 free_gcr3_table(domain);
2950
2951 protection_domain_free(domain);
2952 break;
2953 }
2954 }
2955
2956 static void amd_iommu_detach_device(struct iommu_domain *dom,
2957 struct device *dev)
2958 {
2959 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2960 struct amd_iommu *iommu;
2961 int devid;
2962
2963 if (!check_device(dev))
2964 return;
2965
2966 devid = get_device_id(dev);
2967 if (devid < 0)
2968 return;
2969
2970 if (dev_data->domain != NULL)
2971 detach_device(dev);
2972
2973 iommu = amd_iommu_rlookup_table[devid];
2974 if (!iommu)
2975 return;
2976
2977 #ifdef CONFIG_IRQ_REMAP
2978 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2979 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2980 dev_data->use_vapic = 0;
2981 #endif
2982
2983 iommu_completion_wait(iommu);
2984 }
2985
2986 static int amd_iommu_attach_device(struct iommu_domain *dom,
2987 struct device *dev)
2988 {
2989 struct protection_domain *domain = to_pdomain(dom);
2990 struct iommu_dev_data *dev_data;
2991 struct amd_iommu *iommu;
2992 int ret;
2993
2994 if (!check_device(dev))
2995 return -EINVAL;
2996
2997 dev_data = dev->archdata.iommu;
2998
2999 iommu = amd_iommu_rlookup_table[dev_data->devid];
3000 if (!iommu)
3001 return -EINVAL;
3002
3003 if (dev_data->domain)
3004 detach_device(dev);
3005
3006 ret = attach_device(dev, domain);
3007
3008 #ifdef CONFIG_IRQ_REMAP
3009 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3010 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3011 dev_data->use_vapic = 1;
3012 else
3013 dev_data->use_vapic = 0;
3014 }
3015 #endif
3016
3017 iommu_completion_wait(iommu);
3018
3019 return ret;
3020 }
3021
3022 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3023 phys_addr_t paddr, size_t page_size, int iommu_prot)
3024 {
3025 struct protection_domain *domain = to_pdomain(dom);
3026 int prot = 0;
3027 int ret;
3028
3029 if (domain->mode == PAGE_MODE_NONE)
3030 return -EINVAL;
3031
3032 if (iommu_prot & IOMMU_READ)
3033 prot |= IOMMU_PROT_IR;
3034 if (iommu_prot & IOMMU_WRITE)
3035 prot |= IOMMU_PROT_IW;
3036
3037 mutex_lock(&domain->api_lock);
3038 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3039 mutex_unlock(&domain->api_lock);
3040
3041 return ret;
3042 }
3043
3044 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3045 size_t page_size)
3046 {
3047 struct protection_domain *domain = to_pdomain(dom);
3048 size_t unmap_size;
3049
3050 if (domain->mode == PAGE_MODE_NONE)
3051 return 0;
3052
3053 mutex_lock(&domain->api_lock);
3054 unmap_size = iommu_unmap_page(domain, iova, page_size);
3055 mutex_unlock(&domain->api_lock);
3056
3057 return unmap_size;
3058 }
3059
3060 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3061 dma_addr_t iova)
3062 {
3063 struct protection_domain *domain = to_pdomain(dom);
3064 unsigned long offset_mask, pte_pgsize;
3065 u64 *pte, __pte;
3066
3067 if (domain->mode == PAGE_MODE_NONE)
3068 return iova;
3069
3070 pte = fetch_pte(domain, iova, &pte_pgsize);
3071
3072 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3073 return 0;
3074
3075 offset_mask = pte_pgsize - 1;
3076 __pte = *pte & PM_ADDR_MASK;
3077
3078 return (__pte & ~offset_mask) | (iova & offset_mask);
3079 }
3080
3081 static bool amd_iommu_capable(enum iommu_cap cap)
3082 {
3083 switch (cap) {
3084 case IOMMU_CAP_CACHE_COHERENCY:
3085 return true;
3086 case IOMMU_CAP_INTR_REMAP:
3087 return (irq_remapping_enabled == 1);
3088 case IOMMU_CAP_NOEXEC:
3089 return false;
3090 }
3091
3092 return false;
3093 }
3094
3095 static void amd_iommu_get_resv_regions(struct device *dev,
3096 struct list_head *head)
3097 {
3098 struct iommu_resv_region *region;
3099 struct unity_map_entry *entry;
3100 int devid;
3101
3102 devid = get_device_id(dev);
3103 if (devid < 0)
3104 return;
3105
3106 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3107 size_t length;
3108 int prot = 0;
3109
3110 if (devid < entry->devid_start || devid > entry->devid_end)
3111 continue;
3112
3113 length = entry->address_end - entry->address_start;
3114 if (entry->prot & IOMMU_PROT_IR)
3115 prot |= IOMMU_READ;
3116 if (entry->prot & IOMMU_PROT_IW)
3117 prot |= IOMMU_WRITE;
3118
3119 region = iommu_alloc_resv_region(entry->address_start,
3120 length, prot,
3121 IOMMU_RESV_DIRECT);
3122 if (!region) {
3123 pr_err("Out of memory allocating dm-regions for %s\n",
3124 dev_name(dev));
3125 return;
3126 }
3127 list_add_tail(&region->list, head);
3128 }
3129
3130 region = iommu_alloc_resv_region(MSI_RANGE_START,
3131 MSI_RANGE_END - MSI_RANGE_START + 1,
3132 0, IOMMU_RESV_MSI);
3133 if (!region)
3134 return;
3135 list_add_tail(&region->list, head);
3136
3137 region = iommu_alloc_resv_region(HT_RANGE_START,
3138 HT_RANGE_END - HT_RANGE_START + 1,
3139 0, IOMMU_RESV_RESERVED);
3140 if (!region)
3141 return;
3142 list_add_tail(&region->list, head);
3143 }
3144
3145 static void amd_iommu_put_resv_regions(struct device *dev,
3146 struct list_head *head)
3147 {
3148 struct iommu_resv_region *entry, *next;
3149
3150 list_for_each_entry_safe(entry, next, head, list)
3151 kfree(entry);
3152 }
3153
3154 static void amd_iommu_apply_resv_region(struct device *dev,
3155 struct iommu_domain *domain,
3156 struct iommu_resv_region *region)
3157 {
3158 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3159 unsigned long start, end;
3160
3161 start = IOVA_PFN(region->start);
3162 end = IOVA_PFN(region->start + region->length - 1);
3163
3164 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3165 }
3166
3167 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3168 struct device *dev)
3169 {
3170 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3171 return dev_data->defer_attach;
3172 }
3173
3174 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3175 {
3176 struct protection_domain *dom = to_pdomain(domain);
3177
3178 domain_flush_tlb_pde(dom);
3179 domain_flush_complete(dom);
3180 }
3181
3182 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3183 unsigned long iova, size_t size)
3184 {
3185 }
3186
3187 const struct iommu_ops amd_iommu_ops = {
3188 .capable = amd_iommu_capable,
3189 .domain_alloc = amd_iommu_domain_alloc,
3190 .domain_free = amd_iommu_domain_free,
3191 .attach_dev = amd_iommu_attach_device,
3192 .detach_dev = amd_iommu_detach_device,
3193 .map = amd_iommu_map,
3194 .unmap = amd_iommu_unmap,
3195 .map_sg = default_iommu_map_sg,
3196 .iova_to_phys = amd_iommu_iova_to_phys,
3197 .add_device = amd_iommu_add_device,
3198 .remove_device = amd_iommu_remove_device,
3199 .device_group = amd_iommu_device_group,
3200 .get_resv_regions = amd_iommu_get_resv_regions,
3201 .put_resv_regions = amd_iommu_put_resv_regions,
3202 .apply_resv_region = amd_iommu_apply_resv_region,
3203 .is_attach_deferred = amd_iommu_is_attach_deferred,
3204 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3205 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3206 .iotlb_range_add = amd_iommu_iotlb_range_add,
3207 .iotlb_sync = amd_iommu_flush_iotlb_all,
3208 };
3209
3210 /*****************************************************************************
3211 *
3212 * The next functions do a basic initialization of IOMMU for pass through
3213 * mode
3214 *
3215 * In passthrough mode the IOMMU is initialized and enabled but not used for
3216 * DMA-API translation.
3217 *
3218 *****************************************************************************/
3219
3220 /* IOMMUv2 specific functions */
3221 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3222 {
3223 return atomic_notifier_chain_register(&ppr_notifier, nb);
3224 }
3225 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3226
3227 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3228 {
3229 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3230 }
3231 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3232
3233 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3234 {
3235 struct protection_domain *domain = to_pdomain(dom);
3236 unsigned long flags;
3237
3238 spin_lock_irqsave(&domain->lock, flags);
3239
3240 /* Update data structure */
3241 domain->mode = PAGE_MODE_NONE;
3242 domain->updated = true;
3243
3244 /* Make changes visible to IOMMUs */
3245 update_domain(domain);
3246
3247 /* Page-table is not visible to IOMMU anymore, so free it */
3248 free_pagetable(domain);
3249
3250 spin_unlock_irqrestore(&domain->lock, flags);
3251 }
3252 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3253
3254 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3255 {
3256 struct protection_domain *domain = to_pdomain(dom);
3257 unsigned long flags;
3258 int levels, ret;
3259
3260 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3261 return -EINVAL;
3262
3263 /* Number of GCR3 table levels required */
3264 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3265 levels += 1;
3266
3267 if (levels > amd_iommu_max_glx_val)
3268 return -EINVAL;
3269
3270 spin_lock_irqsave(&domain->lock, flags);
3271
3272 /*
3273 * Save us all sanity checks whether devices already in the
3274 * domain support IOMMUv2. Just force that the domain has no
3275 * devices attached when it is switched into IOMMUv2 mode.
3276 */
3277 ret = -EBUSY;
3278 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3279 goto out;
3280
3281 ret = -ENOMEM;
3282 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3283 if (domain->gcr3_tbl == NULL)
3284 goto out;
3285
3286 domain->glx = levels;
3287 domain->flags |= PD_IOMMUV2_MASK;
3288 domain->updated = true;
3289
3290 update_domain(domain);
3291
3292 ret = 0;
3293
3294 out:
3295 spin_unlock_irqrestore(&domain->lock, flags);
3296
3297 return ret;
3298 }
3299 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3300
3301 static int __flush_pasid(struct protection_domain *domain, int pasid,
3302 u64 address, bool size)
3303 {
3304 struct iommu_dev_data *dev_data;
3305 struct iommu_cmd cmd;
3306 int i, ret;
3307
3308 if (!(domain->flags & PD_IOMMUV2_MASK))
3309 return -EINVAL;
3310
3311 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3312
3313 /*
3314 * IOMMU TLB needs to be flushed before Device TLB to
3315 * prevent device TLB refill from IOMMU TLB
3316 */
3317 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3318 if (domain->dev_iommu[i] == 0)
3319 continue;
3320
3321 ret = iommu_queue_command(amd_iommus[i], &cmd);
3322 if (ret != 0)
3323 goto out;
3324 }
3325
3326 /* Wait until IOMMU TLB flushes are complete */
3327 domain_flush_complete(domain);
3328
3329 /* Now flush device TLBs */
3330 list_for_each_entry(dev_data, &domain->dev_list, list) {
3331 struct amd_iommu *iommu;
3332 int qdep;
3333
3334 /*
3335 There might be non-IOMMUv2 capable devices in an IOMMUv2
3336 * domain.
3337 */
3338 if (!dev_data->ats.enabled)
3339 continue;
3340
3341 qdep = dev_data->ats.qdep;
3342 iommu = amd_iommu_rlookup_table[dev_data->devid];
3343
3344 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3345 qdep, address, size);
3346
3347 ret = iommu_queue_command(iommu, &cmd);
3348 if (ret != 0)
3349 goto out;
3350 }
3351
3352 /* Wait until all device TLBs are flushed */
3353 domain_flush_complete(domain);
3354
3355 ret = 0;
3356
3357 out:
3358
3359 return ret;
3360 }
3361
3362 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3363 u64 address)
3364 {
3365 return __flush_pasid(domain, pasid, address, false);
3366 }
3367
3368 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3369 u64 address)
3370 {
3371 struct protection_domain *domain = to_pdomain(dom);
3372 unsigned long flags;
3373 int ret;
3374
3375 spin_lock_irqsave(&domain->lock, flags);
3376 ret = __amd_iommu_flush_page(domain, pasid, address);
3377 spin_unlock_irqrestore(&domain->lock, flags);
3378
3379 return ret;
3380 }
3381 EXPORT_SYMBOL(amd_iommu_flush_page);
3382
3383 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3384 {
3385 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3386 true);
3387 }
3388
3389 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3390 {
3391 struct protection_domain *domain = to_pdomain(dom);
3392 unsigned long flags;
3393 int ret;
3394
3395 spin_lock_irqsave(&domain->lock, flags);
3396 ret = __amd_iommu_flush_tlb(domain, pasid);
3397 spin_unlock_irqrestore(&domain->lock, flags);
3398
3399 return ret;
3400 }
3401 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3402
3403 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3404 {
3405 int index;
3406 u64 *pte;
3407
3408 while (true) {
3409
3410 index = (pasid >> (9 * level)) & 0x1ff;
3411 pte = &root[index];
3412
3413 if (level == 0)
3414 break;
3415
3416 if (!(*pte & GCR3_VALID)) {
3417 if (!alloc)
3418 return NULL;
3419
3420 root = (void *)get_zeroed_page(GFP_ATOMIC);
3421 if (root == NULL)
3422 return NULL;
3423
3424 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3425 }
3426
3427 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3428
3429 level -= 1;
3430 }
3431
3432 return pte;
3433 }
3434
3435 static int __set_gcr3(struct protection_domain *domain, int pasid,
3436 unsigned long cr3)
3437 {
3438 u64 *pte;
3439
3440 if (domain->mode != PAGE_MODE_NONE)
3441 return -EINVAL;
3442
3443 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3444 if (pte == NULL)
3445 return -ENOMEM;
3446
3447 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3448
3449 return __amd_iommu_flush_tlb(domain, pasid);
3450 }
3451
3452 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3453 {
3454 u64 *pte;
3455
3456 if (domain->mode != PAGE_MODE_NONE)
3457 return -EINVAL;
3458
3459 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3460 if (pte == NULL)
3461 return 0;
3462
3463 *pte = 0;
3464
3465 return __amd_iommu_flush_tlb(domain, pasid);
3466 }
3467
3468 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3469 unsigned long cr3)
3470 {
3471 struct protection_domain *domain = to_pdomain(dom);
3472 unsigned long flags;
3473 int ret;
3474
3475 spin_lock_irqsave(&domain->lock, flags);
3476 ret = __set_gcr3(domain, pasid, cr3);
3477 spin_unlock_irqrestore(&domain->lock, flags);
3478
3479 return ret;
3480 }
3481 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3482
3483 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3484 {
3485 struct protection_domain *domain = to_pdomain(dom);
3486 unsigned long flags;
3487 int ret;
3488
3489 spin_lock_irqsave(&domain->lock, flags);
3490 ret = __clear_gcr3(domain, pasid);
3491 spin_unlock_irqrestore(&domain->lock, flags);
3492
3493 return ret;
3494 }
3495 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3496
3497 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3498 int status, int tag)
3499 {
3500 struct iommu_dev_data *dev_data;
3501 struct amd_iommu *iommu;
3502 struct iommu_cmd cmd;
3503
3504 dev_data = get_dev_data(&pdev->dev);
3505 iommu = amd_iommu_rlookup_table[dev_data->devid];
3506
3507 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3508 tag, dev_data->pri_tlp);
3509
3510 return iommu_queue_command(iommu, &cmd);
3511 }
3512 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3513
3514 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3515 {
3516 struct protection_domain *pdomain;
3517
3518 pdomain = get_domain(&pdev->dev);
3519 if (IS_ERR(pdomain))
3520 return NULL;
3521
3522 /* Only return IOMMUv2 domains */
3523 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3524 return NULL;
3525
3526 return &pdomain->domain;
3527 }
3528 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3529
3530 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3531 {
3532 struct iommu_dev_data *dev_data;
3533
3534 if (!amd_iommu_v2_supported())
3535 return;
3536
3537 dev_data = get_dev_data(&pdev->dev);
3538 dev_data->errata |= (1 << erratum);
3539 }
3540 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3541
3542 int amd_iommu_device_info(struct pci_dev *pdev,
3543 struct amd_iommu_device_info *info)
3544 {
3545 int max_pasids;
3546 int pos;
3547
3548 if (pdev == NULL || info == NULL)
3549 return -EINVAL;
3550
3551 if (!amd_iommu_v2_supported())
3552 return -EINVAL;
3553
3554 memset(info, 0, sizeof(*info));
3555
3556 if (!pci_ats_disabled()) {
3557 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3558 if (pos)
3559 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3560 }
3561
3562 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3563 if (pos)
3564 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3565
3566 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3567 if (pos) {
3568 int features;
3569
3570 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3571 max_pasids = min(max_pasids, (1 << 20));
3572
3573 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3574 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3575
3576 features = pci_pasid_features(pdev);
3577 if (features & PCI_PASID_CAP_EXEC)
3578 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3579 if (features & PCI_PASID_CAP_PRIV)
3580 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3581 }
3582
3583 return 0;
3584 }
3585 EXPORT_SYMBOL(amd_iommu_device_info);
3586
3587 #ifdef CONFIG_IRQ_REMAP
3588
3589 /*****************************************************************************
3590 *
3591 * Interrupt Remapping Implementation
3592 *
3593 *****************************************************************************/
3594
3595 static struct irq_chip amd_ir_chip;
3596 static DEFINE_SPINLOCK(iommu_table_lock);
3597
3598 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3599 {
3600 u64 dte;
3601
3602 dte = amd_iommu_dev_table[devid].data[2];
3603 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3604 dte |= iommu_virt_to_phys(table->table);
3605 dte |= DTE_IRQ_REMAP_INTCTL;
3606 dte |= DTE_IRQ_TABLE_LEN;
3607 dte |= DTE_IRQ_REMAP_ENABLE;
3608
3609 amd_iommu_dev_table[devid].data[2] = dte;
3610 }
3611
3612 static struct irq_remap_table *get_irq_table(u16 devid)
3613 {
3614 struct irq_remap_table *table;
3615
3616 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3617 "%s: no iommu for devid %x\n", __func__, devid))
3618 return NULL;
3619
3620 table = irq_lookup_table[devid];
3621 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3622 return NULL;
3623
3624 return table;
3625 }
3626
3627 static struct irq_remap_table *__alloc_irq_table(void)
3628 {
3629 struct irq_remap_table *table;
3630
3631 table = kzalloc(sizeof(*table), GFP_KERNEL);
3632 if (!table)
3633 return NULL;
3634
3635 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3636 if (!table->table) {
3637 kfree(table);
3638 return NULL;
3639 }
3640 raw_spin_lock_init(&table->lock);
3641
3642 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3643 memset(table->table, 0,
3644 MAX_IRQS_PER_TABLE * sizeof(u32));
3645 else
3646 memset(table->table, 0,
3647 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3648 return table;
3649 }
3650
3651 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3652 struct irq_remap_table *table)
3653 {
3654 irq_lookup_table[devid] = table;
3655 set_dte_irq_entry(devid, table);
3656 iommu_flush_dte(iommu, devid);
3657 }
3658
3659 static struct irq_remap_table *alloc_irq_table(u16 devid)
3660 {
3661 struct irq_remap_table *table = NULL;
3662 struct irq_remap_table *new_table = NULL;
3663 struct amd_iommu *iommu;
3664 unsigned long flags;
3665 u16 alias;
3666
3667 spin_lock_irqsave(&iommu_table_lock, flags);
3668
3669 iommu = amd_iommu_rlookup_table[devid];
3670 if (!iommu)
3671 goto out_unlock;
3672
3673 table = irq_lookup_table[devid];
3674 if (table)
3675 goto out_unlock;
3676
3677 alias = amd_iommu_alias_table[devid];
3678 table = irq_lookup_table[alias];
3679 if (table) {
3680 set_remap_table_entry(iommu, devid, table);
3681 goto out_wait;
3682 }
3683 spin_unlock_irqrestore(&iommu_table_lock, flags);
3684
3685 /* Nothing there yet, allocate new irq remapping table */
3686 new_table = __alloc_irq_table();
3687 if (!new_table)
3688 return NULL;
3689
3690 spin_lock_irqsave(&iommu_table_lock, flags);
3691
3692 table = irq_lookup_table[devid];
3693 if (table)
3694 goto out_unlock;
3695
3696 table = irq_lookup_table[alias];
3697 if (table) {
3698 set_remap_table_entry(iommu, devid, table);
3699 goto out_wait;
3700 }
3701
3702 table = new_table;
3703 new_table = NULL;
3704
3705 set_remap_table_entry(iommu, devid, table);
3706 if (devid != alias)
3707 set_remap_table_entry(iommu, alias, table);
3708
3709 out_wait:
3710 iommu_completion_wait(iommu);
3711
3712 out_unlock:
3713 spin_unlock_irqrestore(&iommu_table_lock, flags);
3714
3715 if (new_table) {
3716 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3717 kfree(new_table);
3718 }
3719 return table;
3720 }
3721
3722 static int alloc_irq_index(u16 devid, int count, bool align)
3723 {
3724 struct irq_remap_table *table;
3725 int index, c, alignment = 1;
3726 unsigned long flags;
3727 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3728
3729 if (!iommu)
3730 return -ENODEV;
3731
3732 table = alloc_irq_table(devid);
3733 if (!table)
3734 return -ENODEV;
3735
3736 if (align)
3737 alignment = roundup_pow_of_two(count);
3738
3739 raw_spin_lock_irqsave(&table->lock, flags);
3740
3741 /* Scan table for free entries */
3742 for (index = ALIGN(table->min_index, alignment), c = 0;
3743 index < MAX_IRQS_PER_TABLE;) {
3744 if (!iommu->irte_ops->is_allocated(table, index)) {
3745 c += 1;
3746 } else {
3747 c = 0;
3748 index = ALIGN(index + 1, alignment);
3749 continue;
3750 }
3751
3752 if (c == count) {
3753 for (; c != 0; --c)
3754 iommu->irte_ops->set_allocated(table, index - c + 1);
3755
3756 index -= count - 1;
3757 goto out;
3758 }
3759
3760 index++;
3761 }
3762
3763 index = -ENOSPC;
3764
3765 out:
3766 raw_spin_unlock_irqrestore(&table->lock, flags);
3767
3768 return index;
3769 }
3770
3771 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3772 struct amd_ir_data *data)
3773 {
3774 struct irq_remap_table *table;
3775 struct amd_iommu *iommu;
3776 unsigned long flags;
3777 struct irte_ga *entry;
3778
3779 iommu = amd_iommu_rlookup_table[devid];
3780 if (iommu == NULL)
3781 return -EINVAL;
3782
3783 table = get_irq_table(devid);
3784 if (!table)
3785 return -ENOMEM;
3786
3787 raw_spin_lock_irqsave(&table->lock, flags);
3788
3789 entry = (struct irte_ga *)table->table;
3790 entry = &entry[index];
3791 entry->lo.fields_remap.valid = 0;
3792 entry->hi.val = irte->hi.val;
3793 entry->lo.val = irte->lo.val;
3794 entry->lo.fields_remap.valid = 1;
3795 if (data)
3796 data->ref = entry;
3797
3798 raw_spin_unlock_irqrestore(&table->lock, flags);
3799
3800 iommu_flush_irt(iommu, devid);
3801 iommu_completion_wait(iommu);
3802
3803 return 0;
3804 }
3805
3806 static int modify_irte(u16 devid, int index, union irte *irte)
3807 {
3808 struct irq_remap_table *table;
3809 struct amd_iommu *iommu;
3810 unsigned long flags;
3811
3812 iommu = amd_iommu_rlookup_table[devid];
3813 if (iommu == NULL)
3814 return -EINVAL;
3815
3816 table = get_irq_table(devid);
3817 if (!table)
3818 return -ENOMEM;
3819
3820 raw_spin_lock_irqsave(&table->lock, flags);
3821 table->table[index] = irte->val;
3822 raw_spin_unlock_irqrestore(&table->lock, flags);
3823
3824 iommu_flush_irt(iommu, devid);
3825 iommu_completion_wait(iommu);
3826
3827 return 0;
3828 }
3829
3830 static void free_irte(u16 devid, int index)
3831 {
3832 struct irq_remap_table *table;
3833 struct amd_iommu *iommu;
3834 unsigned long flags;
3835
3836 iommu = amd_iommu_rlookup_table[devid];
3837 if (iommu == NULL)
3838 return;
3839
3840 table = get_irq_table(devid);
3841 if (!table)
3842 return;
3843
3844 raw_spin_lock_irqsave(&table->lock, flags);
3845 iommu->irte_ops->clear_allocated(table, index);
3846 raw_spin_unlock_irqrestore(&table->lock, flags);
3847
3848 iommu_flush_irt(iommu, devid);
3849 iommu_completion_wait(iommu);
3850 }
3851
3852 static void irte_prepare(void *entry,
3853 u32 delivery_mode, u32 dest_mode,
3854 u8 vector, u32 dest_apicid, int devid)
3855 {
3856 union irte *irte = (union irte *) entry;
3857
3858 irte->val = 0;
3859 irte->fields.vector = vector;
3860 irte->fields.int_type = delivery_mode;
3861 irte->fields.destination = dest_apicid;
3862 irte->fields.dm = dest_mode;
3863 irte->fields.valid = 1;
3864 }
3865
3866 static void irte_ga_prepare(void *entry,
3867 u32 delivery_mode, u32 dest_mode,
3868 u8 vector, u32 dest_apicid, int devid)
3869 {
3870 struct irte_ga *irte = (struct irte_ga *) entry;
3871
3872 irte->lo.val = 0;
3873 irte->hi.val = 0;
3874 irte->lo.fields_remap.int_type = delivery_mode;
3875 irte->lo.fields_remap.dm = dest_mode;
3876 irte->hi.fields.vector = vector;
3877 irte->lo.fields_remap.destination = dest_apicid;
3878 irte->lo.fields_remap.valid = 1;
3879 }
3880
3881 static void irte_activate(void *entry, u16 devid, u16 index)
3882 {
3883 union irte *irte = (union irte *) entry;
3884
3885 irte->fields.valid = 1;
3886 modify_irte(devid, index, irte);
3887 }
3888
3889 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3890 {
3891 struct irte_ga *irte = (struct irte_ga *) entry;
3892
3893 irte->lo.fields_remap.valid = 1;
3894 modify_irte_ga(devid, index, irte, NULL);
3895 }
3896
3897 static void irte_deactivate(void *entry, u16 devid, u16 index)
3898 {
3899 union irte *irte = (union irte *) entry;
3900
3901 irte->fields.valid = 0;
3902 modify_irte(devid, index, irte);
3903 }
3904
3905 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3906 {
3907 struct irte_ga *irte = (struct irte_ga *) entry;
3908
3909 irte->lo.fields_remap.valid = 0;
3910 modify_irte_ga(devid, index, irte, NULL);
3911 }
3912
3913 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3914 u8 vector, u32 dest_apicid)
3915 {
3916 union irte *irte = (union irte *) entry;
3917
3918 irte->fields.vector = vector;
3919 irte->fields.destination = dest_apicid;
3920 modify_irte(devid, index, irte);
3921 }
3922
3923 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3924 u8 vector, u32 dest_apicid)
3925 {
3926 struct irte_ga *irte = (struct irte_ga *) entry;
3927
3928 if (!irte->lo.fields_remap.guest_mode) {
3929 irte->hi.fields.vector = vector;
3930 irte->lo.fields_remap.destination = dest_apicid;
3931 modify_irte_ga(devid, index, irte, NULL);
3932 }
3933 }
3934
3935 #define IRTE_ALLOCATED (~1U)
3936 static void irte_set_allocated(struct irq_remap_table *table, int index)
3937 {
3938 table->table[index] = IRTE_ALLOCATED;
3939 }
3940
3941 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3942 {
3943 struct irte_ga *ptr = (struct irte_ga *)table->table;
3944 struct irte_ga *irte = &ptr[index];
3945
3946 memset(&irte->lo.val, 0, sizeof(u64));
3947 memset(&irte->hi.val, 0, sizeof(u64));
3948 irte->hi.fields.vector = 0xff;
3949 }
3950
3951 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3952 {
3953 union irte *ptr = (union irte *)table->table;
3954 union irte *irte = &ptr[index];
3955
3956 return irte->val != 0;
3957 }
3958
3959 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3960 {
3961 struct irte_ga *ptr = (struct irte_ga *)table->table;
3962 struct irte_ga *irte = &ptr[index];
3963
3964 return irte->hi.fields.vector != 0;
3965 }
3966
3967 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3968 {
3969 table->table[index] = 0;
3970 }
3971
3972 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3973 {
3974 struct irte_ga *ptr = (struct irte_ga *)table->table;
3975 struct irte_ga *irte = &ptr[index];
3976
3977 memset(&irte->lo.val, 0, sizeof(u64));
3978 memset(&irte->hi.val, 0, sizeof(u64));
3979 }
3980
3981 static int get_devid(struct irq_alloc_info *info)
3982 {
3983 int devid = -1;
3984
3985 switch (info->type) {
3986 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3987 devid = get_ioapic_devid(info->ioapic_id);
3988 break;
3989 case X86_IRQ_ALLOC_TYPE_HPET:
3990 devid = get_hpet_devid(info->hpet_id);
3991 break;
3992 case X86_IRQ_ALLOC_TYPE_MSI:
3993 case X86_IRQ_ALLOC_TYPE_MSIX:
3994 devid = get_device_id(&info->msi_dev->dev);
3995 break;
3996 default:
3997 BUG_ON(1);
3998 break;
3999 }
4000
4001 return devid;
4002 }
4003
4004 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4005 {
4006 struct amd_iommu *iommu;
4007 int devid;
4008
4009 if (!info)
4010 return NULL;
4011
4012 devid = get_devid(info);
4013 if (devid >= 0) {
4014 iommu = amd_iommu_rlookup_table[devid];
4015 if (iommu)
4016 return iommu->ir_domain;
4017 }
4018
4019 return NULL;
4020 }
4021
4022 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4023 {
4024 struct amd_iommu *iommu;
4025 int devid;
4026
4027 if (!info)
4028 return NULL;
4029
4030 switch (info->type) {
4031 case X86_IRQ_ALLOC_TYPE_MSI:
4032 case X86_IRQ_ALLOC_TYPE_MSIX:
4033 devid = get_device_id(&info->msi_dev->dev);
4034 if (devid < 0)
4035 return NULL;
4036
4037 iommu = amd_iommu_rlookup_table[devid];
4038 if (iommu)
4039 return iommu->msi_domain;
4040 break;
4041 default:
4042 break;
4043 }
4044
4045 return NULL;
4046 }
4047
4048 struct irq_remap_ops amd_iommu_irq_ops = {
4049 .prepare = amd_iommu_prepare,
4050 .enable = amd_iommu_enable,
4051 .disable = amd_iommu_disable,
4052 .reenable = amd_iommu_reenable,
4053 .enable_faulting = amd_iommu_enable_faulting,
4054 .get_ir_irq_domain = get_ir_irq_domain,
4055 .get_irq_domain = get_irq_domain,
4056 };
4057
4058 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4059 struct irq_cfg *irq_cfg,
4060 struct irq_alloc_info *info,
4061 int devid, int index, int sub_handle)
4062 {
4063 struct irq_2_irte *irte_info = &data->irq_2_irte;
4064 struct msi_msg *msg = &data->msi_entry;
4065 struct IO_APIC_route_entry *entry;
4066 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4067
4068 if (!iommu)
4069 return;
4070
4071 data->irq_2_irte.devid = devid;
4072 data->irq_2_irte.index = index + sub_handle;
4073 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4074 apic->irq_dest_mode, irq_cfg->vector,
4075 irq_cfg->dest_apicid, devid);
4076
4077 switch (info->type) {
4078 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4079 /* Setup IOAPIC entry */
4080 entry = info->ioapic_entry;
4081 info->ioapic_entry = NULL;
4082 memset(entry, 0, sizeof(*entry));
4083 entry->vector = index;
4084 entry->mask = 0;
4085 entry->trigger = info->ioapic_trigger;
4086 entry->polarity = info->ioapic_polarity;
4087 /* Mask level triggered irqs. */
4088 if (info->ioapic_trigger)
4089 entry->mask = 1;
4090 break;
4091
4092 case X86_IRQ_ALLOC_TYPE_HPET:
4093 case X86_IRQ_ALLOC_TYPE_MSI:
4094 case X86_IRQ_ALLOC_TYPE_MSIX:
4095 msg->address_hi = MSI_ADDR_BASE_HI;
4096 msg->address_lo = MSI_ADDR_BASE_LO;
4097 msg->data = irte_info->index;
4098 break;
4099
4100 default:
4101 BUG_ON(1);
4102 break;
4103 }
4104 }
4105
4106 struct amd_irte_ops irte_32_ops = {
4107 .prepare = irte_prepare,
4108 .activate = irte_activate,
4109 .deactivate = irte_deactivate,
4110 .set_affinity = irte_set_affinity,
4111 .set_allocated = irte_set_allocated,
4112 .is_allocated = irte_is_allocated,
4113 .clear_allocated = irte_clear_allocated,
4114 };
4115
4116 struct amd_irte_ops irte_128_ops = {
4117 .prepare = irte_ga_prepare,
4118 .activate = irte_ga_activate,
4119 .deactivate = irte_ga_deactivate,
4120 .set_affinity = irte_ga_set_affinity,
4121 .set_allocated = irte_ga_set_allocated,
4122 .is_allocated = irte_ga_is_allocated,
4123 .clear_allocated = irte_ga_clear_allocated,
4124 };
4125
4126 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4127 unsigned int nr_irqs, void *arg)
4128 {
4129 struct irq_alloc_info *info = arg;
4130 struct irq_data *irq_data;
4131 struct amd_ir_data *data = NULL;
4132 struct irq_cfg *cfg;
4133 int i, ret, devid;
4134 int index;
4135
4136 if (!info)
4137 return -EINVAL;
4138 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4139 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4140 return -EINVAL;
4141
4142 /*
4143 * With IRQ remapping enabled, don't need contiguous CPU vectors
4144 * to support multiple MSI interrupts.
4145 */
4146 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4147 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4148
4149 devid = get_devid(info);
4150 if (devid < 0)
4151 return -EINVAL;
4152
4153 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4154 if (ret < 0)
4155 return ret;
4156
4157 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4158 struct irq_remap_table *table;
4159 struct amd_iommu *iommu;
4160
4161 table = alloc_irq_table(devid);
4162 if (table) {
4163 if (!table->min_index) {
4164 /*
4165 * Keep the first 32 indexes free for IOAPIC
4166 * interrupts.
4167 */
4168 table->min_index = 32;
4169 iommu = amd_iommu_rlookup_table[devid];
4170 for (i = 0; i < 32; ++i)
4171 iommu->irte_ops->set_allocated(table, i);
4172 }
4173 WARN_ON(table->min_index != 32);
4174 index = info->ioapic_pin;
4175 } else {
4176 index = -ENOMEM;
4177 }
4178 } else {
4179 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4180
4181 index = alloc_irq_index(devid, nr_irqs, align);
4182 }
4183 if (index < 0) {
4184 pr_warn("Failed to allocate IRTE\n");
4185 ret = index;
4186 goto out_free_parent;
4187 }
4188
4189 for (i = 0; i < nr_irqs; i++) {
4190 irq_data = irq_domain_get_irq_data(domain, virq + i);
4191 cfg = irqd_cfg(irq_data);
4192 if (!irq_data || !cfg) {
4193 ret = -EINVAL;
4194 goto out_free_data;
4195 }
4196
4197 ret = -ENOMEM;
4198 data = kzalloc(sizeof(*data), GFP_KERNEL);
4199 if (!data)
4200 goto out_free_data;
4201
4202 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4203 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4204 else
4205 data->entry = kzalloc(sizeof(struct irte_ga),
4206 GFP_KERNEL);
4207 if (!data->entry) {
4208 kfree(data);
4209 goto out_free_data;
4210 }
4211
4212 irq_data->hwirq = (devid << 16) + i;
4213 irq_data->chip_data = data;
4214 irq_data->chip = &amd_ir_chip;
4215 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4216 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4217 }
4218
4219 return 0;
4220
4221 out_free_data:
4222 for (i--; i >= 0; i--) {
4223 irq_data = irq_domain_get_irq_data(domain, virq + i);
4224 if (irq_data)
4225 kfree(irq_data->chip_data);
4226 }
4227 for (i = 0; i < nr_irqs; i++)
4228 free_irte(devid, index + i);
4229 out_free_parent:
4230 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4231 return ret;
4232 }
4233
4234 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4235 unsigned int nr_irqs)
4236 {
4237 struct irq_2_irte *irte_info;
4238 struct irq_data *irq_data;
4239 struct amd_ir_data *data;
4240 int i;
4241
4242 for (i = 0; i < nr_irqs; i++) {
4243 irq_data = irq_domain_get_irq_data(domain, virq + i);
4244 if (irq_data && irq_data->chip_data) {
4245 data = irq_data->chip_data;
4246 irte_info = &data->irq_2_irte;
4247 free_irte(irte_info->devid, irte_info->index);
4248 kfree(data->entry);
4249 kfree(data);
4250 }
4251 }
4252 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4253 }
4254
4255 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4256 struct amd_ir_data *ir_data,
4257 struct irq_2_irte *irte_info,
4258 struct irq_cfg *cfg);
4259
4260 static int irq_remapping_activate(struct irq_domain *domain,
4261 struct irq_data *irq_data, bool reserve)
4262 {
4263 struct amd_ir_data *data = irq_data->chip_data;
4264 struct irq_2_irte *irte_info = &data->irq_2_irte;
4265 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4266 struct irq_cfg *cfg = irqd_cfg(irq_data);
4267
4268 if (!iommu)
4269 return 0;
4270
4271 iommu->irte_ops->activate(data->entry, irte_info->devid,
4272 irte_info->index);
4273 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4274 return 0;
4275 }
4276
4277 static void irq_remapping_deactivate(struct irq_domain *domain,
4278 struct irq_data *irq_data)
4279 {
4280 struct amd_ir_data *data = irq_data->chip_data;
4281 struct irq_2_irte *irte_info = &data->irq_2_irte;
4282 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4283
4284 if (iommu)
4285 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4286 irte_info->index);
4287 }
4288
4289 static const struct irq_domain_ops amd_ir_domain_ops = {
4290 .alloc = irq_remapping_alloc,
4291 .free = irq_remapping_free,
4292 .activate = irq_remapping_activate,
4293 .deactivate = irq_remapping_deactivate,
4294 };
4295
4296 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4297 {
4298 struct amd_iommu *iommu;
4299 struct amd_iommu_pi_data *pi_data = vcpu_info;
4300 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4301 struct amd_ir_data *ir_data = data->chip_data;
4302 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4303 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4304 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4305
4306 /* Note:
4307 * This device has never been set up for guest mode.
4308 * we should not modify the IRTE
4309 */
4310 if (!dev_data || !dev_data->use_vapic)
4311 return 0;
4312
4313 pi_data->ir_data = ir_data;
4314
4315 /* Note:
4316 * SVM tries to set up for VAPIC mode, but we are in
4317 * legacy mode. So, we force legacy mode instead.
4318 */
4319 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4320 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4321 __func__);
4322 pi_data->is_guest_mode = false;
4323 }
4324
4325 iommu = amd_iommu_rlookup_table[irte_info->devid];
4326 if (iommu == NULL)
4327 return -EINVAL;
4328
4329 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4330 if (pi_data->is_guest_mode) {
4331 /* Setting */
4332 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4333 irte->hi.fields.vector = vcpu_pi_info->vector;
4334 irte->lo.fields_vapic.ga_log_intr = 1;
4335 irte->lo.fields_vapic.guest_mode = 1;
4336 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4337
4338 ir_data->cached_ga_tag = pi_data->ga_tag;
4339 } else {
4340 /* Un-Setting */
4341 struct irq_cfg *cfg = irqd_cfg(data);
4342
4343 irte->hi.val = 0;
4344 irte->lo.val = 0;
4345 irte->hi.fields.vector = cfg->vector;
4346 irte->lo.fields_remap.guest_mode = 0;
4347 irte->lo.fields_remap.destination = cfg->dest_apicid;
4348 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4349 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4350
4351 /*
4352 * This communicates the ga_tag back to the caller
4353 * so that it can do all the necessary clean up.
4354 */
4355 ir_data->cached_ga_tag = 0;
4356 }
4357
4358 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4359 }
4360
4361
4362 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4363 struct amd_ir_data *ir_data,
4364 struct irq_2_irte *irte_info,
4365 struct irq_cfg *cfg)
4366 {
4367
4368 /*
4369 * Atomically updates the IRTE with the new destination, vector
4370 * and flushes the interrupt entry cache.
4371 */
4372 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4373 irte_info->index, cfg->vector,
4374 cfg->dest_apicid);
4375 }
4376
4377 static int amd_ir_set_affinity(struct irq_data *data,
4378 const struct cpumask *mask, bool force)
4379 {
4380 struct amd_ir_data *ir_data = data->chip_data;
4381 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4382 struct irq_cfg *cfg = irqd_cfg(data);
4383 struct irq_data *parent = data->parent_data;
4384 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4385 int ret;
4386
4387 if (!iommu)
4388 return -ENODEV;
4389
4390 ret = parent->chip->irq_set_affinity(parent, mask, force);
4391 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4392 return ret;
4393
4394 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4395 /*
4396 * After this point, all the interrupts will start arriving
4397 * at the new destination. So, time to cleanup the previous
4398 * vector allocation.
4399 */
4400 send_cleanup_vector(cfg);
4401
4402 return IRQ_SET_MASK_OK_DONE;
4403 }
4404
4405 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4406 {
4407 struct amd_ir_data *ir_data = irq_data->chip_data;
4408
4409 *msg = ir_data->msi_entry;
4410 }
4411
4412 static struct irq_chip amd_ir_chip = {
4413 .name = "AMD-IR",
4414 .irq_ack = apic_ack_irq,
4415 .irq_set_affinity = amd_ir_set_affinity,
4416 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4417 .irq_compose_msi_msg = ir_compose_msi_msg,
4418 };
4419
4420 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4421 {
4422 struct fwnode_handle *fn;
4423
4424 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4425 if (!fn)
4426 return -ENOMEM;
4427 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4428 irq_domain_free_fwnode(fn);
4429 if (!iommu->ir_domain)
4430 return -ENOMEM;
4431
4432 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4433 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4434 "AMD-IR-MSI",
4435 iommu->index);
4436 return 0;
4437 }
4438
4439 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4440 {
4441 unsigned long flags;
4442 struct amd_iommu *iommu;
4443 struct irq_remap_table *table;
4444 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4445 int devid = ir_data->irq_2_irte.devid;
4446 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4447 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4448
4449 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4450 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4451 return 0;
4452
4453 iommu = amd_iommu_rlookup_table[devid];
4454 if (!iommu)
4455 return -ENODEV;
4456
4457 table = get_irq_table(devid);
4458 if (!table)
4459 return -ENODEV;
4460
4461 raw_spin_lock_irqsave(&table->lock, flags);
4462
4463 if (ref->lo.fields_vapic.guest_mode) {
4464 if (cpu >= 0)
4465 ref->lo.fields_vapic.destination = cpu;
4466 ref->lo.fields_vapic.is_run = is_run;
4467 barrier();
4468 }
4469
4470 raw_spin_unlock_irqrestore(&table->lock, flags);
4471
4472 iommu_flush_irt(iommu, devid);
4473 iommu_completion_wait(iommu);
4474 return 0;
4475 }
4476 EXPORT_SYMBOL(amd_iommu_update_ga);
4477 #endif
Linux with added FPC-III support