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of/platform: Initialise default DMA masks
[linux/fpc-iii.git] / drivers / pinctrl / mvebu / pinctrl-armada-37xx.c
blob53cf800688e947ff4720273e64dad39b3d6b8133
1 /*
2 * Marvell 37xx SoC pinctrl driver
3 *
4 * Copyright (C) 2017 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
11 */
12
13 #include <linux/gpio/driver.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
26
27 #include "../pinctrl-utils.h"
28
29 #define OUTPUT_EN 0x0
30 #define INPUT_VAL 0x10
31 #define OUTPUT_VAL 0x18
32 #define OUTPUT_CTL 0x20
33 #define SELECTION 0x30
34
35 #define IRQ_EN 0x0
36 #define IRQ_POL 0x08
37 #define IRQ_STATUS 0x10
38 #define IRQ_WKUP 0x18
39
40 #define NB_FUNCS 3
41 #define GPIO_PER_REG 32
42
43 /**
44 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
45 * The pins of a pinmux groups are composed of one or two groups of contiguous
46 * pins.
47 * @name: Name of the pin group, used to lookup the group.
48 * @start_pins: Index of the first pin of the main range of pins belonging to
49 * the group
50 * @npins: Number of pins included in the first range
51 * @reg_mask: Bit mask matching the group in the selection register
52 * @extra_pins: Index of the first pin of the optional second range of pins
53 * belonging to the group
54 * @npins: Number of pins included in the second optional range
55 * @funcs: A list of pinmux functions that can be selected for this group.
56 * @pins: List of the pins included in the group
57 */
58 struct armada_37xx_pin_group {
59 const char *name;
60 unsigned int start_pin;
61 unsigned int npins;
62 u32 reg_mask;
63 u32 val[NB_FUNCS];
64 unsigned int extra_pin;
65 unsigned int extra_npins;
66 const char *funcs[NB_FUNCS];
67 unsigned int *pins;
68 };
69
70 struct armada_37xx_pin_data {
71 u8 nr_pins;
72 char *name;
73 struct armada_37xx_pin_group *groups;
74 int ngroups;
75 };
76
77 struct armada_37xx_pmx_func {
78 const char *name;
79 const char **groups;
80 unsigned int ngroups;
81 };
82
83 struct armada_37xx_pinctrl {
84 struct regmap *regmap;
85 void __iomem *base;
86 const struct armada_37xx_pin_data *data;
87 struct device *dev;
88 struct gpio_chip gpio_chip;
89 struct irq_chip irq_chip;
90 spinlock_t irq_lock;
91 struct pinctrl_desc pctl;
92 struct pinctrl_dev *pctl_dev;
93 struct armada_37xx_pin_group *groups;
94 unsigned int ngroups;
95 struct armada_37xx_pmx_func *funcs;
96 unsigned int nfuncs;
97 };
98
99 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
100 { \
101 .name = _name, \
102 .start_pin = _start, \
103 .npins = _nr, \
104 .reg_mask = _mask, \
105 .val = {0, _mask}, \
106 .funcs = {_func1, _func2} \
107 }
108
109 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
110 { \
111 .name = _name, \
112 .start_pin = _start, \
113 .npins = _nr, \
114 .reg_mask = _mask, \
115 .val = {0, _mask}, \
116 .funcs = {_func1, "gpio"} \
117 }
118
119 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
120 { \
121 .name = _name, \
122 .start_pin = _start, \
123 .npins = _nr, \
124 .reg_mask = _mask, \
125 .val = {_val1, _val2}, \
126 .funcs = {_func1, "gpio"} \
127 }
128
129 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
130 { \
131 .name = _name, \
132 .start_pin = _start, \
133 .npins = _nr, \
134 .reg_mask = _mask, \
135 .val = {_v1, _v2, _v3}, \
136 .funcs = {_f1, _f2, "gpio"} \
137 }
138
139 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
140 _f1, _f2) \
141 { \
142 .name = _name, \
143 .start_pin = _start, \
144 .npins = _nr, \
145 .reg_mask = _mask, \
146 .val = {_v1, _v2}, \
147 .extra_pin = _start2, \
148 .extra_npins = _nr2, \
149 .funcs = {_f1, _f2} \
150 }
151
152 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
153 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
154 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
155 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
156 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
157 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
158 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
159 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
160 PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"),
161 PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"),
162 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
163 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
164 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
165 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
166 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
167 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
168 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
169 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
170 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
171 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
172 18, 2, "gpio", "uart"),
173 PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
174 PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
175 PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
176 PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"),
177
178 };
179
180 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
181 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
182 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
183 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
184 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
185 PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
186 PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
187 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
188 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
189 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
190 "mii", "mii_err"),
191 };
192
193 static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
194 .nr_pins = 36,
195 .name = "GPIO1",
196 .groups = armada_37xx_nb_groups,
197 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
198 };
199
200 static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
201 .nr_pins = 30,
202 .name = "GPIO2",
203 .groups = armada_37xx_sb_groups,
204 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
205 };
206
207 static inline void armada_37xx_update_reg(unsigned int *reg,
208 unsigned int offset)
209 {
210 /* We never have more than 2 registers */
211 if (offset >= GPIO_PER_REG) {
212 offset -= GPIO_PER_REG;
213 *reg += sizeof(u32);
214 }
215 }
216
217 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
218 struct armada_37xx_pinctrl *info, int pin, int *grp)
219 {
220 while (*grp < info->ngroups) {
221 struct armada_37xx_pin_group *group = &info->groups[*grp];
222 int j;
223
224 *grp = *grp + 1;
225 for (j = 0; j < (group->npins + group->extra_npins); j++)
226 if (group->pins[j] == pin)
227 return group;
228 }
229 return NULL;
230 }
231
232 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
233 unsigned int selector, unsigned long *config)
234 {
235 return -ENOTSUPP;
236 }
237
238 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
239 unsigned int selector, unsigned long *configs,
240 unsigned int num_configs)
241 {
242 return -ENOTSUPP;
243 }
244
245 static const struct pinconf_ops armada_37xx_pinconf_ops = {
246 .is_generic = true,
247 .pin_config_group_get = armada_37xx_pin_config_group_get,
248 .pin_config_group_set = armada_37xx_pin_config_group_set,
249 };
250
251 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
252 {
253 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
254
255 return info->ngroups;
256 }
257
258 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
259 unsigned int group)
260 {
261 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
262
263 return info->groups[group].name;
264 }
265
266 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
267 unsigned int selector,
268 const unsigned int **pins,
269 unsigned int *npins)
270 {
271 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
272
273 if (selector >= info->ngroups)
274 return -EINVAL;
275
276 *pins = info->groups[selector].pins;
277 *npins = info->groups[selector].npins +
278 info->groups[selector].extra_npins;
279
280 return 0;
281 }
282
283 static const struct pinctrl_ops armada_37xx_pctrl_ops = {
284 .get_groups_count = armada_37xx_get_groups_count,
285 .get_group_name = armada_37xx_get_group_name,
286 .get_group_pins = armada_37xx_get_group_pins,
287 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
288 .dt_free_map = pinctrl_utils_free_map,
289 };
290
291 /*
292 * Pinmux_ops handling
293 */
294
295 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
296 {
297 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
298
299 return info->nfuncs;
300 }
301
302 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
303 unsigned int selector)
304 {
305 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
306
307 return info->funcs[selector].name;
308 }
309
310 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
311 unsigned int selector,
312 const char * const **groups,
313 unsigned int * const num_groups)
314 {
315 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
316
317 *groups = info->funcs[selector].groups;
318 *num_groups = info->funcs[selector].ngroups;
319
320 return 0;
321 }
322
323 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
324 const char *name,
325 struct armada_37xx_pin_group *grp)
326 {
327 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
328 unsigned int reg = SELECTION;
329 unsigned int mask = grp->reg_mask;
330 int func, val;
331
332 dev_dbg(info->dev, "enable function %s group %s\n",
333 name, grp->name);
334
335 func = match_string(grp->funcs, NB_FUNCS, name);
336 if (func < 0)
337 return -ENOTSUPP;
338
339 val = grp->val[func];
340
341 regmap_update_bits(info->regmap, reg, mask, val);
342
343 return 0;
344 }
345
346 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
347 unsigned int selector,
348 unsigned int group)
349 {
350
351 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
352 struct armada_37xx_pin_group *grp = &info->groups[group];
353 const char *name = info->funcs[selector].name;
354
355 return armada_37xx_pmx_set_by_name(pctldev, name, grp);
356 }
357
358 static inline void armada_37xx_irq_update_reg(unsigned int *reg,
359 struct irq_data *d)
360 {
361 int offset = irqd_to_hwirq(d);
362
363 armada_37xx_update_reg(reg, offset);
364 }
365
366 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
367 unsigned int offset)
368 {
369 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
370 unsigned int reg = OUTPUT_EN;
371 unsigned int mask;
372
373 armada_37xx_update_reg(&reg, offset);
374 mask = BIT(offset);
375
376 return regmap_update_bits(info->regmap, reg, mask, 0);
377 }
378
379 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
380 unsigned int offset)
381 {
382 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
383 unsigned int reg = OUTPUT_EN;
384 unsigned int val, mask;
385
386 armada_37xx_update_reg(&reg, offset);
387 mask = BIT(offset);
388 regmap_read(info->regmap, reg, &val);
389
390 return !(val & mask);
391 }
392
393 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
394 unsigned int offset, int value)
395 {
396 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
397 unsigned int reg = OUTPUT_EN;
398 unsigned int mask, val, ret;
399
400 armada_37xx_update_reg(&reg, offset);
401 mask = BIT(offset);
402
403 ret = regmap_update_bits(info->regmap, reg, mask, mask);
404
405 if (ret)
406 return ret;
407
408 reg = OUTPUT_VAL;
409 val = value ? mask : 0;
410 regmap_update_bits(info->regmap, reg, mask, val);
411
412 return 0;
413 }
414
415 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
416 {
417 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
418 unsigned int reg = INPUT_VAL;
419 unsigned int val, mask;
420
421 armada_37xx_update_reg(&reg, offset);
422 mask = BIT(offset);
423
424 regmap_read(info->regmap, reg, &val);
425
426 return (val & mask) != 0;
427 }
428
429 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
430 int value)
431 {
432 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
433 unsigned int reg = OUTPUT_VAL;
434 unsigned int mask, val;
435
436 armada_37xx_update_reg(&reg, offset);
437 mask = BIT(offset);
438 val = value ? mask : 0;
439
440 regmap_update_bits(info->regmap, reg, mask, val);
441 }
442
443 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
444 struct pinctrl_gpio_range *range,
445 unsigned int offset, bool input)
446 {
447 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
448 struct gpio_chip *chip = range->gc;
449
450 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
451 offset, range->name, offset, input ? "input" : "output");
452
453 if (input)
454 armada_37xx_gpio_direction_input(chip, offset);
455 else
456 armada_37xx_gpio_direction_output(chip, offset, 0);
457
458 return 0;
459 }
460
461 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
462 struct pinctrl_gpio_range *range,
463 unsigned int offset)
464 {
465 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
466 struct armada_37xx_pin_group *group;
467 int grp = 0;
468
469 dev_dbg(info->dev, "requesting gpio %d\n", offset);
470
471 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
472 armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
473
474 return 0;
475 }
476
477 static const struct pinmux_ops armada_37xx_pmx_ops = {
478 .get_functions_count = armada_37xx_pmx_get_funcs_count,
479 .get_function_name = armada_37xx_pmx_get_func_name,
480 .get_function_groups = armada_37xx_pmx_get_groups,
481 .set_mux = armada_37xx_pmx_set,
482 .gpio_request_enable = armada_37xx_gpio_request_enable,
483 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
484 };
485
486 static const struct gpio_chip armada_37xx_gpiolib_chip = {
487 .request = gpiochip_generic_request,
488 .free = gpiochip_generic_free,
489 .set = armada_37xx_gpio_set,
490 .get = armada_37xx_gpio_get,
491 .get_direction = armada_37xx_gpio_get_direction,
492 .direction_input = armada_37xx_gpio_direction_input,
493 .direction_output = armada_37xx_gpio_direction_output,
494 .owner = THIS_MODULE,
495 };
496
497 static void armada_37xx_irq_ack(struct irq_data *d)
498 {
499 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
500 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
501 u32 reg = IRQ_STATUS;
502 unsigned long flags;
503
504 armada_37xx_irq_update_reg(&reg, d);
505 spin_lock_irqsave(&info->irq_lock, flags);
506 writel(d->mask, info->base + reg);
507 spin_unlock_irqrestore(&info->irq_lock, flags);
508 }
509
510 static void armada_37xx_irq_mask(struct irq_data *d)
511 {
512 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
513 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
514 u32 val, reg = IRQ_EN;
515 unsigned long flags;
516
517 armada_37xx_irq_update_reg(&reg, d);
518 spin_lock_irqsave(&info->irq_lock, flags);
519 val = readl(info->base + reg);
520 writel(val & ~d->mask, info->base + reg);
521 spin_unlock_irqrestore(&info->irq_lock, flags);
522 }
523
524 static void armada_37xx_irq_unmask(struct irq_data *d)
525 {
526 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
527 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
528 u32 val, reg = IRQ_EN;
529 unsigned long flags;
530
531 armada_37xx_irq_update_reg(&reg, d);
532 spin_lock_irqsave(&info->irq_lock, flags);
533 val = readl(info->base + reg);
534 writel(val | d->mask, info->base + reg);
535 spin_unlock_irqrestore(&info->irq_lock, flags);
536 }
537
538 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
539 {
540 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
541 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
542 u32 val, reg = IRQ_WKUP;
543 unsigned long flags;
544
545 armada_37xx_irq_update_reg(&reg, d);
546 spin_lock_irqsave(&info->irq_lock, flags);
547 val = readl(info->base + reg);
548 if (on)
549 val |= (BIT(d->hwirq % GPIO_PER_REG));
550 else
551 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
552 writel(val, info->base + reg);
553 spin_unlock_irqrestore(&info->irq_lock, flags);
554
555 return 0;
556 }
557
558 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
559 {
560 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
561 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
562 u32 val, reg = IRQ_POL;
563 unsigned long flags;
564
565 spin_lock_irqsave(&info->irq_lock, flags);
566 armada_37xx_irq_update_reg(&reg, d);
567 val = readl(info->base + reg);
568 switch (type) {
569 case IRQ_TYPE_EDGE_RISING:
570 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
571 break;
572 case IRQ_TYPE_EDGE_FALLING:
573 val |= (BIT(d->hwirq % GPIO_PER_REG));
574 break;
575 case IRQ_TYPE_EDGE_BOTH: {
576 u32 in_val, in_reg = INPUT_VAL;
577
578 armada_37xx_irq_update_reg(&in_reg, d);
579 regmap_read(info->regmap, in_reg, &in_val);
580
581 /* Set initial polarity based on current input level. */
582 if (in_val & d->mask)
583 val |= d->mask; /* falling */
584 else
585 val &= ~d->mask; /* rising */
586 break;
587 }
588 default:
589 spin_unlock_irqrestore(&info->irq_lock, flags);
590 return -EINVAL;
591 }
592 writel(val, info->base + reg);
593 spin_unlock_irqrestore(&info->irq_lock, flags);
594
595 return 0;
596 }
597
598 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
599 u32 pin_idx)
600 {
601 u32 reg_idx = pin_idx / GPIO_PER_REG;
602 u32 bit_num = pin_idx % GPIO_PER_REG;
603 u32 p, l, ret;
604 unsigned long flags;
605
606 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
607
608 spin_lock_irqsave(&info->irq_lock, flags);
609 p = readl(info->base + IRQ_POL + 4 * reg_idx);
610 if ((p ^ l) & (1 << bit_num)) {
611 /*
612 * For the gpios which are used for both-edge irqs, when their
613 * interrupts happen, their input levels are changed,
614 * yet their interrupt polarities are kept in old values, we
615 * should synchronize their interrupt polarities; for example,
616 * at first a gpio's input level is low and its interrupt
617 * polarity control is "Detect rising edge", then the gpio has
618 * a interrupt , its level turns to high, we should change its
619 * polarity control to "Detect falling edge" correspondingly.
620 */
621 p ^= 1 << bit_num;
622 writel(p, info->base + IRQ_POL + 4 * reg_idx);
623 ret = 0;
624 } else {
625 /* Spurious irq */
626 ret = -1;
627 }
628
629 spin_unlock_irqrestore(&info->irq_lock, flags);
630 return ret;
631 }
632
633 static void armada_37xx_irq_handler(struct irq_desc *desc)
634 {
635 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
636 struct irq_chip *chip = irq_desc_get_chip(desc);
637 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
638 struct irq_domain *d = gc->irq.domain;
639 int i;
640
641 chained_irq_enter(chip, desc);
642 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
643 u32 status;
644 unsigned long flags;
645
646 spin_lock_irqsave(&info->irq_lock, flags);
647 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
648 /* Manage only the interrupt that was enabled */
649 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
650 spin_unlock_irqrestore(&info->irq_lock, flags);
651 while (status) {
652 u32 hwirq = ffs(status) - 1;
653 u32 virq = irq_find_mapping(d, hwirq +
654 i * GPIO_PER_REG);
655 u32 t = irq_get_trigger_type(virq);
656
657 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
658 /* Swap polarity (race with GPIO line) */
659 if (armada_37xx_edge_both_irq_swap_pol(info,
660 hwirq + i * GPIO_PER_REG)) {
661 /*
662 * For spurious irq, which gpio level
663 * is not as expected after incoming
664 * edge, just ack the gpio irq.
665 */
666 writel(1 << hwirq,
667 info->base +
668 IRQ_STATUS + 4 * i);
669 goto update_status;
670 }
671 }
672
673 generic_handle_irq(virq);
674
675 update_status:
676 /* Update status in case a new IRQ appears */
677 spin_lock_irqsave(&info->irq_lock, flags);
678 status = readl_relaxed(info->base +
679 IRQ_STATUS + 4 * i);
680 /* Manage only the interrupt that was enabled */
681 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
682 spin_unlock_irqrestore(&info->irq_lock, flags);
683 }
684 }
685 chained_irq_exit(chip, desc);
686 }
687
688 static unsigned int armada_37xx_irq_startup(struct irq_data *d)
689 {
690 /*
691 * The mask field is a "precomputed bitmask for accessing the
692 * chip registers" which was introduced for the generic
693 * irqchip framework. As we don't use this framework, we can
694 * reuse this field for our own usage.
695 */
696 d->mask = BIT(d->hwirq % GPIO_PER_REG);
697
698 armada_37xx_irq_unmask(d);
699
700 return 0;
701 }
702
703 static int armada_37xx_irqchip_register(struct platform_device *pdev,
704 struct armada_37xx_pinctrl *info)
705 {
706 struct device_node *np = info->dev->of_node;
707 struct gpio_chip *gc = &info->gpio_chip;
708 struct irq_chip *irqchip = &info->irq_chip;
709 struct resource res;
710 int ret = -ENODEV, i, nr_irq_parent;
711
712 /* Check if we have at least one gpio-controller child node */
713 for_each_child_of_node(info->dev->of_node, np) {
714 if (of_property_read_bool(np, "gpio-controller")) {
715 ret = 0;
716 break;
717 }
718 };
719 if (ret)
720 return ret;
721
722 nr_irq_parent = of_irq_count(np);
723 spin_lock_init(&info->irq_lock);
724
725 if (!nr_irq_parent) {
726 dev_err(&pdev->dev, "Invalid or no IRQ\n");
727 return 0;
728 }
729
730 if (of_address_to_resource(info->dev->of_node, 1, &res)) {
731 dev_err(info->dev, "cannot find IO resource\n");
732 return -ENOENT;
733 }
734
735 info->base = devm_ioremap_resource(info->dev, &res);
736 if (IS_ERR(info->base))
737 return PTR_ERR(info->base);
738
739 irqchip->irq_ack = armada_37xx_irq_ack;
740 irqchip->irq_mask = armada_37xx_irq_mask;
741 irqchip->irq_unmask = armada_37xx_irq_unmask;
742 irqchip->irq_set_wake = armada_37xx_irq_set_wake;
743 irqchip->irq_set_type = armada_37xx_irq_set_type;
744 irqchip->irq_startup = armada_37xx_irq_startup;
745 irqchip->name = info->data->name;
746 ret = gpiochip_irqchip_add(gc, irqchip, 0,
747 handle_edge_irq, IRQ_TYPE_NONE);
748 if (ret) {
749 dev_info(&pdev->dev, "could not add irqchip\n");
750 return ret;
751 }
752
753 /*
754 * Many interrupts are connected to the parent interrupt
755 * controller. But we do not take advantage of this and use
756 * the chained irq with all of them.
757 */
758 for (i = 0; i < nr_irq_parent; i++) {
759 int irq = irq_of_parse_and_map(np, i);
760
761 if (irq < 0)
762 continue;
763
764 gpiochip_set_chained_irqchip(gc, irqchip, irq,
765 armada_37xx_irq_handler);
766 }
767
768 return 0;
769 }
770
771 static int armada_37xx_gpiochip_register(struct platform_device *pdev,
772 struct armada_37xx_pinctrl *info)
773 {
774 struct device_node *np;
775 struct gpio_chip *gc;
776 int ret = -ENODEV;
777
778 for_each_child_of_node(info->dev->of_node, np) {
779 if (of_find_property(np, "gpio-controller", NULL)) {
780 ret = 0;
781 break;
782 }
783 };
784 if (ret)
785 return ret;
786
787 info->gpio_chip = armada_37xx_gpiolib_chip;
788
789 gc = &info->gpio_chip;
790 gc->ngpio = info->data->nr_pins;
791 gc->parent = &pdev->dev;
792 gc->base = -1;
793 gc->of_node = np;
794 gc->label = info->data->name;
795
796 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
797 if (ret)
798 return ret;
799 ret = armada_37xx_irqchip_register(pdev, info);
800 if (ret)
801 return ret;
802
803 return 0;
804 }
805
806 /**
807 * armada_37xx_add_function() - Add a new function to the list
808 * @funcs: array of function to add the new one
809 * @funcsize: size of the remaining space for the function
810 * @name: name of the function to add
811 *
812 * If it is a new function then create it by adding its name else
813 * increment the number of group associated to this function.
814 */
815 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
816 int *funcsize, const char *name)
817 {
818 int i = 0;
819
820 if (*funcsize <= 0)
821 return -EOVERFLOW;
822
823 while (funcs->ngroups) {
824 /* function already there */
825 if (strcmp(funcs->name, name) == 0) {
826 funcs->ngroups++;
827
828 return -EEXIST;
829 }
830 funcs++;
831 i++;
832 }
833
834 /* append new unique function */
835 funcs->name = name;
836 funcs->ngroups = 1;
837 (*funcsize)--;
838
839 return 0;
840 }
841
842 /**
843 * armada_37xx_fill_group() - complete the group array
844 * @info: info driver instance
845 *
846 * Based on the data available from the armada_37xx_pin_group array
847 * completes the last member of the struct for each function: the list
848 * of the groups associated to this function.
849 *
850 */
851 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
852 {
853 int n, num = 0, funcsize = info->data->nr_pins;
854
855 for (n = 0; n < info->ngroups; n++) {
856 struct armada_37xx_pin_group *grp = &info->groups[n];
857 int i, j, f;
858
859 grp->pins = devm_kcalloc(info->dev,
860 grp->npins + grp->extra_npins,
861 sizeof(*grp->pins),
862 GFP_KERNEL);
863 if (!grp->pins)
864 return -ENOMEM;
865
866 for (i = 0; i < grp->npins; i++)
867 grp->pins[i] = grp->start_pin + i;
868
869 for (j = 0; j < grp->extra_npins; j++)
870 grp->pins[i+j] = grp->extra_pin + j;
871
872 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
873 int ret;
874 /* check for unique functions and count groups */
875 ret = armada_37xx_add_function(info->funcs, &funcsize,
876 grp->funcs[f]);
877 if (ret == -EOVERFLOW)
878 dev_err(info->dev,
879 "More functions than pins(%d)\n",
880 info->data->nr_pins);
881 if (ret < 0)
882 continue;
883 num++;
884 }
885 }
886
887 info->nfuncs = num;
888
889 return 0;
890 }
891
892 /**
893 * armada_37xx_fill_funcs() - complete the funcs array
894 * @info: info driver instance
895 *
896 * Based on the data available from the armada_37xx_pin_group array
897 * completes the last two member of the struct for each group:
898 * - the list of the pins included in the group
899 * - the list of pinmux functions that can be selected for this group
900 *
901 */
902 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
903 {
904 struct armada_37xx_pmx_func *funcs = info->funcs;
905 int n;
906
907 for (n = 0; n < info->nfuncs; n++) {
908 const char *name = funcs[n].name;
909 const char **groups;
910 int g;
911
912 funcs[n].groups = devm_kcalloc(info->dev,
913 funcs[n].ngroups,
914 sizeof(*(funcs[n].groups)),
915 GFP_KERNEL);
916 if (!funcs[n].groups)
917 return -ENOMEM;
918
919 groups = funcs[n].groups;
920
921 for (g = 0; g < info->ngroups; g++) {
922 struct armada_37xx_pin_group *gp = &info->groups[g];
923 int f;
924
925 f = match_string(gp->funcs, NB_FUNCS, name);
926 if (f < 0)
927 continue;
928
929 *groups = gp->name;
930 groups++;
931 }
932 }
933 return 0;
934 }
935
936 static int armada_37xx_pinctrl_register(struct platform_device *pdev,
937 struct armada_37xx_pinctrl *info)
938 {
939 const struct armada_37xx_pin_data *pin_data = info->data;
940 struct pinctrl_desc *ctrldesc = &info->pctl;
941 struct pinctrl_pin_desc *pindesc, *pdesc;
942 int pin, ret;
943
944 info->groups = pin_data->groups;
945 info->ngroups = pin_data->ngroups;
946
947 ctrldesc->name = "armada_37xx-pinctrl";
948 ctrldesc->owner = THIS_MODULE;
949 ctrldesc->pctlops = &armada_37xx_pctrl_ops;
950 ctrldesc->pmxops = &armada_37xx_pmx_ops;
951 ctrldesc->confops = &armada_37xx_pinconf_ops;
952
953 pindesc = devm_kcalloc(&pdev->dev,
954 pin_data->nr_pins, sizeof(*pindesc),
955 GFP_KERNEL);
956 if (!pindesc)
957 return -ENOMEM;
958
959 ctrldesc->pins = pindesc;
960 ctrldesc->npins = pin_data->nr_pins;
961
962 pdesc = pindesc;
963 for (pin = 0; pin < pin_data->nr_pins; pin++) {
964 pdesc->number = pin;
965 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
966 pin_data->name, pin);
967 pdesc++;
968 }
969
970 /*
971 * we allocate functions for number of pins and hope there are
972 * fewer unique functions than pins available
973 */
974 info->funcs = devm_kcalloc(&pdev->dev,
975 pin_data->nr_pins,
976 sizeof(struct armada_37xx_pmx_func),
977 GFP_KERNEL);
978 if (!info->funcs)
979 return -ENOMEM;
980
981
982 ret = armada_37xx_fill_group(info);
983 if (ret)
984 return ret;
985
986 ret = armada_37xx_fill_func(info);
987 if (ret)
988 return ret;
989
990 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
991 if (IS_ERR(info->pctl_dev)) {
992 dev_err(&pdev->dev, "could not register pinctrl driver\n");
993 return PTR_ERR(info->pctl_dev);
994 }
995
996 return 0;
997 }
998
999 static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
1000 {
1001 .compatible = "marvell,armada3710-sb-pinctrl",
1002 .data = &armada_37xx_pin_sb,
1003 },
1004 {
1005 .compatible = "marvell,armada3710-nb-pinctrl",
1006 .data = &armada_37xx_pin_nb,
1007 },
1008 { },
1009 };
1010
1011 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
1012 {
1013 struct armada_37xx_pinctrl *info;
1014 struct device *dev = &pdev->dev;
1015 struct device_node *np = dev->of_node;
1016 struct regmap *regmap;
1017 int ret;
1018
1019 info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
1020 GFP_KERNEL);
1021 if (!info)
1022 return -ENOMEM;
1023
1024 info->dev = dev;
1025
1026 regmap = syscon_node_to_regmap(np);
1027 if (IS_ERR(regmap)) {
1028 dev_err(&pdev->dev, "cannot get regmap\n");
1029 return PTR_ERR(regmap);
1030 }
1031 info->regmap = regmap;
1032
1033 info->data = of_device_get_match_data(dev);
1034
1035 ret = armada_37xx_pinctrl_register(pdev, info);
1036 if (ret)
1037 return ret;
1038
1039 ret = armada_37xx_gpiochip_register(pdev, info);
1040 if (ret)
1041 return ret;
1042
1043 platform_set_drvdata(pdev, info);
1044
1045 return 0;
1046 }
1047
1048 static struct platform_driver armada_37xx_pinctrl_driver = {
1049 .driver = {
1050 .name = "armada-37xx-pinctrl",
1051 .of_match_table = armada_37xx_pinctrl_of_match,
1052 },
1053 };
1054
1055 builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1056 armada_37xx_pinctrl_probe);
Linux with added FPC-III support