?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
netxen patches
[linux/fpc-iii.git] / drivers / net / netxen / netxen_nic_niu.c
blob40d7003a371caf4d06dd9d0cd91aa84ce1845bc7
1 /*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Provides access to the Network Interface Unit h/w block.
31 *
32 */
33
34 #include "netxen_nic.h"
35
36 #define NETXEN_GB_MAC_SOFT_RESET 0x80000000
37 #define NETXEN_GB_MAC_RESET_PROT_BLK 0x000F0000
38 #define NETXEN_GB_MAC_ENABLE_TX_RX 0x00000005
39 #define NETXEN_GB_MAC_PAUSED_FRMS 0x00000020
40
41 static long phy_lock_timeout = 100000000;
42
43 static inline int phy_lock(struct netxen_adapter *adapter)
44 {
45 int i;
46 int done = 0, timeout = 0;
47
48 while (!done) {
49 done =
50 readl(pci_base_offset
51 (adapter, NETXEN_PCIE_REG(PCIE_SEM3_LOCK)));
52 if (done == 1)
53 break;
54 if (timeout >= phy_lock_timeout) {
55 return -1;
56 }
57 timeout++;
58 if (!in_atomic())
59 schedule();
60 else {
61 for (i = 0; i < 20; i++)
62 cpu_relax();
63 }
64 }
65
66 writel(PHY_LOCK_DRIVER,
67 NETXEN_CRB_NORMALIZE(adapter, NETXEN_PHY_LOCK_ID));
68 return 0;
69 }
70
71 static inline int phy_unlock(struct netxen_adapter *adapter)
72 {
73 readl(pci_base_offset(adapter, NETXEN_PCIE_REG(PCIE_SEM3_UNLOCK)));
74
75 return 0;
76 }
77
78 /*
79 * netxen_niu_gbe_phy_read - read a register from the GbE PHY via
80 * mii management interface.
81 *
82 * Note: The MII management interface goes through port 0.
83 * Individual phys are addressed as follows:
84 * @param phy [15:8] phy id
85 * @param reg [7:0] register number
86 *
87 * @returns 0 on success
88 * -1 on error
89 *
90 */
91 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long phy,
92 long reg, __u32 * readval)
93 {
94 long timeout = 0;
95 long result = 0;
96 long restore = 0;
97 __u32 address;
98 __u32 command;
99 __u32 status;
100 __u32 mac_cfg0;
101
102 if (phy_lock(adapter) != 0) {
103 return -1;
104 }
105
106 /*
107 * MII mgmt all goes through port 0 MAC interface,
108 * so it cannot be in reset
109 */
110
111 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0),
112 &mac_cfg0, 4))
113 return -EIO;
114 if (netxen_gb_get_soft_reset(mac_cfg0)) {
115 __u32 temp;
116 temp = 0;
117 netxen_gb_tx_reset_pb(temp);
118 netxen_gb_rx_reset_pb(temp);
119 netxen_gb_tx_reset_mac(temp);
120 netxen_gb_rx_reset_mac(temp);
121 if (netxen_nic_hw_write_wx(adapter,
122 NETXEN_NIU_GB_MAC_CONFIG_0(0),
123 &temp, 4))
124 return -EIO;
125 restore = 1;
126 }
127
128 address = 0;
129 netxen_gb_mii_mgmt_reg_addr(address, reg);
130 netxen_gb_mii_mgmt_phy_addr(address, phy);
131 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0),
132 &address, 4))
133 return -EIO;
134 command = 0; /* turn off any prior activity */
135 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
136 &command, 4))
137 return -EIO;
138 /* send read command */
139 netxen_gb_mii_mgmt_set_read_cycle(command);
140 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
141 &command, 4))
142 return -EIO;
143
144 status = 0;
145 do {
146 if (netxen_nic_hw_read_wx(adapter,
147 NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
148 &status, 4))
149 return -EIO;
150 timeout++;
151 } while ((netxen_get_gb_mii_mgmt_busy(status)
152 || netxen_get_gb_mii_mgmt_notvalid(status))
153 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
154
155 if (timeout < NETXEN_NIU_PHY_WAITMAX) {
156 if (netxen_nic_hw_read_wx(adapter,
157 NETXEN_NIU_GB_MII_MGMT_STATUS(0),
158 readval, 4))
159 return -EIO;
160 result = 0;
161 } else
162 result = -1;
163
164 if (restore)
165 if (netxen_nic_hw_write_wx(adapter,
166 NETXEN_NIU_GB_MAC_CONFIG_0(0),
167 &mac_cfg0, 4))
168 return -EIO;
169 phy_unlock(adapter);
170 return result;
171 }
172
173 /*
174 * netxen_niu_gbe_phy_write - write a register to the GbE PHY via
175 * mii management interface.
176 *
177 * Note: The MII management interface goes through port 0.
178 * Individual phys are addressed as follows:
179 * @param phy [15:8] phy id
180 * @param reg [7:0] register number
181 *
182 * @returns 0 on success
183 * -1 on error
184 *
185 */
186 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
187 long phy, long reg, __u32 val)
188 {
189 long timeout = 0;
190 long result = 0;
191 long restore = 0;
192 __u32 address;
193 __u32 command;
194 __u32 status;
195 __u32 mac_cfg0;
196
197 /*
198 * MII mgmt all goes through port 0 MAC interface, so it
199 * cannot be in reset
200 */
201
202 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0),
203 &mac_cfg0, 4))
204 return -EIO;
205 if (netxen_gb_get_soft_reset(mac_cfg0)) {
206 __u32 temp;
207 temp = 0;
208 netxen_gb_tx_reset_pb(temp);
209 netxen_gb_rx_reset_pb(temp);
210 netxen_gb_tx_reset_mac(temp);
211 netxen_gb_rx_reset_mac(temp);
212
213 if (netxen_nic_hw_write_wx(adapter,
214 NETXEN_NIU_GB_MAC_CONFIG_0(0),
215 &temp, 4))
216 return -EIO;
217 restore = 1;
218 }
219
220 command = 0; /* turn off any prior activity */
221 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
222 &command, 4))
223 return -EIO;
224
225 address = 0;
226 netxen_gb_mii_mgmt_reg_addr(address, reg);
227 netxen_gb_mii_mgmt_phy_addr(address, phy);
228 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0),
229 &address, 4))
230 return -EIO;
231
232 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0),
233 &val, 4))
234 return -EIO;
235
236 status = 0;
237 do {
238 if (netxen_nic_hw_read_wx(adapter,
239 NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
240 &status, 4))
241 return -EIO;
242 timeout++;
243 } while ((netxen_get_gb_mii_mgmt_busy(status))
244 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
245
246 if (timeout < NETXEN_NIU_PHY_WAITMAX)
247 result = 0;
248 else
249 result = -EIO;
250
251 /* restore the state of port 0 MAC in case we tampered with it */
252 if (restore)
253 if (netxen_nic_hw_write_wx(adapter,
254 NETXEN_NIU_GB_MAC_CONFIG_0(0),
255 &mac_cfg0, 4))
256 return -EIO;
257
258 return result;
259 }
260
261 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter,
262 int port)
263 {
264 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x3f);
265 return 0;
266 }
267
268 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter,
269 int port)
270 {
271 int result = 0;
272 __u32 enable = 0;
273 netxen_set_phy_int_link_status_changed(enable);
274 netxen_set_phy_int_autoneg_completed(enable);
275 netxen_set_phy_int_speed_changed(enable);
276
277 if (0 !=
278 netxen_niu_gbe_phy_write(adapter, port,
279 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE,
280 enable))
281 result = -EIO;
282
283 return result;
284 }
285
286 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter,
287 int port)
288 {
289 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x7f);
290 return 0;
291 }
292
293 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter,
294 int port)
295 {
296 int result = 0;
297 if (0 !=
298 netxen_niu_gbe_phy_write(adapter, port,
299 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE, 0))
300 result = -EIO;
301
302 return result;
303 }
304
305 int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter,
306 int port)
307 {
308 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_ACTIVE_INT, -1);
309 return 0;
310 }
311
312 int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter,
313 int port)
314 {
315 int result = 0;
316 if (0 !=
317 netxen_niu_gbe_phy_write(adapter, port,
318 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
319 -EIO))
320 result = -EIO;
321
322 return result;
323 }
324
325 /*
326 * netxen_niu_gbe_set_mii_mode- Set 10/100 Mbit Mode for GbE MAC
327 *
328 */
329 void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter,
330 int port, long enable)
331 {
332 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2);
333 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
334 0x80000000);
335 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
336 0x0000f0025);
337 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port),
338 0xf1ff);
339 netxen_crb_writelit_adapter(adapter,
340 NETXEN_NIU_GB0_GMII_MODE + (port << 3), 0);
341 netxen_crb_writelit_adapter(adapter,
342 NETXEN_NIU_GB0_MII_MODE + (port << 3), 1);
343 netxen_crb_writelit_adapter(adapter,
344 (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
345 netxen_crb_writelit_adapter(adapter,
346 NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
347
348 if (enable) {
349 /*
350 * Do NOT enable flow control until a suitable solution for
351 * shutting down pause frames is found.
352 */
353 netxen_crb_writelit_adapter(adapter,
354 NETXEN_NIU_GB_MAC_CONFIG_0(port),
355 0x5);
356 }
357
358 if (netxen_niu_gbe_enable_phy_interrupts(adapter, port))
359 printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n");
360 if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
361 printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n");
362 }
363
364 /*
365 * netxen_niu_gbe_set_gmii_mode- Set GbE Mode for GbE MAC
366 */
367 void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter,
368 int port, long enable)
369 {
370 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2);
371 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
372 0x80000000);
373 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
374 0x0000f0025);
375 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port),
376 0xf2ff);
377 netxen_crb_writelit_adapter(adapter,
378 NETXEN_NIU_GB0_MII_MODE + (port << 3), 0);
379 netxen_crb_writelit_adapter(adapter,
380 NETXEN_NIU_GB0_GMII_MODE + (port << 3), 1);
381 netxen_crb_writelit_adapter(adapter,
382 (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
383 netxen_crb_writelit_adapter(adapter,
384 NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
385
386 if (enable) {
387 /*
388 * Do NOT enable flow control until a suitable solution for
389 * shutting down pause frames is found.
390 */
391 netxen_crb_writelit_adapter(adapter,
392 NETXEN_NIU_GB_MAC_CONFIG_0(port),
393 0x5);
394 }
395
396 if (netxen_niu_gbe_enable_phy_interrupts(adapter, port))
397 printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n");
398 if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
399 printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n");
400 }
401
402 int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
403 {
404 int result = 0;
405 __u32 status;
406 if (adapter->disable_phy_interrupts)
407 adapter->disable_phy_interrupts(adapter, port);
408 mdelay(2);
409
410 if (0 ==
411 netxen_niu_gbe_phy_read(adapter, port,
412 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
413 &status)) {
414 if (netxen_get_phy_link(status)) {
415 if (netxen_get_phy_speed(status) == 2) {
416 netxen_niu_gbe_set_gmii_mode(adapter, port, 1);
417 } else if ((netxen_get_phy_speed(status) == 1)
418 || (netxen_get_phy_speed(status) == 0)) {
419 netxen_niu_gbe_set_mii_mode(adapter, port, 1);
420 } else {
421 result = -1;
422 }
423
424 } else {
425 /*
426 * We don't have link. Cable must be unconnected.
427 * Enable phy interrupts so we take action when
428 * plugged in.
429 */
430
431 netxen_crb_writelit_adapter(adapter,
432 NETXEN_NIU_GB_MAC_CONFIG_0
433 (port),
434 NETXEN_GB_MAC_SOFT_RESET);
435 netxen_crb_writelit_adapter(adapter,
436 NETXEN_NIU_GB_MAC_CONFIG_0
437 (port),
438 NETXEN_GB_MAC_RESET_PROT_BLK
439 | NETXEN_GB_MAC_ENABLE_TX_RX
440 |
441 NETXEN_GB_MAC_PAUSED_FRMS);
442 if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
443 printk(KERN_ERR PFX
444 "ERROR clearing PHY interrupts\n");
445 if (netxen_niu_gbe_enable_phy_interrupts(adapter, port))
446 printk(KERN_ERR PFX
447 "ERROR enabling PHY interrupts\n");
448 if (netxen_niu_gbe_clear_phy_interrupts(adapter, port))
449 printk(KERN_ERR PFX
450 "ERROR clearing PHY interrupts\n");
451 result = -1;
452 }
453 } else {
454 result = -EIO;
455 }
456 return result;
457 }
458
459 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
460 {
461 long reg = 0, ret = 0;
462
463 if (adapter->ahw.boardcfg.board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) {
464 netxen_crb_writelit_adapter(adapter,
465 NETXEN_NIU_XG1_CONFIG_0, 0x5);
466 /* XXX hack for Mez cards: both ports in promisc mode */
467 netxen_nic_hw_read_wx(adapter,
468 NETXEN_NIU_XGE_CONFIG_1, &reg, 4);
469 reg = (reg | 0x2000UL);
470 netxen_crb_writelit_adapter(adapter,
471 NETXEN_NIU_XGE_CONFIG_1, reg);
472 reg = 0;
473 netxen_nic_hw_read_wx(adapter,
474 NETXEN_NIU_XG1_CONFIG_1, &reg, 4);
475 reg = (reg | 0x2000UL);
476 netxen_crb_writelit_adapter(adapter,
477 NETXEN_NIU_XG1_CONFIG_1, reg);
478 }
479
480 return ret;
481 }
482
483 /*
484 * netxen_niu_gbe_handle_phy_interrupt - Handles GbE PHY interrupts
485 * @param enable 0 means don't enable the port
486 * 1 means enable (or re-enable) the port
487 */
488 int netxen_niu_gbe_handle_phy_interrupt(struct netxen_adapter *adapter,
489 int port, long enable)
490 {
491 int result = 0;
492 __u32 int_src;
493
494 printk(KERN_INFO PFX "NETXEN: Handling PHY interrupt on port %d"
495 " (device enable = %d)\n", (int)port, (int)enable);
496
497 /*
498 * The read of the PHY INT status will clear the pending
499 * interrupt status
500 */
501 if (netxen_niu_gbe_phy_read(adapter, port,
502 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
503 &int_src) != 0)
504 result = -EINVAL;
505 else {
506 printk(KERN_INFO PFX "PHY Interrupt source = 0x%x \n", int_src);
507 if (netxen_get_phy_int_jabber(int_src))
508 printk(KERN_INFO PFX "jabber Interrupt ");
509 if (netxen_get_phy_int_polarity_changed(int_src))
510 printk(KERN_INFO PFX "polarity changed ");
511 if (netxen_get_phy_int_energy_detect(int_src))
512 printk(KERN_INFO PFX "energy detect \n");
513 if (netxen_get_phy_int_downshift(int_src))
514 printk(KERN_INFO PFX "downshift \n");
515 if (netxen_get_phy_int_mdi_xover_changed(int_src))
516 printk(KERN_INFO PFX "mdi_xover_changed ");
517 if (netxen_get_phy_int_fifo_over_underflow(int_src))
518 printk(KERN_INFO PFX "fifo_over_underflow ");
519 if (netxen_get_phy_int_false_carrier(int_src))
520 printk(KERN_INFO PFX "false_carrier ");
521 if (netxen_get_phy_int_symbol_error(int_src))
522 printk(KERN_INFO PFX "symbol_error ");
523 if (netxen_get_phy_int_autoneg_completed(int_src))
524 printk(KERN_INFO PFX "autoneg_completed ");
525 if (netxen_get_phy_int_page_received(int_src))
526 printk(KERN_INFO PFX "page_received ");
527 if (netxen_get_phy_int_duplex_changed(int_src))
528 printk(KERN_INFO PFX "duplex_changed ");
529 if (netxen_get_phy_int_autoneg_error(int_src))
530 printk(KERN_INFO PFX "autoneg_error ");
531 if ((netxen_get_phy_int_speed_changed(int_src))
532 || (netxen_get_phy_int_link_status_changed(int_src))) {
533 __u32 status;
534
535 printk(KERN_INFO PFX
536 "speed_changed or link status changed");
537 if (netxen_niu_gbe_phy_read
538 (adapter, port,
539 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
540 &status) == 0) {
541 if (netxen_get_phy_speed(status) == 2) {
542 printk
543 (KERN_INFO PFX "Link speed changed"
544 " to 1000 Mbps\n");
545 netxen_niu_gbe_set_gmii_mode(adapter,
546 port,
547 enable);
548 } else if (netxen_get_phy_speed(status) == 1) {
549 printk
550 (KERN_INFO PFX "Link speed changed"
551 " to 100 Mbps\n");
552 netxen_niu_gbe_set_mii_mode(adapter,
553 port,
554 enable);
555 } else if (netxen_get_phy_speed(status) == 0) {
556 printk
557 (KERN_INFO PFX "Link speed changed"
558 " to 10 Mbps\n");
559 netxen_niu_gbe_set_mii_mode(adapter,
560 port,
561 enable);
562 } else {
563 printk(KERN_ERR PFX "ERROR reading"
564 "PHY status. Illegal speed.\n");
565 result = -1;
566 }
567 } else {
568 printk(KERN_ERR PFX
569 "ERROR reading PHY status.\n");
570 result = -1;
571 }
572
573 }
574 printk(KERN_INFO "\n");
575 }
576 return result;
577 }
578
579 /*
580 * Return the current station MAC address.
581 * Note that the passed-in value must already be in network byte order.
582 */
583 int netxen_niu_macaddr_get(struct netxen_adapter *adapter,
584 int phy, netxen_ethernet_macaddr_t * addr)
585 {
586 u32 stationhigh;
587 u32 stationlow;
588 u8 val[8];
589
590 if (addr == NULL)
591 return -EINVAL;
592 if ((phy < 0) || (phy > 3))
593 return -EINVAL;
594
595 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy),
596 &stationhigh, 4))
597 return -EIO;
598 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy),
599 &stationlow, 4))
600 return -EIO;
601 ((__le32 *)val)[1] = cpu_to_le32(stationhigh);
602 ((__le32 *)val)[0] = cpu_to_le32(stationlow);
603
604 memcpy(addr, val + 2, 6);
605
606 return 0;
607 }
608
609 /*
610 * Set the station MAC address.
611 * Note that the passed-in value must already be in network byte order.
612 */
613 int netxen_niu_macaddr_set(struct netxen_port *port,
614 netxen_ethernet_macaddr_t addr)
615 {
616 u8 temp[4];
617 u32 val;
618 struct netxen_adapter *adapter = port->adapter;
619 int phy = port->portnum;
620 unsigned char mac_addr[6];
621 int i;
622
623 for (i = 0; i < 10; i++) {
624 temp[0] = temp[1] = 0;
625 memcpy(temp + 2, addr, 2);
626 val = le32_to_cpu(*(__le32 *)temp);
627 if (netxen_nic_hw_write_wx
628 (adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy), &val, 4))
629 return -EIO;
630
631 memcpy(temp, ((u8 *) addr) + 2, sizeof(__le32));
632 val = le32_to_cpu(*(__le32 *)temp);
633 if (netxen_nic_hw_write_wx
634 (adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy), &val, 4))
635 return -2;
636
637 netxen_niu_macaddr_get(adapter, phy,
638 (netxen_ethernet_macaddr_t *) mac_addr);
639 if (memcmp(mac_addr, addr, 6) == 0)
640 break;
641 }
642
643 if (i == 10) {
644 printk(KERN_ERR "%s: cannot set Mac addr for %s\n",
645 netxen_nic_driver_name, port->netdev->name);
646 printk(KERN_ERR "MAC address set: "
647 "%02x:%02x:%02x:%02x:%02x:%02x.\n",
648 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
649
650 printk(KERN_ERR "MAC address get: "
651 "%02x:%02x:%02x:%02x:%02x:%02x.\n",
652 mac_addr[0],
653 mac_addr[1],
654 mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
655 }
656 return 0;
657 }
658
659 /* Enable a GbE interface */
660 int netxen_niu_enable_gbe_port(struct netxen_adapter *adapter,
661 int port, netxen_niu_gbe_ifmode_t mode)
662 {
663 __u32 mac_cfg0;
664 __u32 mac_cfg1;
665 __u32 mii_cfg;
666
667 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
668 return -EINVAL;
669
670 mac_cfg0 = 0;
671 netxen_gb_soft_reset(mac_cfg0);
672 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
673 &mac_cfg0, 4))
674 return -EIO;
675 mac_cfg0 = 0;
676 netxen_gb_enable_tx(mac_cfg0);
677 netxen_gb_enable_rx(mac_cfg0);
678 netxen_gb_unset_rx_flowctl(mac_cfg0);
679 netxen_gb_tx_reset_pb(mac_cfg0);
680 netxen_gb_rx_reset_pb(mac_cfg0);
681 netxen_gb_tx_reset_mac(mac_cfg0);
682 netxen_gb_rx_reset_mac(mac_cfg0);
683
684 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
685 &mac_cfg0, 4))
686 return -EIO;
687 mac_cfg1 = 0;
688 netxen_gb_set_preamblelen(mac_cfg1, 0xf);
689 netxen_gb_set_duplex(mac_cfg1);
690 netxen_gb_set_crc_enable(mac_cfg1);
691 netxen_gb_set_padshort(mac_cfg1);
692 netxen_gb_set_checklength(mac_cfg1);
693 netxen_gb_set_hugeframes(mac_cfg1);
694
695 if (mode == NETXEN_NIU_10_100_MB) {
696 netxen_gb_set_intfmode(mac_cfg1, 1);
697 if (netxen_nic_hw_write_wx(adapter,
698 NETXEN_NIU_GB_MAC_CONFIG_1(port),
699 &mac_cfg1, 4))
700 return -EIO;
701
702 /* set mii mode */
703 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_GMII_MODE +
704 (port << 3), 0);
705 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_MII_MODE +
706 (port << 3), 1);
707
708 } else if (mode == NETXEN_NIU_1000_MB) {
709 netxen_gb_set_intfmode(mac_cfg1, 2);
710 if (netxen_nic_hw_write_wx(adapter,
711 NETXEN_NIU_GB_MAC_CONFIG_1(port),
712 &mac_cfg1, 4))
713 return -EIO;
714 /* set gmii mode */
715 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_MII_MODE +
716 (port << 3), 0);
717 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_GMII_MODE +
718 (port << 3), 1);
719 }
720 mii_cfg = 0;
721 netxen_gb_set_mii_mgmt_clockselect(mii_cfg, 7);
722 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port),
723 &mii_cfg, 4))
724 return -EIO;
725 mac_cfg0 = 0;
726 netxen_gb_enable_tx(mac_cfg0);
727 netxen_gb_enable_rx(mac_cfg0);
728 netxen_gb_unset_rx_flowctl(mac_cfg0);
729 netxen_gb_unset_tx_flowctl(mac_cfg0);
730
731 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
732 &mac_cfg0, 4))
733 return -EIO;
734 return 0;
735 }
736
737 /* Disable a GbE interface */
738 int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter, int port)
739 {
740 __u32 mac_cfg0;
741
742 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
743 return -EINVAL;
744
745 mac_cfg0 = 0;
746 netxen_gb_soft_reset(mac_cfg0);
747 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
748 &mac_cfg0, 4))
749 return -EIO;
750 return 0;
751 }
752
753 /* Disable an XG interface */
754 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter, int port)
755 {
756 __u32 mac_cfg;
757
758 if (port != 0)
759 return -EINVAL;
760
761 mac_cfg = 0;
762 netxen_xg_soft_reset(mac_cfg);
763 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_CONFIG_0,
764 &mac_cfg, 4))
765 return -EIO;
766 return 0;
767 }
768
769 /* Set promiscuous mode for a GbE interface */
770 int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter, int port,
771 netxen_niu_prom_mode_t mode)
772 {
773 __u32 reg;
774
775 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
776 return -EINVAL;
777
778 /* save previous contents */
779 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR,
780 &reg, 4))
781 return -EIO;
782 if (mode == NETXEN_NIU_PROMISC_MODE) {
783 switch (port) {
784 case 0:
785 netxen_clear_gb_drop_gb0(reg);
786 break;
787 case 1:
788 netxen_clear_gb_drop_gb1(reg);
789 break;
790 case 2:
791 netxen_clear_gb_drop_gb2(reg);
792 break;
793 case 3:
794 netxen_clear_gb_drop_gb3(reg);
795 break;
796 default:
797 return -EIO;
798 }
799 } else {
800 switch (port) {
801 case 0:
802 netxen_set_gb_drop_gb0(reg);
803 break;
804 case 1:
805 netxen_set_gb_drop_gb1(reg);
806 break;
807 case 2:
808 netxen_set_gb_drop_gb2(reg);
809 break;
810 case 3:
811 netxen_set_gb_drop_gb3(reg);
812 break;
813 default:
814 return -EIO;
815 }
816 }
817 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR,
818 &reg, 4))
819 return -EIO;
820 return 0;
821 }
822
823 /*
824 * Set the MAC address for an XG port
825 * Note that the passed-in value must already be in network byte order.
826 */
827 int netxen_niu_xg_macaddr_set(struct netxen_port *port,
828 netxen_ethernet_macaddr_t addr)
829 {
830 u8 temp[4];
831 u32 val;
832 struct netxen_adapter *adapter = port->adapter;
833
834 temp[0] = temp[1] = 0;
835 memcpy(temp + 2, addr, 2);
836 val = le32_to_cpu(*(__le32 *)temp);
837 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1,
838 &val, 4))
839 return -EIO;
840
841 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
842 val = le32_to_cpu(*(__le32 *)temp);
843 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI,
844 &val, 4))
845 return -EIO;
846
847 return 0;
848 }
849
850 /*
851 * Return the current station MAC address.
852 * Note that the passed-in value must already be in network byte order.
853 */
854 int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter, int phy,
855 netxen_ethernet_macaddr_t * addr)
856 {
857 u32 stationhigh;
858 u32 stationlow;
859 u8 val[8];
860
861 if (addr == NULL)
862 return -EINVAL;
863 if (phy != 0)
864 return -EINVAL;
865
866 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI,
867 &stationhigh, 4))
868 return -EIO;
869 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1,
870 &stationlow, 4))
871 return -EIO;
872 ((__le32 *)val)[1] = cpu_to_le32(stationhigh);
873 ((__le32 *)val)[0] = cpu_to_le32(stationlow);
874
875 memcpy(addr, val + 2, 6);
876
877 return 0;
878 }
879
880 int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
881 int port, netxen_niu_prom_mode_t mode)
882 {
883 __u32 reg;
884
885 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
886 return -EINVAL;
887
888 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_CONFIG_1, &reg, 4))
889 return -EIO;
890 if (mode == NETXEN_NIU_PROMISC_MODE)
891 reg = (reg | 0x2000UL);
892 else
893 reg = (reg & ~0x2000UL);
894
895 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_XGE_CONFIG_1, reg);
896
897 return 0;
898 }
Linux with added FPC-III support