Documentation/devicetree/bindings/arm/cpus.txt

   1 =================
   2 ARM CPUs bindings
   3 =================
   4
   5 The device tree allows to describe the layout of CPUs in a system through
   6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
   7 defining properties for every cpu.
   8
   9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
  10
  11 https://www.power.org/documentation/epapr-version-1-1/
  12
  13 with updates for 32-bit and 64-bit ARM systems provided in this document.
  14
  15 ================================
  16 Convention used in this document
  17 ================================
  18
  19 This document follows the conventions described in the ePAPR v1.1, with
  20 the addition:
  21
  22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
  23   the reg property contained in bits 7 down to 0
  24
  25 =====================================
  26 cpus and cpu node bindings definition
  27 =====================================
  28
  29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
  30 nodes to be present and contain the properties described below.
  31
  32 - cpus node
  33
  34         Description: Container of cpu nodes
  35
  36         The node name must be "cpus".
  37
  38         A cpus node must define the following properties:
  39
  40         - #address-cells
  41                 Usage: required
  42                 Value type: <u32>
  43
  44                 Definition depends on ARM architecture version and
  45                 configuration:
  46
  47                         # On uniprocessor ARM architectures previous to v7
  48                           value must be 1, to enable a simple enumeration
  49                           scheme for processors that do not have a HW CPU
  50                           identification register.
  51                         # On 32-bit ARM 11 MPcore, ARM v7 or later systems
  52                           value must be 1, that corresponds to CPUID/MPIDR
  53                           registers sizes.
  54                         # On ARM v8 64-bit systems value should be set to 2,
  55                           that corresponds to the MPIDR_EL1 register size.
  56                           If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
  57                           in the system, #address-cells can be set to 1, since
  58                           MPIDR_EL1[63:32] bits are not used for CPUs
  59                           identification.
  60         - #size-cells
  61                 Usage: required
  62                 Value type: <u32>
  63                 Definition: must be set to 0
  64
  65 - cpu node
  66
  67         Description: Describes a CPU in an ARM based system
  68
  69         PROPERTIES
  70
  71         - device_type
  72                 Usage: required
  73                 Value type: <string>
  74                 Definition: must be "cpu"
  75         - reg
  76                 Usage and definition depend on ARM architecture version and
  77                 configuration:
  78
  79                         # On uniprocessor ARM architectures previous to v7
  80                           this property is required and must be set to 0.
  81
  82                         # On ARM 11 MPcore based systems this property is
  83                           required and matches the CPUID[11:0] register bits.
  84
  85                           Bits [11:0] in the reg cell must be set to
  86                           bits [11:0] in CPU ID register.
  87
  88                           All other bits in the reg cell must be set to 0.
  89
  90                         # On 32-bit ARM v7 or later systems this property is
  91                           required and matches the CPU MPIDR[23:0] register
  92                           bits.
  93
  94                           Bits [23:0] in the reg cell must be set to
  95                           bits [23:0] in MPIDR.
  96
  97                           All other bits in the reg cell must be set to 0.
  98
  99                         # On ARM v8 64-bit systems this property is required
 100                           and matches the MPIDR_EL1 register affinity bits.
 101
 102                           * If cpus node's #address-cells property is set to 2
 103
 104                             The first reg cell bits [7:0] must be set to
 105                             bits [39:32] of MPIDR_EL1.
 106
 107                             The second reg cell bits [23:0] must be set to
 108                             bits [23:0] of MPIDR_EL1.
 109
 110                           * If cpus node's #address-cells property is set to 1
 111
 112                             The reg cell bits [23:0] must be set to bits [23:0]
 113                             of MPIDR_EL1.
 114
 115                           All other bits in the reg cells must be set to 0.
 116
 117         - compatible:
 118                 Usage: required
 119                 Value type: <string>
 120                 Definition: should be one of:
 121                             "arm,arm710t"
 122                             "arm,arm720t"
 123                             "arm,arm740t"
 124                             "arm,arm7ej-s"
 125                             "arm,arm7tdmi"
 126                             "arm,arm7tdmi-s"
 127                             "arm,arm9es"
 128                             "arm,arm9ej-s"
 129                             "arm,arm920t"
 130                             "arm,arm922t"
 131                             "arm,arm925"
 132                             "arm,arm926e-s"
 133                             "arm,arm926ej-s"
 134                             "arm,arm940t"
 135                             "arm,arm946e-s"
 136                             "arm,arm966e-s"
 137                             "arm,arm968e-s"
 138                             "arm,arm9tdmi"
 139                             "arm,arm1020e"
 140                             "arm,arm1020t"
 141                             "arm,arm1022e"
 142                             "arm,arm1026ej-s"
 143                             "arm,arm1136j-s"
 144                             "arm,arm1136jf-s"
 145                             "arm,arm1156t2-s"
 146                             "arm,arm1156t2f-s"
 147                             "arm,arm1176jzf"
 148                             "arm,arm1176jz-s"
 149                             "arm,arm1176jzf-s"
 150                             "arm,arm11mpcore"
 151                             "arm,cortex-a5"
 152                             "arm,cortex-a7"
 153                             "arm,cortex-a8"
 154                             "arm,cortex-a9"
 155                             "arm,cortex-a12"
 156                             "arm,cortex-a15"
 157                             "arm,cortex-a17"
 158                             "arm,cortex-a53"
 159                             "arm,cortex-a57"
 160                             "arm,cortex-a72"
 161                             "arm,cortex-m0"
 162                             "arm,cortex-m0+"
 163                             "arm,cortex-m1"
 164                             "arm,cortex-m3"
 165                             "arm,cortex-m4"
 166                             "arm,cortex-r4"
 167                             "arm,cortex-r5"
 168                             "arm,cortex-r7"
 169                             "brcm,brahma-b15"
 170                             "brcm,vulcan"
 171                             "cavium,thunder"
 172                             "faraday,fa526"
 173                             "intel,sa110"
 174                             "intel,sa1100"
 175                             "marvell,feroceon"
 176                             "marvell,mohawk"
 177                             "marvell,pj4a"
 178                             "marvell,pj4b"
 179                             "marvell,sheeva-v5"
 180                             "nvidia,tegra132-denver"
 181                             "qcom,krait"
 182                             "qcom,kryo"
 183                             "qcom,scorpion"
 184         - enable-method
 185                 Value type: <stringlist>
 186                 Usage and definition depend on ARM architecture version.
 187                         # On ARM v8 64-bit this property is required and must
 188                           be one of:
 189                              "psci"
 190                              "spin-table"
 191                         # On ARM 32-bit systems this property is optional and
 192                           can be one of:
 193                             "allwinner,sun6i-a31"
 194                             "allwinner,sun8i-a23"
 195                             "arm,psci"
 196                             "arm,realview-smp"
 197                             "brcm,bcm-nsp-smp"
 198                             "brcm,brahma-b15"
 199                             "marvell,armada-375-smp"
 200                             "marvell,armada-380-smp"
 201                             "marvell,armada-390-smp"
 202                             "marvell,armada-xp-smp"
 203                             "mediatek,mt6589-smp"
 204                             "mediatek,mt81xx-tz-smp"
 205                             "qcom,gcc-msm8660"
 206                             "qcom,kpss-acc-v1"
 207                             "qcom,kpss-acc-v2"
 208                             "rockchip,rk3036-smp"
 209                             "rockchip,rk3066-smp"
 210                             "ste,dbx500-smp"
 211
 212         - cpu-release-addr
 213                 Usage: required for systems that have an "enable-method"
 214                        property value of "spin-table".
 215                 Value type: <prop-encoded-array>
 216                 Definition:
 217                         # On ARM v8 64-bit systems must be a two cell
 218                           property identifying a 64-bit zero-initialised
 219                           memory location.
 220
 221         - qcom,saw
 222                 Usage: required for systems that have an "enable-method"
 223                        property value of "qcom,kpss-acc-v1" or
 224                        "qcom,kpss-acc-v2"
 225                 Value type: <phandle>
 226                 Definition: Specifies the SAW[1] node associated with this CPU.
 227
 228         - qcom,acc
 229                 Usage: required for systems that have an "enable-method"
 230                        property value of "qcom,kpss-acc-v1" or
 231                        "qcom,kpss-acc-v2"
 232                 Value type: <phandle>
 233                 Definition: Specifies the ACC[2] node associated with this CPU.
 234
 235         - cpu-idle-states
 236                 Usage: Optional
 237                 Value type: <prop-encoded-array>
 238                 Definition:
 239                         # List of phandles to idle state nodes supported
 240                           by this cpu [3].
 241
 242         - rockchip,pmu
 243                 Usage: optional for systems that have an "enable-method"
 244                        property value of "rockchip,rk3066-smp"
 245                        While optional, it is the preferred way to get access to
 246                        the cpu-core power-domains.
 247                 Value type: <phandle>
 248                 Definition: Specifies the syscon node controlling the cpu core
 249                             power domains.
 250
 251         - dynamic-power-coefficient
 252                 Usage: optional
 253                 Value type: <prop-encoded-array>
 254                 Definition: A u32 value that represents the running time dynamic
 255                             power coefficient in units of mW/MHz/uV^2. The
 256                             coefficient can either be calculated from power
 257                             measurements or derived by analysis.
 258
 259                             The dynamic power consumption of the CPU  is
 260                             proportional to the square of the Voltage (V) and
 261                             the clock frequency (f). The coefficient is used to
 262                             calculate the dynamic power as below -
 263
 264                             Pdyn = dynamic-power-coefficient * V^2 * f
 265
 266                             where voltage is in uV, frequency is in MHz.
 267
 268 Example 1 (dual-cluster big.LITTLE system 32-bit):
 269
 270         cpus {
 271                 #size-cells = <0>;
 272                 #address-cells = <1>;
 273
 274                 cpu@0 {
 275                         device_type = "cpu";
 276                         compatible = "arm,cortex-a15";
 277                         reg = <0x0>;
 278                 };
 279
 280                 cpu@1 {
 281                         device_type = "cpu";
 282                         compatible = "arm,cortex-a15";
 283                         reg = <0x1>;
 284                 };
 285
 286                 cpu@100 {
 287                         device_type = "cpu";
 288                         compatible = "arm,cortex-a7";
 289                         reg = <0x100>;
 290                 };
 291
 292                 cpu@101 {
 293                         device_type = "cpu";
 294                         compatible = "arm,cortex-a7";
 295                         reg = <0x101>;
 296                 };
 297         };
 298
 299 Example 2 (Cortex-A8 uniprocessor 32-bit system):
 300
 301         cpus {
 302                 #size-cells = <0>;
 303                 #address-cells = <1>;
 304
 305                 cpu@0 {
 306                         device_type = "cpu";
 307                         compatible = "arm,cortex-a8";
 308                         reg = <0x0>;
 309                 };
 310         };
 311
 312 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
 313
 314         cpus {
 315                 #size-cells = <0>;
 316                 #address-cells = <1>;
 317
 318                 cpu@0 {
 319                         device_type = "cpu";
 320                         compatible = "arm,arm926ej-s";
 321                         reg = <0x0>;
 322                 };
 323         };
 324
 325 Example 4 (ARM Cortex-A57 64-bit system):
 326
 327 cpus {
 328         #size-cells = <0>;
 329         #address-cells = <2>;
 330
 331         cpu@0 {
 332                 device_type = "cpu";
 333                 compatible = "arm,cortex-a57";
 334                 reg = <0x0 0x0>;
 335                 enable-method = "spin-table";
 336                 cpu-release-addr = <0 0x20000000>;
 337         };
 338
 339         cpu@1 {
 340                 device_type = "cpu";
 341                 compatible = "arm,cortex-a57";
 342                 reg = <0x0 0x1>;
 343                 enable-method = "spin-table";
 344                 cpu-release-addr = <0 0x20000000>;
 345         };
 346
 347         cpu@100 {
 348                 device_type = "cpu";
 349                 compatible = "arm,cortex-a57";
 350                 reg = <0x0 0x100>;
 351                 enable-method = "spin-table";
 352                 cpu-release-addr = <0 0x20000000>;
 353         };
 354
 355         cpu@101 {
 356                 device_type = "cpu";
 357                 compatible = "arm,cortex-a57";
 358                 reg = <0x0 0x101>;
 359                 enable-method = "spin-table";
 360                 cpu-release-addr = <0 0x20000000>;
 361         };
 362
 363         cpu@10000 {
 364                 device_type = "cpu";
 365                 compatible = "arm,cortex-a57";
 366                 reg = <0x0 0x10000>;
 367                 enable-method = "spin-table";
 368                 cpu-release-addr = <0 0x20000000>;
 369         };
 370
 371         cpu@10001 {
 372                 device_type = "cpu";
 373                 compatible = "arm,cortex-a57";
 374                 reg = <0x0 0x10001>;
 375                 enable-method = "spin-table";
 376                 cpu-release-addr = <0 0x20000000>;
 377         };
 378
 379         cpu@10100 {
 380                 device_type = "cpu";
 381                 compatible = "arm,cortex-a57";
 382                 reg = <0x0 0x10100>;
 383                 enable-method = "spin-table";
 384                 cpu-release-addr = <0 0x20000000>;
 385         };
 386
 387         cpu@10101 {
 388                 device_type = "cpu";
 389                 compatible = "arm,cortex-a57";
 390                 reg = <0x0 0x10101>;
 391                 enable-method = "spin-table";
 392                 cpu-release-addr = <0 0x20000000>;
 393         };
 394
 395         cpu@100000000 {
 396                 device_type = "cpu";
 397                 compatible = "arm,cortex-a57";
 398                 reg = <0x1 0x0>;
 399                 enable-method = "spin-table";
 400                 cpu-release-addr = <0 0x20000000>;
 401         };
 402
 403         cpu@100000001 {
 404                 device_type = "cpu";
 405                 compatible = "arm,cortex-a57";
 406                 reg = <0x1 0x1>;
 407                 enable-method = "spin-table";
 408                 cpu-release-addr = <0 0x20000000>;
 409         };
 410
 411         cpu@100000100 {
 412                 device_type = "cpu";
 413                 compatible = "arm,cortex-a57";
 414                 reg = <0x1 0x100>;
 415                 enable-method = "spin-table";
 416                 cpu-release-addr = <0 0x20000000>;
 417         };
 418
 419         cpu@100000101 {
 420                 device_type = "cpu";
 421                 compatible = "arm,cortex-a57";
 422                 reg = <0x1 0x101>;
 423                 enable-method = "spin-table";
 424                 cpu-release-addr = <0 0x20000000>;
 425         };
 426
 427         cpu@100010000 {
 428                 device_type = "cpu";
 429                 compatible = "arm,cortex-a57";
 430                 reg = <0x1 0x10000>;
 431                 enable-method = "spin-table";
 432                 cpu-release-addr = <0 0x20000000>;
 433         };
 434
 435         cpu@100010001 {
 436                 device_type = "cpu";
 437                 compatible = "arm,cortex-a57";
 438                 reg = <0x1 0x10001>;
 439                 enable-method = "spin-table";
 440                 cpu-release-addr = <0 0x20000000>;
 441         };
 442
 443         cpu@100010100 {
 444                 device_type = "cpu";
 445                 compatible = "arm,cortex-a57";
 446                 reg = <0x1 0x10100>;
 447                 enable-method = "spin-table";
 448                 cpu-release-addr = <0 0x20000000>;
 449         };
 450
 451         cpu@100010101 {
 452                 device_type = "cpu";
 453                 compatible = "arm,cortex-a57";
 454                 reg = <0x1 0x10101>;
 455                 enable-method = "spin-table";
 456                 cpu-release-addr = <0 0x20000000>;
 457         };
 458 };
 459
 460 --
 461 [1] arm/msm/qcom,saw2.txt
 462 [2] arm/msm/qcom,kpss-acc.txt
 463 [3] ARM Linux kernel documentation - idle states bindings
 464     Documentation/devicetree/bindings/arm/idle-states.txt