4 compatible = "brcm,bcm7346";
10 mips-hpt-frequency = <163125000>;
13 compatible = "brcm,bmips5000";
19 compatible = "brcm,bmips5000";
33 compatible = "mti,cpu-interrupt-controller";
36 #interrupt-cells = <1>;
41 compatible = "fixed-clock";
43 clock-frequency = <81000000>;
51 compatible = "simple-bus";
52 ranges = <0 0x10000000 0x01000000>;
54 periph_intc: periph_intc@411400 {
55 compatible = "brcm,bcm7038-l1-intc";
56 reg = <0x411400 0x30>, <0x411600 0x30>;
59 #interrupt-cells = <1>;
61 interrupt-parent = <&cpu_intc>;
62 interrupts = <2>, <3>;
65 sun_l2_intc: sun_l2_intc@403000 {
66 compatible = "brcm,l2-intc";
67 reg = <0x403000 0x30>;
69 #interrupt-cells = <1>;
70 interrupt-parent = <&periph_intc>;
75 compatible = "brcm,bcm7400-gisb-arb";
76 reg = <0x400000 0xdc>;
78 interrupt-parent = <&sun_l2_intc>;
79 interrupts = <0>, <2>;
80 brcm,gisb-arb-master-mask = <0x673>;
81 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
86 upg_irq0_intc: upg_irq0_intc@406780 {
87 compatible = "brcm,bcm7120-l2-intc";
90 brcm,int-map-mask = <0x44>, <0xf000000>;
91 brcm,int-fwd-mask = <0x70000>;
94 #interrupt-cells = <1>;
96 interrupt-parent = <&periph_intc>;
97 interrupts = <59>, <57>;
98 interrupt-names = "upg_main", "upg_bsc";
101 upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
102 compatible = "brcm,bcm7120-l2-intc";
103 reg = <0x408b80 0x8>;
105 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
106 brcm,int-fwd-mask = <0>;
109 interrupt-controller;
110 #interrupt-cells = <1>;
112 interrupt-parent = <&periph_intc>;
113 interrupts = <60>, <58>, <62>;
114 interrupt-names = "upg_main_aon", "upg_bsc_aon",
118 sun_top_ctrl: syscon@404000 {
119 compatible = "brcm,bcm7346-sun-top-ctrl", "syscon";
120 reg = <0x404000 0x51c>;
125 compatible = "brcm,brcmstb-reboot";
126 syscon = <&sun_top_ctrl 0x304 0x308>;
129 uart0: serial@406900 {
130 compatible = "ns16550a";
131 reg = <0x406900 0x20>;
132 reg-io-width = <0x4>;
135 interrupt-parent = <&periph_intc>;
137 clocks = <&uart_clk>;
141 uart1: serial@406940 {
142 compatible = "ns16550a";
143 reg = <0x406940 0x20>;
144 reg-io-width = <0x4>;
147 interrupt-parent = <&periph_intc>;
149 clocks = <&uart_clk>;
153 uart2: serial@406980 {
154 compatible = "ns16550a";
155 reg = <0x406980 0x20>;
156 reg-io-width = <0x4>;
159 interrupt-parent = <&periph_intc>;
161 clocks = <&uart_clk>;
166 clock-frequency = <390000>;
167 compatible = "brcm,brcmstb-i2c";
168 interrupt-parent = <&upg_irq0_intc>;
169 reg = <0x406200 0x58>;
171 interrupt-names = "upg_bsca";
176 clock-frequency = <390000>;
177 compatible = "brcm,brcmstb-i2c";
178 interrupt-parent = <&upg_irq0_intc>;
179 reg = <0x406280 0x58>;
181 interrupt-names = "upg_bscb";
186 clock-frequency = <390000>;
187 compatible = "brcm,brcmstb-i2c";
188 interrupt-parent = <&upg_irq0_intc>;
189 reg = <0x406300 0x58>;
191 interrupt-names = "upg_bscc";
196 clock-frequency = <390000>;
197 compatible = "brcm,brcmstb-i2c";
198 interrupt-parent = <&upg_irq0_intc>;
199 reg = <0x406380 0x58>;
201 interrupt-names = "upg_bscd";
206 clock-frequency = <390000>;
207 compatible = "brcm,brcmstb-i2c";
208 interrupt-parent = <&upg_aon_irq0_intc>;
209 reg = <0x408980 0x58>;
211 interrupt-names = "upg_bsce";
215 enet0: ethernet@430000 {
216 phy-mode = "internal";
217 phy-handle = <&phy1>;
218 mac-address = [ 00 10 18 36 23 1a ];
219 compatible = "brcm,genet-v2";
220 #address-cells = <0x1>;
222 reg = <0x430000 0x4c8c>;
223 interrupts = <24>, <25>;
224 interrupt-parent = <&periph_intc>;
228 compatible = "brcm,genet-mdio-v2";
229 #address-cells = <0x1>;
233 phy1: ethernet-phy@1 {
236 compatible = "brcm,40nm-ephy",
237 "ethernet-phy-ieee802.3-c22";
243 compatible = "brcm,bcm7346-ehci", "generic-ehci";
244 reg = <0x480300 0x100>;
246 interrupt-parent = <&periph_intc>;
252 compatible = "brcm,bcm7346-ohci", "generic-ohci";
253 reg = <0x480400 0x100>;
256 interrupt-parent = <&periph_intc>;
262 compatible = "brcm,bcm7346-ehci", "generic-ehci";
263 reg = <0x480500 0x100>;
265 interrupt-parent = <&periph_intc>;
271 compatible = "brcm,bcm7346-ohci", "generic-ohci";
272 reg = <0x480600 0x100>;
275 interrupt-parent = <&periph_intc>;
281 compatible = "brcm,bcm7346-ehci", "generic-ehci";
282 reg = <0x490300 0x100>;
284 interrupt-parent = <&periph_intc>;
290 compatible = "brcm,bcm7346-ohci", "generic-ohci";
291 reg = <0x490400 0x100>;
294 interrupt-parent = <&periph_intc>;
300 compatible = "brcm,bcm7346-ehci", "generic-ehci";
301 reg = <0x490500 0x100>;
303 interrupt-parent = <&periph_intc>;
309 compatible = "brcm,bcm7346-ohci", "generic-ohci";
310 reg = <0x490600 0x100>;
313 interrupt-parent = <&periph_intc>;
319 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
320 reg-names = "ahci", "top-ctrl";
321 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
322 interrupt-parent = <&periph_intc>;
324 #address-cells = <1>;
341 sata_phy: sata-phy@1800000 {
342 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
343 reg = <0x180100 0x0eff>;
345 #address-cells = <1>;
349 sata_phy0: sata-phy@0 {
354 sata_phy1: sata-phy@1 {