arch/powerpc/boot/dts/charon.dts

   1 /*
   2  * charon board Device Tree Source
   3  *
   4  * Copyright (C) 2007 Semihalf
   5  * Marian Balakowicz <m8@semihalf.com>
   6  *
   7  * Copyright (C) 2010 DENX Software Engineering GmbH
   8  * Heiko Schocher <hs@denx.de>
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 /dts-v1/;
  17
  18 / {
  19         model = "anon,charon";
  20         compatible = "anon,charon";
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23         interrupt-parent = <&mpc5200_pic>;
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 PowerPC,5200@0 {
  30                         device_type = "cpu";
  31                         reg = <0>;
  32                         d-cache-line-size = <32>;
  33                         i-cache-line-size = <32>;
  34                         d-cache-size = <0x4000>;        // L1, 16K
  35                         i-cache-size = <0x4000>;        // L1, 16K
  36                         timebase-frequency = <0>;       // from bootloader
  37                         bus-frequency = <0>;            // from bootloader
  38                         clock-frequency = <0>;          // from bootloader
  39                 };
  40         };
  41
  42         memory {
  43                 device_type = "memory";
  44                 reg = <0x00000000 0x08000000>;  // 128MB
  45         };
  46
  47         soc5200@f0000000 {
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 compatible = "fsl,mpc5200-immr";
  51                 ranges = <0 0xf0000000 0x0000c000>;
  52                 reg = <0xf0000000 0x00000100>;
  53                 bus-frequency = <0>;            // from bootloader
  54                 system-frequency = <0>;         // from bootloader
  55
  56                 cdm@200 {
  57                         compatible = "fsl,mpc5200-cdm";
  58                         reg = <0x200 0x38>;
  59                 };
  60
  61                 mpc5200_pic: interrupt-controller@500 {
  62                         // 5200 interrupts are encoded into two levels;
  63                         interrupt-controller;
  64                         #interrupt-cells = <3>;
  65                         compatible = "fsl,mpc5200-pic";
  66                         reg = <0x500 0x80>;
  67                 };
  68
  69                 timer@600 {     // General Purpose Timer
  70                         compatible = "fsl,mpc5200-gpt";
  71                         reg = <0x600 0x10>;
  72                         interrupts = <1 9 0>;
  73                         fsl,has-wdt;
  74                 };
  75
  76                 can@900 {
  77                         compatible = "fsl,mpc5200-mscan";
  78                         interrupts = <2 17 0>;
  79                         reg = <0x900 0x80>;
  80                 };
  81
  82                 can@980 {
  83                         compatible = "fsl,mpc5200-mscan";
  84                         interrupts = <2 18 0>;
  85                         reg = <0x980 0x80>;
  86                 };
  87
  88                 gpio_simple: gpio@b00 {
  89                         compatible = "fsl,mpc5200-gpio";
  90                         reg = <0xb00 0x40>;
  91                         interrupts = <1 7 0>;
  92                         gpio-controller;
  93                         #gpio-cells = <2>;
  94                 };
  95
  96                 usb@1000 {
  97                         compatible = "fsl,mpc5200-ohci","ohci-be";
  98                         reg = <0x1000 0xff>;
  99                         interrupts = <2 6 0>;
 100                 };
 101
 102                 dma-controller@1200 {
 103                         device_type = "dma-controller";
 104                         compatible = "fsl,mpc5200-bestcomm";
 105                         reg = <0x1200 0x80>;
 106                         interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
 107                                       3 4 0  3 5 0  3 6 0  3 7 0
 108                                       3 8 0  3 9 0  3 10 0  3 11 0
 109                                       3 12 0  3 13 0  3 14 0  3 15 0>;
 110                 };
 111
 112                 xlb@1f00 {
 113                         compatible = "fsl,mpc5200-xlb";
 114                         reg = <0x1f00 0x100>;
 115                 };
 116
 117                 serial@2000 {           // PSC1
 118                         compatible = "fsl,mpc5200-psc-uart";
 119                         reg = <0x2000 0x100>;
 120                         interrupts = <2 1 0>;
 121                 };
 122
 123                 serial@2400 {           // PSC3
 124                         compatible = "fsl,mpc5200-psc-uart";
 125                         reg = <0x2400 0x100>;
 126                         interrupts = <2 3 0>;
 127                 };
 128
 129                 ethernet@3000 {
 130                         compatible = "fsl,mpc5200-fec";
 131                         reg = <0x3000 0x400>;
 132                         local-mac-address = [ 00 00 00 00 00 00 ];
 133                         interrupts = <2 5 0>;
 134                         fixed-link = <1 1 100 0 0>;
 135                 };
 136
 137                 mdio@3000 {
 138                         #address-cells = <1>;
 139                         #size-cells = <0>;
 140                         compatible = "fsl,mpc5200-mdio";
 141                         reg = <0x3000 0x400>;       // fec range, since we need to setup fec interrupts
 142                         interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
 143                 };
 144
 145                 ata@3a00 {
 146                         compatible = "fsl,mpc5200-ata";
 147                         reg = <0x3a00 0x100>;
 148                         interrupts = <2 7 0>;
 149                 };
 150
 151                 i2c@3d00 {
 152                         #address-cells = <1>;
 153                         #size-cells = <0>;
 154                         compatible = "fsl,mpc5200-i2c","fsl-i2c";
 155                         reg = <0x3d00 0x40>;
 156                         interrupts = <2 15 0>;
 157                 };
 158
 159
 160                 i2c@3d40 {
 161                         #address-cells = <1>;
 162                         #size-cells = <0>;
 163                         compatible = "fsl,mpc5200-i2c","fsl-i2c";
 164                         reg = <0x3d40 0x40>;
 165                         interrupts = <2 16 0>;
 166
 167                         dtt@28 {
 168                                 compatible = "national,lm80";
 169                                 reg = <0x28>;
 170                         };
 171
 172                         rtc@68 {
 173                                 compatible = "dallas,ds1374";
 174                                 reg = <0x68>;
 175                         };
 176                 };
 177
 178                 sram@8000 {
 179                         compatible = "fsl,mpc5200-sram";
 180                         reg = <0x8000 0x4000>;
 181                 };
 182         };
 183
 184         localbus {
 185                 compatible = "fsl,mpc5200-lpb","simple-bus";
 186                 #address-cells = <2>;
 187                 #size-cells = <1>;
 188                 ranges = <      0 0 0xfc000000 0x02000000
 189                                 1 0 0xe0000000 0x04000000 // CS1 range, SM501
 190                                 3 0 0xe8000000 0x00080000>;
 191
 192                 flash@0,0 {
 193                         compatible = "cfi-flash";
 194                         reg = <0 0 0x02000000>;
 195                         bank-width = <4>;
 196                         device-width = <2>;
 197                         #size-cells = <1>;
 198                         #address-cells = <1>;
 199                 };
 200
 201                 display@1,0 {
 202                         compatible = "smi,sm501";
 203                         reg = <1 0x00000000 0x00800000
 204                                1 0x03e00000 0x00200000>;
 205                         mode = "640x480-32@60";
 206                         interrupts = <1 1 3>;
 207                         little-endian;
 208                 };
 209
 210                 mram0@3,0 {
 211                         compatible = "mtd-ram";
 212                         reg = <3 0x00000 0x80000>;
 213                         bank-width = <1>;
 214                 };
 215         };
 216
 217         pci@f0000d00 {
 218                 #interrupt-cells = <1>;
 219                 #size-cells = <2>;
 220                 #address-cells = <3>;
 221                 device_type = "pci";
 222                 compatible = "fsl,mpc5200-pci";
 223                 reg = <0xf0000d00 0x100>;
 224                 interrupt-map-mask = <0xf800 0 0 7>;
 225                 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
 226                                  0xc000 0 0 2 &mpc5200_pic 0 0 3
 227                                  0xc000 0 0 3 &mpc5200_pic 0 0 3
 228                                  0xc000 0 0 4 &mpc5200_pic 0 0 3>;
 229                 clock-frequency = <0>; // From boot loader
 230                 interrupts = <2 8 0 2 9 0 2 10 0>;
 231                 bus-range = <0 0>;
 232                 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
 233                           0x02000000 0 0x90000000 0x90000000 0 0x10000000
 234                           0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
 235         };
 236 };