thermal: fix Mediatek thermal controller build
[linux/fpc-iii.git] / arch / powerpc / boot / dts / mpc5121ads.dts
blobc228a0a232a652357355646a8b90706d3d7e14cc
1 /*
2  * MPC5121E ADS Device Tree Source
3  *
4  * Copyright 2007-2008 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
12 #include <mpc5121.dtsi>
14 / {
15         model = "mpc5121ads";
16         compatible = "fsl,mpc5121ads", "fsl,mpc5121";
18         nfc@40000000 {
19                 /*
20                  * ADS has two Hynix 512MB Nand flash chips in a single
21                  * stacked package.
22                  */
23                 chips = <2>;
25                 nand@0 {
26                         label = "nand";
27                         reg = <0x00000000 0x40000000>;  /* 512MB + 512MB */
28                 };
29         };
31         localbus@80000020 {
32                 ranges = <0x0 0x0 0xfc000000 0x04000000
33                           0x2 0x0 0x82000000 0x00008000>;
35                 flash@0,0 {
36                         compatible = "cfi-flash";
37                         reg = <0 0x0 0x4000000>;
38                         #address-cells = <1>;
39                         #size-cells = <1>;
40                         bank-width = <4>;
41                         device-width = <2>;
43                         protected@0 {
44                                 label = "protected";
45                                 reg = <0x00000000 0x00040000>;  // first sector is protected
46                                 read-only;
47                         };
48                         filesystem@40000 {
49                                 label = "filesystem";
50                                 reg = <0x00040000 0x03c00000>;  // 60M for filesystem
51                         };
52                         kernel@3c40000 {
53                                 label = "kernel";
54                                 reg = <0x03c40000 0x00280000>;  // 2.5M for kernel
55                         };
56                         device-tree@3ec0000 {
57                                 label = "device-tree";
58                                 reg = <0x03ec0000 0x00040000>;  // one sector for device tree
59                         };
60                         u-boot@3f00000 {
61                                 label = "u-boot";
62                                 reg = <0x03f00000 0x00100000>;  // 1M for u-boot
63                                 read-only;
64                         };
65                 };
67                 board-control@2,0 {
68                         compatible = "fsl,mpc5121ads-cpld";
69                         reg = <0x2 0x0 0x8000>;
70                 };
72                 cpld_pic: pic@2,a {
73                         compatible = "fsl,mpc5121ads-cpld-pic";
74                         interrupt-controller;
75                         #interrupt-cells = <2>;
76                         reg = <0x2 0xa 0x5>;
77                         /* irq routing:
78                          * all irqs but touch screen are routed to irq0 (ipic 48)
79                          * touch screen is statically routed to irq1 (ipic 17)
80                          * so don't use it here
81                          */
82                         interrupts = <48 0x8>;
83                 };
84         };
86         soc@80000000 {
88                 i2c@1700 {
89                         fsl,preserve-clocking;
91                         hwmon@4a {
92                                 compatible = "adi,ad7414";
93                                 reg = <0x4a>;
94                         };
96                         eeprom@50 {
97                                 compatible = "at,24c32";
98                                 reg = <0x50>;
99                         };
101                         rtc@68 {
102                                 compatible = "stm,m41t62";
103                                 reg = <0x68>;
104                         };
105                 };
107                 eth0: ethernet@2800 {
108                         phy-handle = <&phy0>;
109                 };
111                 can@2300 {
112                         status = "disabled";
113                 };
115                 can@2380 {
116                         status = "disabled";
117                 };
119                 viu@2400 {
120                         status = "disabled";
121                 };
123                 mdio@2800 {
124                         phy0: ethernet-phy@0 {
125                                 reg = <1>;
126                         };
127                 };
129                 /* mpc5121ads only uses USB0 */
130                 usb@3000 {
131                         status = "disabled";
132                 };
134                 /* USB0 using internal UTMI PHY */
135                 usb@4000 {
136                         dr_mode = "host";
137                         fsl,invert-drvvbus;
138                         fsl,invert-pwr-fault;
139                 };
141                 /* PSC3 serial port A aka ttyPSC0 */
142                 psc@11300 {
143                         compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
144                 };
146                 /* PSC4 serial port B aka ttyPSC1 */
147                 psc@11400 {
148                         compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
149                 };
151                 /* PSC5 in ac97 mode */
152                 ac97: psc@11500 {
153                         compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";
154                         fsl,mode = "ac97-slave";
155                         fsl,rx-fifo-size = <384>;
156                         fsl,tx-fifo-size = <384>;
157                 };
158         };
160         pci: pci@80008500 {
161                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
162                 interrupt-map = <
163                                 /* IDSEL 0x15 - Slot 1 PCI */
164                                  0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8
165                                  0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8
166                                  0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8
167                                  0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8
169                                 /* IDSEL 0x16 - Slot 2 MiniPCI */
170                                  0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8
171                                  0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8
173                                 /* IDSEL 0x17 - Slot 3 MiniPCI */
174                                  0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8
175                                  0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8
176                                 >;
177         };