5 * This file contains the definitions for the x86 IO instructions
6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
8 * versions of the single-IO instructions (inb_p/inw_p/..).
10 * This file is not meant to be obfuscating: it's just complicated
11 * to (a) handle it all in a way that makes gcc able to optimize it
12 * as well as possible and (b) trying to avoid writing the same thing
13 * over and over again with slight variations and possibly making a
18 * Thanks to James van Artsdalen for a better timing-fix than
19 * the two short jumps: using outb's to a nonexistent port seems
20 * to guarantee better timings even on fast machines.
22 * On the other hand, I'd like to be sure of a non-existent port:
23 * I feel a bit unsafe about using 0x80 (should be safe, though)
29 * Bit simplified and optimized by Jan Hubicka
30 * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
32 * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
33 * isa_read[wl] and isa_write[wl] fixed
34 * - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
37 #define ARCH_HAS_IOREMAP_WC
38 #define ARCH_HAS_IOREMAP_WT
40 #include <linux/string.h>
41 #include <linux/compiler.h>
43 #include <asm/early_ioremap.h>
44 #include <asm/pgtable_types.h>
46 #define build_mmio_read(name, size, type, reg, barrier) \
47 static inline type name(const volatile void __iomem *addr) \
48 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \
49 :"m" (*(volatile type __force *)addr) barrier); return ret; }
51 #define build_mmio_write(name, size, type, reg, barrier) \
52 static inline void name(type val, volatile void __iomem *addr) \
53 { asm volatile("mov" size " %0,%1": :reg (val), \
54 "m" (*(volatile type __force *)addr) barrier); }
56 build_mmio_read(readb
, "b", unsigned char, "=q", :"memory")
57 build_mmio_read(readw
, "w", unsigned short, "=r", :"memory")
58 build_mmio_read(readl
, "l", unsigned int, "=r", :"memory")
60 build_mmio_read(__readb
, "b", unsigned char, "=q", )
61 build_mmio_read(__readw
, "w", unsigned short, "=r", )
62 build_mmio_read(__readl
, "l", unsigned int, "=r", )
64 build_mmio_write(writeb
, "b", unsigned char, "q", :"memory")
65 build_mmio_write(writew
, "w", unsigned short, "r", :"memory")
66 build_mmio_write(writel
, "l", unsigned int, "r", :"memory")
68 build_mmio_write(__writeb
, "b", unsigned char, "q", )
69 build_mmio_write(__writew
, "w", unsigned short, "r", )
70 build_mmio_write(__writel
, "l", unsigned int, "r", )
72 #define readb_relaxed(a) __readb(a)
73 #define readw_relaxed(a) __readw(a)
74 #define readl_relaxed(a) __readl(a)
75 #define __raw_readb __readb
76 #define __raw_readw __readw
77 #define __raw_readl __readl
79 #define writeb_relaxed(v, a) __writeb(v, a)
80 #define writew_relaxed(v, a) __writew(v, a)
81 #define writel_relaxed(v, a) __writel(v, a)
82 #define __raw_writeb __writeb
83 #define __raw_writew __writew
84 #define __raw_writel __writel
86 #define mmiowb() barrier()
90 build_mmio_read(readq
, "q", unsigned long, "=r", :"memory")
91 build_mmio_write(writeq
, "q", unsigned long, "r", :"memory")
93 #define readq_relaxed(a) readq(a)
94 #define writeq_relaxed(v, a) writeq(v, a)
96 #define __raw_readq(a) readq(a)
97 #define __raw_writeq(val, addr) writeq(val, addr)
99 /* Let people know that we have them */
101 #define writeq writeq
106 * virt_to_phys - map virtual addresses to physical
107 * @address: address to remap
109 * The returned physical address is the physical (CPU) mapping for
110 * the memory address given. It is only valid to use this function on
111 * addresses directly mapped or allocated via kmalloc.
113 * This function does not give bus mappings for DMA transfers. In
114 * almost all conceivable cases a device driver should not be using
118 static inline phys_addr_t
virt_to_phys(volatile void *address
)
120 return __pa(address
);
124 * phys_to_virt - map physical address to virtual
125 * @address: address to remap
127 * The returned virtual address is a current CPU mapping for
128 * the memory address given. It is only valid to use this function on
129 * addresses that have a kernel mapping
131 * This function does not handle bus mappings for DMA transfers. In
132 * almost all conceivable cases a device driver should not be using
136 static inline void *phys_to_virt(phys_addr_t address
)
138 return __va(address
);
142 * Change "struct page" to physical address.
144 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
147 * ISA I/O bus memory addresses are 1:1 with the physical address.
148 * However, we truncate the address to unsigned int to avoid undesirable
149 * promitions in legacy drivers.
151 static inline unsigned int isa_virt_to_bus(volatile void *address
)
153 return (unsigned int)virt_to_phys(address
);
155 #define isa_page_to_bus(page) ((unsigned int)page_to_phys(page))
156 #define isa_bus_to_virt phys_to_virt
159 * However PCI ones are not necessarily 1:1 and therefore these interfaces
160 * are forbidden in portable PCI drivers.
162 * Allow them on x86 for legacy drivers, though.
164 #define virt_to_bus virt_to_phys
165 #define bus_to_virt phys_to_virt
168 * ioremap - map bus memory into CPU space
169 * @offset: bus address of the memory
170 * @size: size of the resource to map
172 * ioremap performs a platform specific sequence of operations to
173 * make bus memory CPU accessible via the readb/readw/readl/writeb/
174 * writew/writel functions and the other mmio helpers. The returned
175 * address is not guaranteed to be usable directly as a virtual
178 * If the area you are trying to map is a PCI BAR you should have a
179 * look at pci_iomap().
181 extern void __iomem
*ioremap_nocache(resource_size_t offset
, unsigned long size
);
182 extern void __iomem
*ioremap_uc(resource_size_t offset
, unsigned long size
);
183 #define ioremap_uc ioremap_uc
185 extern void __iomem
*ioremap_cache(resource_size_t offset
, unsigned long size
);
186 extern void __iomem
*ioremap_prot(resource_size_t offset
, unsigned long size
,
187 unsigned long prot_val
);
190 * The default ioremap() behavior is non-cached:
192 static inline void __iomem
*ioremap(resource_size_t offset
, unsigned long size
)
194 return ioremap_nocache(offset
, size
);
197 extern void iounmap(volatile void __iomem
*addr
);
199 extern void set_iounmap_nonlazy(void);
203 #include <asm-generic/iomap.h>
206 * Convert a virtual cached pointer to an uncached pointer
208 #define xlate_dev_kmem_ptr(p) p
211 memset_io(volatile void __iomem
*addr
, unsigned char val
, size_t count
)
213 memset((void __force
*)addr
, val
, count
);
217 memcpy_fromio(void *dst
, const volatile void __iomem
*src
, size_t count
)
219 memcpy(dst
, (const void __force
*)src
, count
);
223 memcpy_toio(volatile void __iomem
*dst
, const void *src
, size_t count
)
225 memcpy((void __force
*)dst
, src
, count
);
229 * ISA space is 'always mapped' on a typical x86 system, no need to
230 * explicitly ioremap() it. The fact that the ISA IO space is mapped
231 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
232 * are physical addresses. The following constant pointer can be
233 * used as the IO-area pointer (it can be iounmapped as well, so the
234 * analogy with PCI is quite large):
236 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
241 * This needed for two cases
242 * 1. Out of order aware processors
243 * 2. Accidentally out of order processors (PPro errata #51)
246 static inline void flush_write_buffers(void)
248 #if defined(CONFIG_X86_PPRO_FENCE)
249 asm volatile("lock; addl $0,0(%%esp)": : :"memory");
253 #endif /* __KERNEL__ */
255 extern void native_io_delay(void);
257 extern int io_delay_type
;
258 extern void io_delay_init(void);
260 #if defined(CONFIG_PARAVIRT)
261 #include <asm/paravirt.h>
264 static inline void slow_down_io(void)
267 #ifdef REALLY_SLOW_IO
276 #define BUILDIO(bwl, bw, type) \
277 static inline void out##bwl(unsigned type value, int port) \
279 asm volatile("out" #bwl " %" #bw "0, %w1" \
280 : : "a"(value), "Nd"(port)); \
283 static inline unsigned type in##bwl(int port) \
285 unsigned type value; \
286 asm volatile("in" #bwl " %w1, %" #bw "0" \
287 : "=a"(value) : "Nd"(port)); \
291 static inline void out##bwl##_p(unsigned type value, int port) \
293 out##bwl(value, port); \
297 static inline unsigned type in##bwl##_p(int port) \
299 unsigned type value = in##bwl(port); \
304 static inline void outs##bwl(int port, const void *addr, unsigned long count) \
306 asm volatile("rep; outs" #bwl \
307 : "+S"(addr), "+c"(count) : "d"(port)); \
310 static inline void ins##bwl(int port, void *addr, unsigned long count) \
312 asm volatile("rep; ins" #bwl \
313 : "+D"(addr), "+c"(count) : "d"(port)); \
320 extern void *xlate_dev_mem_ptr(phys_addr_t phys
);
321 extern void unxlate_dev_mem_ptr(phys_addr_t phys
, void *addr
);
323 extern int ioremap_change_attr(unsigned long vaddr
, unsigned long size
,
324 enum page_cache_mode pcm
);
325 extern void __iomem
*ioremap_wc(resource_size_t offset
, unsigned long size
);
326 extern void __iomem
*ioremap_wt(resource_size_t offset
, unsigned long size
);
328 extern bool is_early_ioremap_ptep(pte_t
*ptep
);
334 extern bool xen_biovec_phys_mergeable(const struct bio_vec
*vec1
,
335 const struct bio_vec
*vec2
);
337 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \
338 (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \
339 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
340 #endif /* CONFIG_XEN */
342 #define IO_SPACE_LIMIT 0xffff
345 extern int __must_check
arch_phys_wc_index(int handle
);
346 #define arch_phys_wc_index arch_phys_wc_index
348 extern int __must_check
arch_phys_wc_add(unsigned long base
,
350 extern void arch_phys_wc_del(int handle
);
351 #define arch_phys_wc_add arch_phys_wc_add
354 #endif /* _ASM_X86_IO_H */