arch/x86/include/asm/iosf_mbi.h

   1 /*
   2  * Intel OnChip System Fabric MailBox access support
   3  */
   4
   5 #ifndef IOSF_MBI_SYMS_H
   6 #define IOSF_MBI_SYMS_H
   7
   8 #define MBI_MCR_OFFSET          0xD0
   9 #define MBI_MDR_OFFSET          0xD4
  10 #define MBI_MCRX_OFFSET         0xD8
  11
  12 #define MBI_RD_MASK             0xFEFFFFFF
  13 #define MBI_WR_MASK             0X01000000
  14
  15 #define MBI_MASK_HI             0xFFFFFF00
  16 #define MBI_MASK_LO             0x000000FF
  17 #define MBI_ENABLE              0xF0
  18
  19 /* IOSF SB read/write opcodes */
  20 #define MBI_MMIO_READ           0x00
  21 #define MBI_MMIO_WRITE          0x01
  22 #define MBI_CFG_READ            0x04
  23 #define MBI_CFG_WRITE           0x05
  24 #define MBI_CR_READ             0x06
  25 #define MBI_CR_WRITE            0x07
  26 #define MBI_REG_READ            0x10
  27 #define MBI_REG_WRITE           0x11
  28 #define MBI_ESRAM_READ          0x12
  29 #define MBI_ESRAM_WRITE         0x13
  30
  31 /* Baytrail available units */
  32 #define BT_MBI_UNIT_AUNIT       0x00
  33 #define BT_MBI_UNIT_SMC         0x01
  34 #define BT_MBI_UNIT_CPU         0x02
  35 #define BT_MBI_UNIT_BUNIT       0x03
  36 #define BT_MBI_UNIT_PMC         0x04
  37 #define BT_MBI_UNIT_GFX         0x06
  38 #define BT_MBI_UNIT_SMI         0x0C
  39 #define BT_MBI_UNIT_USB         0x43
  40 #define BT_MBI_UNIT_SATA        0xA3
  41 #define BT_MBI_UNIT_PCIE        0xA6
  42
  43 /* Quark available units */
  44 #define QRK_MBI_UNIT_HBA        0x00
  45 #define QRK_MBI_UNIT_HB         0x03
  46 #define QRK_MBI_UNIT_RMU        0x04
  47 #define QRK_MBI_UNIT_MM         0x05
  48 #define QRK_MBI_UNIT_SOC        0x31
  49
  50 #if IS_ENABLED(CONFIG_IOSF_MBI)
  51
  52 bool iosf_mbi_available(void);
  53
  54 /**
  55  * iosf_mbi_read() - MailBox Interface read command
  56  * @port:       port indicating subunit being accessed
  57  * @opcode:     port specific read or write opcode
  58  * @offset:     register address offset
  59  * @mdr:        register data to be read
  60  *
  61  * Locking is handled by spinlock - cannot sleep.
  62  * Return: Nonzero on error
  63  */
  64 int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr);
  65
  66 /**
  67  * iosf_mbi_write() - MailBox unmasked write command
  68  * @port:       port indicating subunit being accessed
  69  * @opcode:     port specific read or write opcode
  70  * @offset:     register address offset
  71  * @mdr:        register data to be written
  72  *
  73  * Locking is handled by spinlock - cannot sleep.
  74  * Return: Nonzero on error
  75  */
  76 int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
  77
  78 /**
  79  * iosf_mbi_modify() - MailBox masked write command
  80  * @port:       port indicating subunit being accessed
  81  * @opcode:     port specific read or write opcode
  82  * @offset:     register address offset
  83  * @mdr:        register data being modified
  84  * @mask:       mask indicating bits in mdr to be modified
  85  *
  86  * Locking is handled by spinlock - cannot sleep.
  87  * Return: Nonzero on error
  88  */
  89 int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
  90
  91 #else /* CONFIG_IOSF_MBI is not enabled */
  92 static inline
  93 bool iosf_mbi_available(void)
  94 {
  95         return false;
  96 }
  97
  98 static inline
  99 int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
 100 {
 101         WARN(1, "IOSF_MBI driver not available");
 102         return -EPERM;
 103 }
 104
 105 static inline
 106 int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
 107 {
 108         WARN(1, "IOSF_MBI driver not available");
 109         return -EPERM;
 110 }
 111
 112 static inline
 113 int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
 114 {
 115         WARN(1, "IOSF_MBI driver not available");
 116         return -EPERM;
 117 }
 118 #endif /* CONFIG_IOSF_MBI */
 119
 120 #endif /* IOSF_MBI_SYMS_H */