1 #ifndef _ASM_X86_SYNC_BITOPS_H
2 #define _ASM_X86_SYNC_BITOPS_H
5 * Copyright 1992, Linus Torvalds.
9 * These have to be done with inline assembly: that way the bit-setting
10 * is guaranteed to be atomic. All bit operations return 0 if the bit
11 * was cleared before the operation and != 0 if it was not.
13 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
16 #define ADDR (*(volatile long *)addr)
19 * sync_set_bit - Atomically set a bit in memory
21 * @addr: the address to start counting from
23 * This function is atomic and may not be reordered. See __set_bit()
24 * if you do not require the atomic guarantees.
26 * Note that @nr may be almost arbitrarily large; this function is not
27 * restricted to acting on a single-word quantity.
29 static inline void sync_set_bit(long nr
, volatile unsigned long *addr
)
31 asm volatile("lock; bts %1,%0"
38 * sync_clear_bit - Clears a bit in memory
40 * @addr: Address to start counting from
42 * sync_clear_bit() is atomic and may not be reordered. However, it does
43 * not contain a memory barrier, so if it is used for locking purposes,
44 * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
45 * in order to ensure changes are visible on other processors.
47 static inline void sync_clear_bit(long nr
, volatile unsigned long *addr
)
49 asm volatile("lock; btr %1,%0"
56 * sync_change_bit - Toggle a bit in memory
58 * @addr: Address to start counting from
60 * sync_change_bit() is atomic and may not be reordered.
61 * Note that @nr may be almost arbitrarily large; this function is not
62 * restricted to acting on a single-word quantity.
64 static inline void sync_change_bit(long nr
, volatile unsigned long *addr
)
66 asm volatile("lock; btc %1,%0"
73 * sync_test_and_set_bit - Set a bit and return its old value
75 * @addr: Address to count from
77 * This operation is atomic and cannot be reordered.
78 * It also implies a memory barrier.
80 static inline int sync_test_and_set_bit(long nr
, volatile unsigned long *addr
)
84 asm volatile("lock; bts %2,%1\n\tsbbl %0,%0"
85 : "=r" (oldbit
), "+m" (ADDR
)
86 : "Ir" (nr
) : "memory");
91 * sync_test_and_clear_bit - Clear a bit and return its old value
93 * @addr: Address to count from
95 * This operation is atomic and cannot be reordered.
96 * It also implies a memory barrier.
98 static inline int sync_test_and_clear_bit(long nr
, volatile unsigned long *addr
)
102 asm volatile("lock; btr %2,%1\n\tsbbl %0,%0"
103 : "=r" (oldbit
), "+m" (ADDR
)
104 : "Ir" (nr
) : "memory");
109 * sync_test_and_change_bit - Change a bit and return its old value
111 * @addr: Address to count from
113 * This operation is atomic and cannot be reordered.
114 * It also implies a memory barrier.
116 static inline int sync_test_and_change_bit(long nr
, volatile unsigned long *addr
)
120 asm volatile("lock; btc %2,%1\n\tsbbl %0,%0"
121 : "=r" (oldbit
), "+m" (ADDR
)
122 : "Ir" (nr
) : "memory");
126 #define sync_test_bit(nr, addr) test_bit(nr, addr)
130 #endif /* _ASM_X86_SYNC_BITOPS_H */