2 * Copyright (C) 1995 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
10 * CPU hotplug support - ashok.raj@intel.com
14 * This file handles the architecture-dependent parts of process handling..
17 #include <linux/cpu.h>
18 #include <linux/errno.h>
19 #include <linux/sched.h>
21 #include <linux/kernel.h>
23 #include <linux/elfcore.h>
24 #include <linux/smp.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/module.h>
30 #include <linux/ptrace.h>
31 #include <linux/notifier.h>
32 #include <linux/kprobes.h>
33 #include <linux/kdebug.h>
34 #include <linux/prctl.h>
35 #include <linux/uaccess.h>
37 #include <linux/ftrace.h>
39 #include <asm/pgtable.h>
40 #include <asm/processor.h>
41 #include <asm/fpu/internal.h>
42 #include <asm/mmu_context.h>
43 #include <asm/prctl.h>
45 #include <asm/proto.h>
48 #include <asm/syscalls.h>
49 #include <asm/debugreg.h>
50 #include <asm/switch_to.h>
51 #include <asm/xen/hypervisor.h>
53 asmlinkage
extern void ret_from_fork(void);
55 __visible
DEFINE_PER_CPU(unsigned long, rsp_scratch
);
57 /* Prints also some state that isn't saved in the pt_regs */
58 void __show_regs(struct pt_regs
*regs
, int all
)
60 unsigned long cr0
= 0L, cr2
= 0L, cr3
= 0L, cr4
= 0L, fs
, gs
, shadowgs
;
61 unsigned long d0
, d1
, d2
, d3
, d6
, d7
;
62 unsigned int fsindex
, gsindex
;
63 unsigned int ds
, cs
, es
;
65 printk(KERN_DEFAULT
"RIP: %04lx:[<%016lx>] ", regs
->cs
& 0xffff, regs
->ip
);
66 printk_address(regs
->ip
);
67 printk(KERN_DEFAULT
"RSP: %04lx:%016lx EFLAGS: %08lx\n", regs
->ss
,
68 regs
->sp
, regs
->flags
);
69 printk(KERN_DEFAULT
"RAX: %016lx RBX: %016lx RCX: %016lx\n",
70 regs
->ax
, regs
->bx
, regs
->cx
);
71 printk(KERN_DEFAULT
"RDX: %016lx RSI: %016lx RDI: %016lx\n",
72 regs
->dx
, regs
->si
, regs
->di
);
73 printk(KERN_DEFAULT
"RBP: %016lx R08: %016lx R09: %016lx\n",
74 regs
->bp
, regs
->r8
, regs
->r9
);
75 printk(KERN_DEFAULT
"R10: %016lx R11: %016lx R12: %016lx\n",
76 regs
->r10
, regs
->r11
, regs
->r12
);
77 printk(KERN_DEFAULT
"R13: %016lx R14: %016lx R15: %016lx\n",
78 regs
->r13
, regs
->r14
, regs
->r15
);
80 asm("movl %%ds,%0" : "=r" (ds
));
81 asm("movl %%cs,%0" : "=r" (cs
));
82 asm("movl %%es,%0" : "=r" (es
));
83 asm("movl %%fs,%0" : "=r" (fsindex
));
84 asm("movl %%gs,%0" : "=r" (gsindex
));
86 rdmsrl(MSR_FS_BASE
, fs
);
87 rdmsrl(MSR_GS_BASE
, gs
);
88 rdmsrl(MSR_KERNEL_GS_BASE
, shadowgs
);
98 printk(KERN_DEFAULT
"FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
99 fs
, fsindex
, gs
, gsindex
, shadowgs
);
100 printk(KERN_DEFAULT
"CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs
, ds
,
102 printk(KERN_DEFAULT
"CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2
, cr3
,
112 /* Only print out debug registers if they are in their non-default state. */
113 if ((d0
== 0) && (d1
== 0) && (d2
== 0) && (d3
== 0) &&
114 (d6
== DR6_RESERVED
) && (d7
== 0x400))
117 printk(KERN_DEFAULT
"DR0: %016lx DR1: %016lx DR2: %016lx\n", d0
, d1
, d2
);
118 printk(KERN_DEFAULT
"DR3: %016lx DR6: %016lx DR7: %016lx\n", d3
, d6
, d7
);
120 if (boot_cpu_has(X86_FEATURE_OSPKE
))
121 printk(KERN_DEFAULT
"PKRU: %08x\n", read_pkru());
124 void release_thread(struct task_struct
*dead_task
)
127 #ifdef CONFIG_MODIFY_LDT_SYSCALL
128 if (dead_task
->mm
->context
.ldt
) {
129 pr_warn("WARNING: dead process %s still has LDT? <%p/%d>\n",
131 dead_task
->mm
->context
.ldt
->entries
,
132 dead_task
->mm
->context
.ldt
->size
);
139 static inline void set_32bit_tls(struct task_struct
*t
, int tls
, u32 addr
)
141 struct user_desc ud
= {
148 struct desc_struct
*desc
= t
->thread
.tls_array
;
153 static inline u32
read_32bit_tls(struct task_struct
*t
, int tls
)
155 return get_desc_base(&t
->thread
.tls_array
[tls
]);
158 int copy_thread_tls(unsigned long clone_flags
, unsigned long sp
,
159 unsigned long arg
, struct task_struct
*p
, unsigned long tls
)
162 struct pt_regs
*childregs
;
163 struct task_struct
*me
= current
;
165 p
->thread
.sp0
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
166 childregs
= task_pt_regs(p
);
167 p
->thread
.sp
= (unsigned long) childregs
;
168 set_tsk_thread_flag(p
, TIF_FORK
);
169 p
->thread
.io_bitmap_ptr
= NULL
;
171 savesegment(gs
, p
->thread
.gsindex
);
172 p
->thread
.gs
= p
->thread
.gsindex
? 0 : me
->thread
.gs
;
173 savesegment(fs
, p
->thread
.fsindex
);
174 p
->thread
.fs
= p
->thread
.fsindex
? 0 : me
->thread
.fs
;
175 savesegment(es
, p
->thread
.es
);
176 savesegment(ds
, p
->thread
.ds
);
177 memset(p
->thread
.ptrace_bps
, 0, sizeof(p
->thread
.ptrace_bps
));
179 if (unlikely(p
->flags
& PF_KTHREAD
)) {
181 memset(childregs
, 0, sizeof(struct pt_regs
));
182 childregs
->sp
= (unsigned long)childregs
;
183 childregs
->ss
= __KERNEL_DS
;
184 childregs
->bx
= sp
; /* function */
186 childregs
->orig_ax
= -1;
187 childregs
->cs
= __KERNEL_CS
| get_kernel_rpl();
188 childregs
->flags
= X86_EFLAGS_IF
| X86_EFLAGS_FIXED
;
191 *childregs
= *current_pt_regs();
198 if (unlikely(test_tsk_thread_flag(me
, TIF_IO_BITMAP
))) {
199 p
->thread
.io_bitmap_ptr
= kmemdup(me
->thread
.io_bitmap_ptr
,
200 IO_BITMAP_BYTES
, GFP_KERNEL
);
201 if (!p
->thread
.io_bitmap_ptr
) {
202 p
->thread
.io_bitmap_max
= 0;
205 set_tsk_thread_flag(p
, TIF_IO_BITMAP
);
209 * Set a new TLS for the child thread?
211 if (clone_flags
& CLONE_SETTLS
) {
212 #ifdef CONFIG_IA32_EMULATION
214 err
= do_set_thread_area(p
, -1,
215 (struct user_desc __user
*)tls
, 0);
218 err
= do_arch_prctl(p
, ARCH_SET_FS
, tls
);
224 if (err
&& p
->thread
.io_bitmap_ptr
) {
225 kfree(p
->thread
.io_bitmap_ptr
);
226 p
->thread
.io_bitmap_max
= 0;
233 start_thread_common(struct pt_regs
*regs
, unsigned long new_ip
,
234 unsigned long new_sp
,
235 unsigned int _cs
, unsigned int _ss
, unsigned int _ds
)
238 loadsegment(es
, _ds
);
239 loadsegment(ds
, _ds
);
245 regs
->flags
= X86_EFLAGS_IF
;
250 start_thread(struct pt_regs
*regs
, unsigned long new_ip
, unsigned long new_sp
)
252 start_thread_common(regs
, new_ip
, new_sp
,
253 __USER_CS
, __USER_DS
, 0);
257 void compat_start_thread(struct pt_regs
*regs
, u32 new_ip
, u32 new_sp
)
259 start_thread_common(regs
, new_ip
, new_sp
,
260 test_thread_flag(TIF_X32
)
261 ? __USER_CS
: __USER32_CS
,
262 __USER_DS
, __USER_DS
);
267 * switch_to(x,y) should switch tasks from x to y.
269 * This could still be optimized:
270 * - fold all the options into a flag word and test it with a single test.
271 * - could test fs/gs bitsliced
273 * Kprobes not supported here. Set the probe on schedule instead.
274 * Function graph tracer not supported too.
276 __visible __notrace_funcgraph
struct task_struct
*
277 __switch_to(struct task_struct
*prev_p
, struct task_struct
*next_p
)
279 struct thread_struct
*prev
= &prev_p
->thread
;
280 struct thread_struct
*next
= &next_p
->thread
;
281 struct fpu
*prev_fpu
= &prev
->fpu
;
282 struct fpu
*next_fpu
= &next
->fpu
;
283 int cpu
= smp_processor_id();
284 struct tss_struct
*tss
= &per_cpu(cpu_tss
, cpu
);
285 unsigned fsindex
, gsindex
;
286 fpu_switch_t fpu_switch
;
288 fpu_switch
= switch_fpu_prepare(prev_fpu
, next_fpu
, cpu
);
290 /* We must save %fs and %gs before load_TLS() because
291 * %fs and %gs may be cleared by load_TLS().
293 * (e.g. xen_load_tls())
295 savesegment(fs
, fsindex
);
296 savesegment(gs
, gsindex
);
299 * Load TLS before restoring any segments so that segment loads
300 * reference the correct GDT entries.
305 * Leave lazy mode, flushing any hypercalls made here. This
306 * must be done after loading TLS entries in the GDT but before
307 * loading segments that might reference them, and and it must
308 * be done before fpu__restore(), so the TS bit is up to
311 arch_end_context_switch(next_p
);
315 * Reading them only returns the selectors, but writing them (if
316 * nonzero) loads the full descriptor from the GDT or LDT. The
317 * LDT for next is loaded in switch_mm, and the GDT is loaded
320 * We therefore need to write new values to the segment
321 * registers on every context switch unless both the new and old
324 * Note that we don't need to do anything for CS and SS, as
325 * those are saved and restored as part of pt_regs.
327 savesegment(es
, prev
->es
);
328 if (unlikely(next
->es
| prev
->es
))
329 loadsegment(es
, next
->es
);
331 savesegment(ds
, prev
->ds
);
332 if (unlikely(next
->ds
| prev
->ds
))
333 loadsegment(ds
, next
->ds
);
338 * These are even more complicated than DS and ES: they have
339 * 64-bit bases are that controlled by arch_prctl. Those bases
340 * only differ from the values in the GDT or LDT if the selector
343 * Loading the segment register resets the hidden base part of
344 * the register to 0 or the value from the GDT / LDT. If the
345 * next base address zero, writing 0 to the segment register is
346 * much faster than using wrmsr to explicitly zero the base.
348 * The thread_struct.fs and thread_struct.gs values are 0
349 * if the fs and gs bases respectively are not overridden
350 * from the values implied by fsindex and gsindex. They
351 * are nonzero, and store the nonzero base addresses, if
352 * the bases are overridden.
354 * (fs != 0 && fsindex != 0) || (gs != 0 && gsindex != 0) should
357 * Therefore we need to reload the segment registers if either
358 * the old or new selector is nonzero, and we need to override
359 * the base address if next thread expects it to be overridden.
361 * This code is unnecessarily slow in the case where the old and
362 * new indexes are zero and the new base is nonzero -- it will
363 * unnecessarily write 0 to the selector before writing the new
366 * Note: This all depends on arch_prctl being the only way that
367 * user code can override the segment base. Once wrfsbase and
368 * wrgsbase are enabled, most of this code will need to change.
370 if (unlikely(fsindex
| next
->fsindex
| prev
->fs
)) {
371 loadsegment(fs
, next
->fsindex
);
374 * If user code wrote a nonzero value to FS, then it also
375 * cleared the overridden base address.
377 * XXX: if user code wrote 0 to FS and cleared the base
378 * address itself, we won't notice and we'll incorrectly
379 * restore the prior base address next time we reschdule
386 wrmsrl(MSR_FS_BASE
, next
->fs
);
387 prev
->fsindex
= fsindex
;
389 if (unlikely(gsindex
| next
->gsindex
| prev
->gs
)) {
390 load_gs_index(next
->gsindex
);
392 /* This works (and fails) the same way as fsindex above. */
397 wrmsrl(MSR_KERNEL_GS_BASE
, next
->gs
);
398 prev
->gsindex
= gsindex
;
400 switch_fpu_finish(next_fpu
, fpu_switch
);
403 * Switch the PDA and FPU contexts.
405 this_cpu_write(current_task
, next_p
);
407 /* Reload esp0 and ss1. This changes current_thread_info(). */
411 * Now maybe reload the debug registers and handle I/O bitmaps
413 if (unlikely(task_thread_info(next_p
)->flags
& _TIF_WORK_CTXSW_NEXT
||
414 task_thread_info(prev_p
)->flags
& _TIF_WORK_CTXSW_PREV
))
415 __switch_to_xtra(prev_p
, next_p
, tss
);
419 * On Xen PV, IOPL bits in pt_regs->flags have no effect, and
420 * current_pt_regs()->flags may not match the current task's
421 * intended IOPL. We need to switch it manually.
423 if (unlikely(static_cpu_has(X86_FEATURE_XENPV
) &&
424 prev
->iopl
!= next
->iopl
))
425 xen_set_iopl_mask(next
->iopl
);
428 if (static_cpu_has_bug(X86_BUG_SYSRET_SS_ATTRS
)) {
430 * AMD CPUs have a misfeature: SYSRET sets the SS selector but
431 * does not update the cached descriptor. As a result, if we
432 * do SYSRET while SS is NULL, we'll end up in user mode with
433 * SS apparently equal to __USER_DS but actually unusable.
435 * The straightforward workaround would be to fix it up just
436 * before SYSRET, but that would slow down the system call
437 * fast paths. Instead, we ensure that SS is never NULL in
438 * system call context. We do this by replacing NULL SS
439 * selectors at every context switch. SYSCALL sets up a valid
440 * SS, so the only way to get NULL is to re-enter the kernel
441 * from CPL 3 through an interrupt. Since that can't happen
442 * in the same task as a running syscall, we are guaranteed to
443 * context switch between every interrupt vector entry and a
446 * We read SS first because SS reads are much faster than
447 * writes. Out of caution, we force SS to __KERNEL_DS even if
448 * it previously had a different non-NULL value.
450 unsigned short ss_sel
;
451 savesegment(ss
, ss_sel
);
452 if (ss_sel
!= __KERNEL_DS
)
453 loadsegment(ss
, __KERNEL_DS
);
459 void set_personality_64bit(void)
461 /* inherit personality from parent */
463 /* Make sure to be in 64bit mode */
464 clear_thread_flag(TIF_IA32
);
465 clear_thread_flag(TIF_ADDR32
);
466 clear_thread_flag(TIF_X32
);
468 /* Ensure the corresponding mm is not marked. */
470 current
->mm
->context
.ia32_compat
= 0;
472 /* TBD: overwrites user setup. Should have two bits.
473 But 64bit processes have always behaved this way,
474 so it's not too bad. The main problem is just that
475 32bit childs are affected again. */
476 current
->personality
&= ~READ_IMPLIES_EXEC
;
479 void set_personality_ia32(bool x32
)
481 /* inherit personality from parent */
483 /* Make sure to be in 32bit mode */
484 set_thread_flag(TIF_ADDR32
);
486 /* Mark the associated mm as containing 32-bit tasks. */
488 clear_thread_flag(TIF_IA32
);
489 set_thread_flag(TIF_X32
);
491 current
->mm
->context
.ia32_compat
= TIF_X32
;
492 current
->personality
&= ~READ_IMPLIES_EXEC
;
493 /* in_compat_syscall() uses the presence of the x32
494 syscall bit flag to determine compat status */
495 current_thread_info()->status
&= ~TS_COMPAT
;
497 set_thread_flag(TIF_IA32
);
498 clear_thread_flag(TIF_X32
);
500 current
->mm
->context
.ia32_compat
= TIF_IA32
;
501 current
->personality
|= force_personality32
;
502 /* Prepare the first "return" to user space */
503 current_thread_info()->status
|= TS_COMPAT
;
506 EXPORT_SYMBOL_GPL(set_personality_ia32
);
508 long do_arch_prctl(struct task_struct
*task
, int code
, unsigned long addr
)
511 int doit
= task
== current
;
516 if (addr
>= TASK_SIZE_OF(task
))
519 /* handle small bases via the GDT because that's faster to
521 if (addr
<= 0xffffffff) {
522 set_32bit_tls(task
, GS_TLS
, addr
);
524 load_TLS(&task
->thread
, cpu
);
525 load_gs_index(GS_TLS_SEL
);
527 task
->thread
.gsindex
= GS_TLS_SEL
;
530 task
->thread
.gsindex
= 0;
531 task
->thread
.gs
= addr
;
534 ret
= wrmsrl_safe(MSR_KERNEL_GS_BASE
, addr
);
540 /* Not strictly needed for fs, but do it for symmetry
542 if (addr
>= TASK_SIZE_OF(task
))
545 /* handle small bases via the GDT because that's faster to
547 if (addr
<= 0xffffffff) {
548 set_32bit_tls(task
, FS_TLS
, addr
);
550 load_TLS(&task
->thread
, cpu
);
551 loadsegment(fs
, FS_TLS_SEL
);
553 task
->thread
.fsindex
= FS_TLS_SEL
;
556 task
->thread
.fsindex
= 0;
557 task
->thread
.fs
= addr
;
559 /* set the selector to 0 to not confuse
562 ret
= wrmsrl_safe(MSR_FS_BASE
, addr
);
569 if (task
->thread
.fsindex
== FS_TLS_SEL
)
570 base
= read_32bit_tls(task
, FS_TLS
);
572 rdmsrl(MSR_FS_BASE
, base
);
574 base
= task
->thread
.fs
;
575 ret
= put_user(base
, (unsigned long __user
*)addr
);
581 if (task
->thread
.gsindex
== GS_TLS_SEL
)
582 base
= read_32bit_tls(task
, GS_TLS
);
584 savesegment(gs
, gsindex
);
586 rdmsrl(MSR_KERNEL_GS_BASE
, base
);
588 base
= task
->thread
.gs
;
590 base
= task
->thread
.gs
;
591 ret
= put_user(base
, (unsigned long __user
*)addr
);
603 long sys_arch_prctl(int code
, unsigned long addr
)
605 return do_arch_prctl(current
, code
, addr
);
608 unsigned long KSTK_ESP(struct task_struct
*task
)
610 return task_pt_regs(task
)->sp
;