2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
71 #include <asm/fpu/internal.h>
72 #include <asm/setup.h>
73 #include <asm/uv/uv.h>
74 #include <linux/mc146818rtc.h>
75 #include <asm/i8259.h>
76 #include <asm/realmode.h>
79 /* Number of siblings per CPU package */
80 int smp_num_siblings
= 1;
81 EXPORT_SYMBOL(smp_num_siblings
);
83 /* Last level cache ID of each logical CPU */
84 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
86 /* representing HT siblings of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
90 /* representing HT and core siblings of each logical CPU */
91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
92 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
96 /* Per CPU bogomips and other parameters */
97 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
98 EXPORT_PER_CPU_SYMBOL(cpu_info
);
100 /* Logical package management. We might want to allocate that dynamically */
101 static int *physical_to_logical_pkg __read_mostly
;
102 static unsigned long *physical_package_map __read_mostly
;;
103 static unsigned long *logical_package_map __read_mostly
;
104 static unsigned int max_physical_pkg_id __read_mostly
;
105 unsigned int __max_logical_packages __read_mostly
;
106 EXPORT_SYMBOL(__max_logical_packages
);
108 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip
)
112 spin_lock_irqsave(&rtc_lock
, flags
);
113 CMOS_WRITE(0xa, 0xf);
114 spin_unlock_irqrestore(&rtc_lock
, flags
);
117 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH
)) =
120 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) =
125 static inline void smpboot_restore_warm_reset_vector(void)
130 * Install writable page 0 entry to set BIOS data area.
135 * Paranoid: Set warm reset code and vector here back
138 spin_lock_irqsave(&rtc_lock
, flags
);
140 spin_unlock_irqrestore(&rtc_lock
, flags
);
142 *((volatile u32
*)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) = 0;
146 * Report back to the Boot Processor during boot time or to the caller processor
149 static void smp_callin(void)
154 * If waken up by an INIT in an 82489DX configuration
155 * cpu_callout_mask guarantees we don't get here before
156 * an INIT_deassert IPI reaches our local APIC, so it is
157 * now safe to touch our local APIC.
159 cpuid
= smp_processor_id();
162 * (This works even if the APIC is not enabled.)
164 phys_id
= read_apic_id();
167 * the boot CPU has finished the init stage and is spinning
168 * on callin_map until we finish. We are free to set up this
169 * CPU, first the APIC. (this is probably redundant on most
175 * Save our processor parameters. Note: this information
176 * is needed for clock calibration.
178 smp_store_cpu_info(cpuid
);
182 * Update loops_per_jiffy in cpu_data. Previous call to
183 * smp_store_cpu_info() stored a value that is close but not as
184 * accurate as the value just calculated.
187 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
188 pr_debug("Stack at about %p\n", &cpuid
);
191 * This must be done before setting cpu_online_mask
192 * or calling notify_cpu_starting.
194 set_cpu_sibling_map(raw_smp_processor_id());
197 notify_cpu_starting(cpuid
);
200 * Allow the master to continue.
202 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
205 static int cpu0_logical_apicid
;
206 static int enable_start_cpu0
;
208 * Activate a secondary processor.
210 static void notrace
start_secondary(void *unused
)
213 * Don't put *anything* before cpu_init(), SMP booting is too
214 * fragile that we want to limit the things done here to the
215 * most necessary things.
218 x86_cpuinit
.early_percpu_clock_init();
222 enable_start_cpu0
= 0;
225 /* switch away from the initial page table */
226 load_cr3(swapper_pg_dir
);
230 /* otherwise gcc will move up smp_processor_id before the cpu_init */
233 * Check TSC synchronization with the BP:
235 check_tsc_sync_target();
238 * Lock vector_lock and initialize the vectors on this cpu
239 * before setting the cpu online. We must set it online with
240 * vector_lock held to prevent a concurrent setup/teardown
241 * from seeing a half valid vector space.
244 setup_vector_irq(smp_processor_id());
245 set_cpu_online(smp_processor_id(), true);
246 unlock_vector_lock();
247 cpu_set_state_online(smp_processor_id());
248 x86_platform
.nmi_init();
250 /* enable local interrupts */
253 /* to prevent fake stack check failure in clock setup */
254 boot_init_stack_canary();
256 x86_cpuinit
.setup_percpu_clockev();
259 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE
);
262 int topology_update_package_map(unsigned int apicid
, unsigned int cpu
)
264 unsigned int new, pkg
= apicid
>> boot_cpu_data
.x86_coreid_bits
;
266 /* Called from early boot ? */
267 if (!physical_package_map
)
270 if (pkg
>= max_physical_pkg_id
)
273 /* Set the logical package id */
274 if (test_and_set_bit(pkg
, physical_package_map
))
277 new = find_first_zero_bit(logical_package_map
, __max_logical_packages
);
278 if (new >= __max_logical_packages
) {
279 physical_to_logical_pkg
[pkg
] = -1;
280 pr_warn("APIC(%x) Package %u exceeds logical package map\n",
284 set_bit(new, logical_package_map
);
285 pr_info("APIC(%x) Converting physical %u to logical package %u\n",
287 physical_to_logical_pkg
[pkg
] = new;
290 cpu_data(cpu
).logical_proc_id
= physical_to_logical_pkg
[pkg
];
295 * topology_phys_to_logical_pkg - Map a physical package id to a logical
297 * Returns logical package id or -1 if not found
299 int topology_phys_to_logical_pkg(unsigned int phys_pkg
)
301 if (phys_pkg
>= max_physical_pkg_id
)
303 return physical_to_logical_pkg
[phys_pkg
];
305 EXPORT_SYMBOL(topology_phys_to_logical_pkg
);
307 static void __init
smp_init_package_map(void)
309 unsigned int ncpus
, cpu
;
313 * Today neither Intel nor AMD support heterogenous systems. That
314 * might change in the future....
316 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
317 * computation, this won't actually work since some Intel BIOSes
318 * report inconsistent HT data when they disable HT.
320 * In particular, they reduce the APIC-IDs to only include the cores,
321 * but leave the CPUID topology to say there are (2) siblings.
322 * This means we don't know how many threads there will be until
323 * after the APIC enumeration.
325 * By not including this we'll sometimes over-estimate the number of
326 * logical packages by the amount of !present siblings, but this is
327 * still better than MAX_LOCAL_APIC.
329 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
330 * on the command line leading to a similar issue as the HT disable
331 * problem because the hyperthreads are usually enumerated after the
334 ncpus
= boot_cpu_data
.x86_max_cores
;
335 __max_logical_packages
= DIV_ROUND_UP(total_cpus
, ncpus
);
338 * Possibly larger than what we need as the number of apic ids per
339 * package can be smaller than the actual used apic ids.
341 max_physical_pkg_id
= DIV_ROUND_UP(MAX_LOCAL_APIC
, ncpus
);
342 size
= max_physical_pkg_id
* sizeof(unsigned int);
343 physical_to_logical_pkg
= kmalloc(size
, GFP_KERNEL
);
344 memset(physical_to_logical_pkg
, 0xff, size
);
345 size
= BITS_TO_LONGS(max_physical_pkg_id
) * sizeof(unsigned long);
346 physical_package_map
= kzalloc(size
, GFP_KERNEL
);
347 size
= BITS_TO_LONGS(__max_logical_packages
) * sizeof(unsigned long);
348 logical_package_map
= kzalloc(size
, GFP_KERNEL
);
350 pr_info("Max logical packages: %u\n", __max_logical_packages
);
352 for_each_present_cpu(cpu
) {
353 unsigned int apicid
= apic
->cpu_present_to_apicid(cpu
);
355 if (apicid
== BAD_APICID
|| !apic
->apic_id_valid(apicid
))
357 if (!topology_update_package_map(apicid
, cpu
))
359 pr_warn("CPU %u APICId %x disabled\n", cpu
, apicid
);
360 per_cpu(x86_bios_cpu_apicid
, cpu
) = BAD_APICID
;
361 set_cpu_possible(cpu
, false);
362 set_cpu_present(cpu
, false);
366 void __init
smp_store_boot_cpu_info(void)
368 int id
= 0; /* CPU 0 */
369 struct cpuinfo_x86
*c
= &cpu_data(id
);
373 smp_init_package_map();
377 * The bootstrap kernel entry code has set these up. Save them for
380 void smp_store_cpu_info(int id
)
382 struct cpuinfo_x86
*c
= &cpu_data(id
);
387 * During boot time, CPU0 has this setup already. Save the info when
388 * bringing up AP or offlined CPU0.
390 identify_secondary_cpu(c
);
394 topology_same_node(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
396 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
398 return (cpu_to_node(cpu1
) == cpu_to_node(cpu2
));
402 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
404 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
406 return !WARN_ONCE(!topology_same_node(c
, o
),
407 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
408 "[node: %d != %d]. Ignoring dependency.\n",
409 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
412 #define link_mask(mfunc, c1, c2) \
414 cpumask_set_cpu((c1), mfunc(c2)); \
415 cpumask_set_cpu((c2), mfunc(c1)); \
418 static bool match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
420 if (boot_cpu_has(X86_FEATURE_TOPOEXT
)) {
421 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
423 if (c
->phys_proc_id
== o
->phys_proc_id
&&
424 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
) &&
425 c
->cpu_core_id
== o
->cpu_core_id
)
426 return topology_sane(c
, o
, "smt");
428 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
429 c
->cpu_core_id
== o
->cpu_core_id
) {
430 return topology_sane(c
, o
, "smt");
436 static bool match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
438 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
440 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
441 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
442 return topology_sane(c
, o
, "llc");
448 * Unlike the other levels, we do not enforce keeping a
449 * multicore group inside a NUMA node. If this happens, we will
450 * discard the MC level of the topology later.
452 static bool match_die(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
454 if (c
->phys_proc_id
== o
->phys_proc_id
)
459 static struct sched_domain_topology_level numa_inside_package_topology
[] = {
460 #ifdef CONFIG_SCHED_SMT
461 { cpu_smt_mask
, cpu_smt_flags
, SD_INIT_NAME(SMT
) },
463 #ifdef CONFIG_SCHED_MC
464 { cpu_coregroup_mask
, cpu_core_flags
, SD_INIT_NAME(MC
) },
469 * set_sched_topology() sets the topology internal to a CPU. The
470 * NUMA topologies are layered on top of it to build the full
473 * If NUMA nodes are observed to occur within a CPU package, this
474 * function should be called. It forces the sched domain code to
475 * only use the SMT level for the CPU portion of the topology.
476 * This essentially falls back to relying on NUMA information
477 * from the SRAT table to describe the entire system topology
478 * (except for hyperthreads).
480 static void primarily_use_numa_for_topology(void)
482 set_sched_topology(numa_inside_package_topology
);
485 void set_cpu_sibling_map(int cpu
)
487 bool has_smt
= smp_num_siblings
> 1;
488 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
489 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
490 struct cpuinfo_x86
*o
;
493 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
496 cpumask_set_cpu(cpu
, topology_sibling_cpumask(cpu
));
497 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
498 cpumask_set_cpu(cpu
, topology_core_cpumask(cpu
));
503 for_each_cpu(i
, cpu_sibling_setup_mask
) {
506 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
507 link_mask(topology_sibling_cpumask
, cpu
, i
);
509 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
510 link_mask(cpu_llc_shared_mask
, cpu
, i
);
515 * This needs a separate iteration over the cpus because we rely on all
516 * topology_sibling_cpumask links to be set-up.
518 for_each_cpu(i
, cpu_sibling_setup_mask
) {
521 if ((i
== cpu
) || (has_mp
&& match_die(c
, o
))) {
522 link_mask(topology_core_cpumask
, cpu
, i
);
525 * Does this new cpu bringup a new core?
528 topology_sibling_cpumask(cpu
)) == 1) {
530 * for each core in package, increment
531 * the booted_cores for this new cpu
534 topology_sibling_cpumask(i
)) == i
)
537 * increment the core count for all
538 * the other cpus in this package
541 cpu_data(i
).booted_cores
++;
542 } else if (i
!= cpu
&& !c
->booted_cores
)
543 c
->booted_cores
= cpu_data(i
).booted_cores
;
545 if (match_die(c
, o
) && !topology_same_node(c
, o
))
546 primarily_use_numa_for_topology();
550 /* maps the cpu to the sched domain representing multi-core */
551 const struct cpumask
*cpu_coregroup_mask(int cpu
)
553 return cpu_llc_shared_mask(cpu
);
556 static void impress_friends(void)
559 unsigned long bogosum
= 0;
561 * Allow the user to impress friends.
563 pr_debug("Before bogomips\n");
564 for_each_possible_cpu(cpu
)
565 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
566 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
567 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
570 (bogosum
/(5000/HZ
))%100);
572 pr_debug("Before bogocount - setting activated=1\n");
575 void __inquire_remote_apic(int apicid
)
577 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
578 const char * const names
[] = { "ID", "VERSION", "SPIV" };
582 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
584 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
585 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
590 status
= safe_apic_wait_icr_idle();
592 pr_cont("a previous APIC delivery may have failed\n");
594 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
599 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
600 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
603 case APIC_ICR_RR_VALID
:
604 status
= apic_read(APIC_RRR
);
605 pr_cont("%08x\n", status
);
614 * The Multiprocessor Specification 1.4 (1997) example code suggests
615 * that there should be a 10ms delay between the BSP asserting INIT
616 * and de-asserting INIT, when starting a remote processor.
617 * But that slows boot and resume on modern processors, which include
618 * many cores and don't require that delay.
620 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
621 * Modern processor families are quirked to remove the delay entirely.
623 #define UDELAY_10MS_DEFAULT 10000
625 static unsigned int init_udelay
= UINT_MAX
;
627 static int __init
cpu_init_udelay(char *str
)
629 get_option(&str
, &init_udelay
);
633 early_param("cpu_init_udelay", cpu_init_udelay
);
635 static void __init
smp_quirk_init_udelay(void)
637 /* if cmdline changed it from default, leave it alone */
638 if (init_udelay
!= UINT_MAX
)
641 /* if modern processor, use no delay */
642 if (((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 6)) ||
643 ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && (boot_cpu_data
.x86
>= 0xF))) {
647 /* else, use legacy delay */
648 init_udelay
= UDELAY_10MS_DEFAULT
;
652 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
653 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
654 * won't ... remember to clear down the APIC, etc later.
657 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
659 unsigned long send_status
, accept_status
= 0;
663 /* Boot on the stack */
664 /* Kick the second */
665 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
667 pr_debug("Waiting for send to finish...\n");
668 send_status
= safe_apic_wait_icr_idle();
671 * Give the other CPU some time to accept the IPI.
674 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
675 maxlvt
= lapic_get_maxlvt();
676 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
677 apic_write(APIC_ESR
, 0);
678 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
680 pr_debug("NMI sent\n");
683 pr_err("APIC never delivered???\n");
685 pr_err("APIC delivery error (%lx)\n", accept_status
);
687 return (send_status
| accept_status
);
691 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
693 unsigned long send_status
= 0, accept_status
= 0;
694 int maxlvt
, num_starts
, j
;
696 maxlvt
= lapic_get_maxlvt();
699 * Be paranoid about clearing APIC errors.
701 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
702 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
703 apic_write(APIC_ESR
, 0);
707 pr_debug("Asserting INIT\n");
710 * Turn INIT on target chip
715 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
718 pr_debug("Waiting for send to finish...\n");
719 send_status
= safe_apic_wait_icr_idle();
723 pr_debug("Deasserting INIT\n");
727 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
729 pr_debug("Waiting for send to finish...\n");
730 send_status
= safe_apic_wait_icr_idle();
735 * Should we send STARTUP IPIs ?
737 * Determine this based on the APIC version.
738 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
740 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
746 * Run STARTUP IPI loop.
748 pr_debug("#startup loops: %d\n", num_starts
);
750 for (j
= 1; j
<= num_starts
; j
++) {
751 pr_debug("Sending STARTUP #%d\n", j
);
752 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
753 apic_write(APIC_ESR
, 0);
755 pr_debug("After apic_write\n");
762 /* Boot on the stack */
763 /* Kick the second */
764 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
768 * Give the other CPU some time to accept the IPI.
770 if (init_udelay
== 0)
775 pr_debug("Startup point 1\n");
777 pr_debug("Waiting for send to finish...\n");
778 send_status
= safe_apic_wait_icr_idle();
781 * Give the other CPU some time to accept the IPI.
783 if (init_udelay
== 0)
788 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
789 apic_write(APIC_ESR
, 0);
790 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
791 if (send_status
|| accept_status
)
794 pr_debug("After Startup\n");
797 pr_err("APIC never delivered???\n");
799 pr_err("APIC delivery error (%lx)\n", accept_status
);
801 return (send_status
| accept_status
);
804 void smp_announce(void)
806 int num_nodes
= num_online_nodes();
808 printk(KERN_INFO
"x86: Booted up %d node%s, %d CPUs\n",
809 num_nodes
, (num_nodes
> 1 ? "s" : ""), num_online_cpus());
812 /* reduce the number of lines printed when booting a large cpu count system */
813 static void announce_cpu(int cpu
, int apicid
)
815 static int current_node
= -1;
816 int node
= early_cpu_to_node(cpu
);
817 static int width
, node_width
;
820 width
= num_digits(num_possible_cpus()) + 1; /* + '#' sign */
823 node_width
= num_digits(num_possible_nodes()) + 1; /* + '#' */
826 printk(KERN_INFO
"x86: Booting SMP configuration:\n");
828 if (system_state
== SYSTEM_BOOTING
) {
829 if (node
!= current_node
) {
830 if (current_node
> (-1))
834 printk(KERN_INFO
".... node %*s#%d, CPUs: ",
835 node_width
- num_digits(node
), " ", node
);
838 /* Add padding for the BSP */
840 pr_cont("%*s", width
+ 1, " ");
842 pr_cont("%*s#%d", width
- num_digits(cpu
), " ", cpu
);
845 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
849 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
853 cpu
= smp_processor_id();
854 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
861 * Wake up AP by INIT, INIT, STARTUP sequence.
863 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
864 * boot-strap code which is not a desired behavior for waking up BSP. To
865 * void the boot-strap code, wake up CPU0 by NMI instead.
867 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
868 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
869 * We'll change this code in the future to wake up hard offlined CPU0 if
870 * real platform and request are available.
873 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
874 int *cpu0_nmi_registered
)
882 * Wake up AP by INIT, INIT, STARTUP sequence.
885 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
890 * Wake up BSP by nmi.
892 * Register a NMI handler to help wake up CPU0.
894 boot_error
= register_nmi_handler(NMI_LOCAL
,
895 wakeup_cpu0_nmi
, 0, "wake_cpu0");
898 enable_start_cpu0
= 1;
899 *cpu0_nmi_registered
= 1;
900 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
901 id
= cpu0_logical_apicid
;
904 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
913 void common_cpu_up(unsigned int cpu
, struct task_struct
*idle
)
915 /* Just in case we booted with a single CPU. */
916 alternatives_enable_smp();
918 per_cpu(current_task
, cpu
) = idle
;
921 /* Stack for startup_32 can be just as for start_secondary onwards */
923 per_cpu(cpu_current_top_of_stack
, cpu
) =
924 (unsigned long)task_stack_page(idle
) + THREAD_SIZE
;
926 clear_tsk_thread_flag(idle
, TIF_FORK
);
927 initial_gs
= per_cpu_offset(cpu
);
932 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
933 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
934 * Returns zero if CPU booted OK, else error code from
935 * ->wakeup_secondary_cpu.
937 static int do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
)
939 volatile u32
*trampoline_status
=
940 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
941 /* start_ip had better be page-aligned! */
942 unsigned long start_ip
= real_mode_header
->trampoline_start
;
944 unsigned long boot_error
= 0;
945 int cpu0_nmi_registered
= 0;
946 unsigned long timeout
;
948 idle
->thread
.sp
= (unsigned long) (((struct pt_regs
*)
949 (THREAD_SIZE
+ task_stack_page(idle
))) - 1);
951 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
952 initial_code
= (unsigned long)start_secondary
;
953 stack_start
= idle
->thread
.sp
;
956 * Enable the espfix hack for this CPU
958 #ifdef CONFIG_X86_ESPFIX64
962 /* So we see what's up */
963 announce_cpu(cpu
, apicid
);
966 * This grunge runs the startup process for
967 * the targeted processor.
970 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
972 pr_debug("Setting warm reset code and vector.\n");
974 smpboot_setup_warm_reset_vector(start_ip
);
976 * Be paranoid about clearing APIC errors.
978 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
979 apic_write(APIC_ESR
, 0);
985 * AP might wait on cpu_callout_mask in cpu_init() with
986 * cpu_initialized_mask set if previous attempt to online
987 * it timed-out. Clear cpu_initialized_mask so that after
988 * INIT/SIPI it could start with a clean state.
990 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
994 * Wake up a CPU in difference cases:
995 * - Use the method in the APIC driver if it's defined
997 * - Use an INIT boot APIC message for APs or NMI for BSP.
999 if (apic
->wakeup_secondary_cpu
)
1000 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
1002 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
1003 &cpu0_nmi_registered
);
1007 * Wait 10s total for first sign of life from AP
1010 timeout
= jiffies
+ 10*HZ
;
1011 while (time_before(jiffies
, timeout
)) {
1012 if (cpumask_test_cpu(cpu
, cpu_initialized_mask
)) {
1014 * Tell AP to proceed with initialization
1016 cpumask_set_cpu(cpu
, cpu_callout_mask
);
1026 * Wait till AP completes initial initialization
1028 while (!cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1030 * Allow other tasks to run while we wait for the
1031 * AP to come online. This also gives a chance
1032 * for the MTRR work(triggered by the AP coming online)
1033 * to be completed in the stop machine context.
1039 /* mark "stuck" area as not stuck */
1040 *trampoline_status
= 0;
1042 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
1044 * Cleanup possible dangling ends...
1046 smpboot_restore_warm_reset_vector();
1049 * Clean up the nmi handler. Do this after the callin and callout sync
1050 * to avoid impact of possible long unregister time.
1052 if (cpu0_nmi_registered
)
1053 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
1058 int native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
1060 int apicid
= apic
->cpu_present_to_apicid(cpu
);
1061 unsigned long flags
;
1064 WARN_ON(irqs_disabled());
1066 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
1068 if (apicid
== BAD_APICID
||
1069 !physid_isset(apicid
, phys_cpu_present_map
) ||
1070 !apic
->apic_id_valid(apicid
)) {
1071 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
1076 * Already booted CPU?
1078 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1079 pr_debug("do_boot_cpu %d Already started\n", cpu
);
1084 * Save current MTRR state in case it was changed since early boot
1085 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1089 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1090 err
= cpu_check_up_prepare(cpu
);
1091 if (err
&& err
!= -EBUSY
)
1094 /* the FPU context is blank, nobody can own it */
1095 __cpu_disable_lazy_restore(cpu
);
1097 common_cpu_up(cpu
, tidle
);
1100 * We have to walk the irq descriptors to setup the vector
1101 * space for the cpu which comes online. Prevent irq
1102 * alloc/free across the bringup.
1106 err
= do_boot_cpu(apicid
, cpu
, tidle
);
1109 irq_unlock_sparse();
1110 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err
, cpu
);
1115 * Check TSC synchronization with the AP (keep irqs disabled
1118 local_irq_save(flags
);
1119 check_tsc_sync_source(cpu
);
1120 local_irq_restore(flags
);
1122 while (!cpu_online(cpu
)) {
1124 touch_nmi_watchdog();
1127 irq_unlock_sparse();
1133 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1135 void arch_disable_smp_support(void)
1137 disable_ioapic_support();
1141 * Fall back to non SMP mode after errors.
1143 * RED-PEN audit/test this more. I bet there is more state messed up here.
1145 static __init
void disable_smp(void)
1147 pr_info("SMP disabled\n");
1149 disable_ioapic_support();
1151 init_cpu_present(cpumask_of(0));
1152 init_cpu_possible(cpumask_of(0));
1154 if (smp_found_config
)
1155 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1157 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
1158 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1159 cpumask_set_cpu(0, topology_core_cpumask(0));
1170 * Various sanity checks.
1172 static int __init
smp_sanity_check(unsigned max_cpus
)
1176 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1177 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
1181 pr_warn("More than 8 CPUs detected - skipping them\n"
1182 "Use CONFIG_X86_BIGSMP\n");
1185 for_each_present_cpu(cpu
) {
1187 set_cpu_present(cpu
, false);
1192 for_each_possible_cpu(cpu
) {
1194 set_cpu_possible(cpu
, false);
1202 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1203 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1204 hard_smp_processor_id());
1206 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1210 * If we couldn't find an SMP configuration at boot time,
1211 * get out of here now!
1213 if (!smp_found_config
&& !acpi_lapic
) {
1215 pr_notice("SMP motherboard not detected\n");
1216 return SMP_NO_CONFIG
;
1220 * Should not be necessary because the MP table should list the boot
1221 * CPU too, but we do it for the sake of robustness anyway.
1223 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1224 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1225 boot_cpu_physical_apicid
);
1226 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1231 * If we couldn't find a local APIC, then get out of here now!
1233 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) &&
1235 if (!disable_apic
) {
1236 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1237 boot_cpu_physical_apicid
);
1238 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1244 * If SMP should be disabled, then really disable it!
1247 pr_info("SMP mode deactivated\n");
1248 return SMP_FORCE_UP
;
1254 static void __init
smp_cpu_index_default(void)
1257 struct cpuinfo_x86
*c
;
1259 for_each_possible_cpu(i
) {
1261 /* mark all to hotplug */
1262 c
->cpu_index
= nr_cpu_ids
;
1267 * Prepare for SMP bootup. The MP table or ACPI has been read
1268 * earlier. Just do some sanity checking here and enable APIC mode.
1270 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1274 smp_cpu_index_default();
1277 * Setup boot CPU information
1279 smp_store_boot_cpu_info(); /* Final full version of the data */
1280 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1283 current_thread_info()->cpu
= 0; /* needed? */
1284 for_each_possible_cpu(i
) {
1285 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1286 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1287 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1289 set_cpu_sibling_map(0);
1291 switch (smp_sanity_check(max_cpus
)) {
1294 if (APIC_init_uniprocessor())
1295 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1302 apic_bsp_setup(false);
1308 default_setup_apic_routing();
1310 if (read_apic_id() != boot_cpu_physical_apicid
) {
1311 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1312 read_apic_id(), boot_cpu_physical_apicid
);
1313 /* Or can we switch back to PIC here? */
1316 cpu0_logical_apicid
= apic_bsp_setup(false);
1318 pr_info("CPU%d: ", 0);
1319 print_cpu_info(&cpu_data(0));
1324 set_mtrr_aps_delayed_init();
1326 smp_quirk_init_udelay();
1329 void arch_enable_nonboot_cpus_begin(void)
1331 set_mtrr_aps_delayed_init();
1334 void arch_enable_nonboot_cpus_end(void)
1340 * Early setup to make printk work.
1342 void __init
native_smp_prepare_boot_cpu(void)
1344 int me
= smp_processor_id();
1345 switch_to_new_gdt(me
);
1346 /* already set me in cpu_online_mask in boot_cpu_init() */
1347 cpumask_set_cpu(me
, cpu_callout_mask
);
1348 cpu_set_state_online(me
);
1351 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1353 pr_debug("Boot done\n");
1357 setup_ioapic_dest();
1361 static int __initdata setup_possible_cpus
= -1;
1362 static int __init
_setup_possible_cpus(char *str
)
1364 get_option(&str
, &setup_possible_cpus
);
1367 early_param("possible_cpus", _setup_possible_cpus
);
1371 * cpu_possible_mask should be static, it cannot change as cpu's
1372 * are onlined, or offlined. The reason is per-cpu data-structures
1373 * are allocated by some modules at init time, and dont expect to
1374 * do this dynamically on cpu arrival/departure.
1375 * cpu_present_mask on the other hand can change dynamically.
1376 * In case when cpu_hotplug is not compiled, then we resort to current
1377 * behaviour, which is cpu_possible == cpu_present.
1380 * Three ways to find out the number of additional hotplug CPUs:
1381 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1382 * - The user can overwrite it with possible_cpus=NUM
1383 * - Otherwise don't reserve additional CPUs.
1384 * We do this because additional CPUs waste a lot of memory.
1387 __init
void prefill_possible_map(void)
1391 /* no processor from mptable or madt */
1392 if (!num_processors
)
1395 i
= setup_max_cpus
?: 1;
1396 if (setup_possible_cpus
== -1) {
1397 possible
= num_processors
;
1398 #ifdef CONFIG_HOTPLUG_CPU
1400 possible
+= disabled_cpus
;
1406 possible
= setup_possible_cpus
;
1408 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1410 /* nr_cpu_ids could be reduced via nr_cpus= */
1411 if (possible
> nr_cpu_ids
) {
1412 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1413 possible
, nr_cpu_ids
);
1414 possible
= nr_cpu_ids
;
1417 #ifdef CONFIG_HOTPLUG_CPU
1418 if (!setup_max_cpus
)
1421 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1422 possible
, setup_max_cpus
);
1426 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1427 possible
, max_t(int, possible
- num_processors
, 0));
1429 for (i
= 0; i
< possible
; i
++)
1430 set_cpu_possible(i
, true);
1431 for (; i
< NR_CPUS
; i
++)
1432 set_cpu_possible(i
, false);
1434 nr_cpu_ids
= possible
;
1437 #ifdef CONFIG_HOTPLUG_CPU
1439 static void remove_siblinginfo(int cpu
)
1442 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1444 for_each_cpu(sibling
, topology_core_cpumask(cpu
)) {
1445 cpumask_clear_cpu(cpu
, topology_core_cpumask(sibling
));
1447 * last thread sibling in this cpu core going down
1449 if (cpumask_weight(topology_sibling_cpumask(cpu
)) == 1)
1450 cpu_data(sibling
).booted_cores
--;
1453 for_each_cpu(sibling
, topology_sibling_cpumask(cpu
))
1454 cpumask_clear_cpu(cpu
, topology_sibling_cpumask(sibling
));
1455 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1456 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1457 cpumask_clear(cpu_llc_shared_mask(cpu
));
1458 cpumask_clear(topology_sibling_cpumask(cpu
));
1459 cpumask_clear(topology_core_cpumask(cpu
));
1460 c
->phys_proc_id
= 0;
1462 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1465 static void remove_cpu_from_maps(int cpu
)
1467 set_cpu_online(cpu
, false);
1468 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1469 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1470 /* was set by cpu_init() */
1471 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1472 numa_remove_cpu(cpu
);
1475 void cpu_disable_common(void)
1477 int cpu
= smp_processor_id();
1479 remove_siblinginfo(cpu
);
1481 /* It's now safe to remove this processor from the online map */
1483 remove_cpu_from_maps(cpu
);
1484 unlock_vector_lock();
1488 int native_cpu_disable(void)
1492 ret
= check_irq_vectors_for_cpu_disable();
1497 cpu_disable_common();
1502 int common_cpu_die(unsigned int cpu
)
1506 /* We don't do anything here: idle task is faking death itself. */
1508 /* They ack this in play_dead() by setting CPU_DEAD */
1509 if (cpu_wait_death(cpu
, 5)) {
1510 if (system_state
== SYSTEM_RUNNING
)
1511 pr_info("CPU %u is now offline\n", cpu
);
1513 pr_err("CPU %u didn't die...\n", cpu
);
1520 void native_cpu_die(unsigned int cpu
)
1522 common_cpu_die(cpu
);
1525 void play_dead_common(void)
1528 reset_lazy_tlbstate();
1529 amd_e400_remove_cpu(raw_smp_processor_id());
1532 (void)cpu_report_death();
1535 * With physical CPU hotplug, we should halt the cpu
1537 local_irq_disable();
1540 static bool wakeup_cpu0(void)
1542 if (smp_processor_id() == 0 && enable_start_cpu0
)
1549 * We need to flush the caches before going to sleep, lest we have
1550 * dirty data in our caches when we come back up.
1552 static inline void mwait_play_dead(void)
1554 unsigned int eax
, ebx
, ecx
, edx
;
1555 unsigned int highest_cstate
= 0;
1556 unsigned int highest_subcstate
= 0;
1560 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1562 if (!this_cpu_has(X86_FEATURE_CLFLUSH
))
1564 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1567 eax
= CPUID_MWAIT_LEAF
;
1569 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1572 * eax will be 0 if EDX enumeration is not valid.
1573 * Initialized below to cstate, sub_cstate value when EDX is valid.
1575 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1578 edx
>>= MWAIT_SUBSTATE_SIZE
;
1579 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1580 if (edx
& MWAIT_SUBSTATE_MASK
) {
1582 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1585 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1586 (highest_subcstate
- 1);
1590 * This should be a memory location in a cache line which is
1591 * unlikely to be touched by other processors. The actual
1592 * content is immaterial as it is not actually modified in any way.
1594 mwait_ptr
= ¤t_thread_info()->flags
;
1600 * The CLFLUSH is a workaround for erratum AAI65 for
1601 * the Xeon 7400 series. It's not clear it is actually
1602 * needed, but it should be harmless in either case.
1603 * The WBINVD is insufficient due to the spurious-wakeup
1604 * case where we return around the loop.
1609 __monitor(mwait_ptr
, 0, 0);
1613 * If NMI wants to wake up CPU0, start CPU0.
1620 static inline void hlt_play_dead(void)
1622 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1628 * If NMI wants to wake up CPU0, start CPU0.
1635 void native_play_dead(void)
1638 tboot_shutdown(TB_SHUTDOWN_WFS
);
1640 mwait_play_dead(); /* Only returns on failure */
1641 if (cpuidle_play_dead())
1645 #else /* ... !CONFIG_HOTPLUG_CPU */
1646 int native_cpu_disable(void)
1651 void native_cpu_die(unsigned int cpu
)
1653 /* We said "no" in __cpu_disable */
1657 void native_play_dead(void)