?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.11-rc5
[linux/fpc-iii.git] / arch / arm / mach-pxa / zeus.c
blobecbcaee5a2d5f8980c6946853cd638da78fd6838
1 /*
2 * Support for the Arcom ZEUS.
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * Loosely based on Arcom's 2.6.16.28.
7 * Maintained by Marc Zyngier <maz@misterjones.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/cpufreq.h>
15 #include <linux/interrupt.h>
16 #include <linux/leds.h>
17 #include <linux/irq.h>
18 #include <linux/pm.h>
19 #include <linux/gpio.h>
20 #include <linux/serial_8250.h>
21 #include <linux/dm9000.h>
22 #include <linux/mmc/host.h>
23 #include <linux/spi/spi.h>
24 #include <linux/spi/pxa2xx_spi.h>
25 #include <linux/mtd/mtd.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/mtd/physmap.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/pxa-i2c.h>
30 #include <linux/platform_data/pca953x.h>
31 #include <linux/apm-emulation.h>
32 #include <linux/can/platform/mcp251x.h>
33 #include <linux/regulator/fixed.h>
34 #include <linux/regulator/machine.h>
35
36 #include <asm/mach-types.h>
37 #include <asm/suspend.h>
38 #include <asm/system_info.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/map.h>
41
42 #include "pxa27x.h"
43 #include <mach/regs-uart.h>
44 #include <linux/platform_data/usb-ohci-pxa27x.h>
45 #include <linux/platform_data/mmc-pxamci.h>
46 #include "pxa27x-udc.h"
47 #include "udc.h"
48 #include <linux/platform_data/video-pxafb.h>
49 #include "pm.h"
50 #include <mach/audio.h>
51 #include <linux/platform_data/pcmcia-pxa2xx_viper.h>
52 #include "zeus.h"
53 #include <mach/smemc.h>
54
55 #include "generic.h"
56
57 /*
58 * Interrupt handling
59 */
60
61 static unsigned long zeus_irq_enabled_mask;
62 static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
63 static const int zeus_isa_irq_map[] = {
64 0, /* ISA irq #0, invalid */
65 0, /* ISA irq #1, invalid */
66 0, /* ISA irq #2, invalid */
67 1 << 0, /* ISA irq #3 */
68 1 << 1, /* ISA irq #4 */
69 1 << 2, /* ISA irq #5 */
70 1 << 3, /* ISA irq #6 */
71 1 << 4, /* ISA irq #7 */
72 0, /* ISA irq #8, invalid */
73 0, /* ISA irq #9, invalid */
74 1 << 5, /* ISA irq #10 */
75 1 << 6, /* ISA irq #11 */
76 1 << 7, /* ISA irq #12 */
77 };
78
79 static inline int zeus_irq_to_bitmask(unsigned int irq)
80 {
81 return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
82 }
83
84 static inline int zeus_bit_to_irq(int bit)
85 {
86 return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
87 }
88
89 static void zeus_ack_irq(struct irq_data *d)
90 {
91 __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
92 }
93
94 static void zeus_mask_irq(struct irq_data *d)
95 {
96 zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
97 }
98
99 static void zeus_unmask_irq(struct irq_data *d)
100 {
101 zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
102 }
103
104 static inline unsigned long zeus_irq_pending(void)
105 {
106 return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
107 }
108
109 static void zeus_irq_handler(struct irq_desc *desc)
110 {
111 unsigned int irq;
112 unsigned long pending;
113
114 pending = zeus_irq_pending();
115 do {
116 /* we're in a chained irq handler,
117 * so ack the interrupt by hand */
118 desc->irq_data.chip->irq_ack(&desc->irq_data);
119
120 if (likely(pending)) {
121 irq = zeus_bit_to_irq(__ffs(pending));
122 generic_handle_irq(irq);
123 }
124 pending = zeus_irq_pending();
125 } while (pending);
126 }
127
128 static struct irq_chip zeus_irq_chip = {
129 .name = "ISA",
130 .irq_ack = zeus_ack_irq,
131 .irq_mask = zeus_mask_irq,
132 .irq_unmask = zeus_unmask_irq,
133 };
134
135 static void __init zeus_init_irq(void)
136 {
137 int level;
138 int isa_irq;
139
140 pxa27x_init_irq();
141
142 /* Peripheral IRQs. It would be nice to move those inside driver
143 configuration, but it is not supported at the moment. */
144 irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
145 irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
146 irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
147 irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
148 IRQ_TYPE_EDGE_FALLING);
149 irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
150
151 /* Setup ISA IRQs */
152 for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
153 isa_irq = zeus_bit_to_irq(level);
154 irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
155 handle_edge_irq);
156 irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
157 }
158
159 irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
160 irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
161 }
162
163
164 /*
165 * Platform devices
166 */
167
168 /* Flash */
169 static struct resource zeus_mtd_resources[] = {
170 [0] = { /* NOR Flash (up to 64MB) */
171 .start = ZEUS_FLASH_PHYS,
172 .end = ZEUS_FLASH_PHYS + SZ_64M - 1,
173 .flags = IORESOURCE_MEM,
174 },
175 [1] = { /* SRAM */
176 .start = ZEUS_SRAM_PHYS,
177 .end = ZEUS_SRAM_PHYS + SZ_512K - 1,
178 .flags = IORESOURCE_MEM,
179 },
180 };
181
182 static struct physmap_flash_data zeus_flash_data[] = {
183 [0] = {
184 .width = 2,
185 .parts = NULL,
186 .nr_parts = 0,
187 },
188 };
189
190 static struct platform_device zeus_mtd_devices[] = {
191 [0] = {
192 .name = "physmap-flash",
193 .id = 0,
194 .dev = {
195 .platform_data = &zeus_flash_data[0],
196 },
197 .resource = &zeus_mtd_resources[0],
198 .num_resources = 1,
199 },
200 };
201
202 /* Serial */
203 static struct resource zeus_serial_resources[] = {
204 {
205 .start = 0x10000000,
206 .end = 0x1000000f,
207 .flags = IORESOURCE_MEM,
208 },
209 {
210 .start = 0x10800000,
211 .end = 0x1080000f,
212 .flags = IORESOURCE_MEM,
213 },
214 {
215 .start = 0x11000000,
216 .end = 0x1100000f,
217 .flags = IORESOURCE_MEM,
218 },
219 {
220 .start = 0x40100000,
221 .end = 0x4010001f,
222 .flags = IORESOURCE_MEM,
223 },
224 {
225 .start = 0x40200000,
226 .end = 0x4020001f,
227 .flags = IORESOURCE_MEM,
228 },
229 {
230 .start = 0x40700000,
231 .end = 0x4070001f,
232 .flags = IORESOURCE_MEM,
233 },
234 };
235
236 static struct plat_serial8250_port serial_platform_data[] = {
237 /* External UARTs */
238 /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
239 { /* COM1 */
240 .mapbase = 0x10000000,
241 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO),
242 .irqflags = IRQF_TRIGGER_RISING,
243 .uartclk = 14745600,
244 .regshift = 1,
245 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
246 .iotype = UPIO_MEM,
247 },
248 { /* COM2 */
249 .mapbase = 0x10800000,
250 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO),
251 .irqflags = IRQF_TRIGGER_RISING,
252 .uartclk = 14745600,
253 .regshift = 1,
254 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
255 .iotype = UPIO_MEM,
256 },
257 { /* COM3 */
258 .mapbase = 0x11000000,
259 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO),
260 .irqflags = IRQF_TRIGGER_RISING,
261 .uartclk = 14745600,
262 .regshift = 1,
263 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
264 .iotype = UPIO_MEM,
265 },
266 { /* COM4 */
267 .mapbase = 0x11800000,
268 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO),
269 .irqflags = IRQF_TRIGGER_RISING,
270 .uartclk = 14745600,
271 .regshift = 1,
272 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
273 .iotype = UPIO_MEM,
274 },
275 /* Internal UARTs */
276 { /* FFUART */
277 .membase = (void *)&FFUART,
278 .mapbase = __PREG(FFUART),
279 .irq = IRQ_FFUART,
280 .uartclk = 921600 * 16,
281 .regshift = 2,
282 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
283 .iotype = UPIO_MEM,
284 },
285 { /* BTUART */
286 .membase = (void *)&BTUART,
287 .mapbase = __PREG(BTUART),
288 .irq = IRQ_BTUART,
289 .uartclk = 921600 * 16,
290 .regshift = 2,
291 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
292 .iotype = UPIO_MEM,
293 },
294 { /* STUART */
295 .membase = (void *)&STUART,
296 .mapbase = __PREG(STUART),
297 .irq = IRQ_STUART,
298 .uartclk = 921600 * 16,
299 .regshift = 2,
300 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
301 .iotype = UPIO_MEM,
302 },
303 { },
304 };
305
306 static struct platform_device zeus_serial_device = {
307 .name = "serial8250",
308 .id = PLAT8250_DEV_PLATFORM,
309 .dev = {
310 .platform_data = serial_platform_data,
311 },
312 .num_resources = ARRAY_SIZE(zeus_serial_resources),
313 .resource = zeus_serial_resources,
314 };
315
316 /* Ethernet */
317 static struct resource zeus_dm9k0_resource[] = {
318 [0] = {
319 .start = ZEUS_ETH0_PHYS,
320 .end = ZEUS_ETH0_PHYS + 1,
321 .flags = IORESOURCE_MEM
322 },
323 [1] = {
324 .start = ZEUS_ETH0_PHYS + 2,
325 .end = ZEUS_ETH0_PHYS + 3,
326 .flags = IORESOURCE_MEM
327 },
328 [2] = {
329 .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
330 .end = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
331 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
332 },
333 };
334
335 static struct resource zeus_dm9k1_resource[] = {
336 [0] = {
337 .start = ZEUS_ETH1_PHYS,
338 .end = ZEUS_ETH1_PHYS + 1,
339 .flags = IORESOURCE_MEM
340 },
341 [1] = {
342 .start = ZEUS_ETH1_PHYS + 2,
343 .end = ZEUS_ETH1_PHYS + 3,
344 .flags = IORESOURCE_MEM,
345 },
346 [2] = {
347 .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
348 .end = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
349 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
350 },
351 };
352
353 static struct dm9000_plat_data zeus_dm9k_platdata = {
354 .flags = DM9000_PLATF_16BITONLY,
355 };
356
357 static struct platform_device zeus_dm9k0_device = {
358 .name = "dm9000",
359 .id = 0,
360 .num_resources = ARRAY_SIZE(zeus_dm9k0_resource),
361 .resource = zeus_dm9k0_resource,
362 .dev = {
363 .platform_data = &zeus_dm9k_platdata,
364 }
365 };
366
367 static struct platform_device zeus_dm9k1_device = {
368 .name = "dm9000",
369 .id = 1,
370 .num_resources = ARRAY_SIZE(zeus_dm9k1_resource),
371 .resource = zeus_dm9k1_resource,
372 .dev = {
373 .platform_data = &zeus_dm9k_platdata,
374 }
375 };
376
377 /* External SRAM */
378 static struct resource zeus_sram_resource = {
379 .start = ZEUS_SRAM_PHYS,
380 .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
381 .flags = IORESOURCE_MEM,
382 };
383
384 static struct platform_device zeus_sram_device = {
385 .name = "pxa2xx-8bit-sram",
386 .id = 0,
387 .num_resources = 1,
388 .resource = &zeus_sram_resource,
389 };
390
391 /* SPI interface on SSP3 */
392 static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
393 .num_chipselect = 1,
394 .enable_dma = 1,
395 };
396
397 /* CAN bus on SPI */
398 static struct regulator_consumer_supply can_regulator_consumer =
399 REGULATOR_SUPPLY("vdd", "spi3.0");
400
401 static struct regulator_init_data can_regulator_init_data = {
402 .constraints = {
403 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
404 },
405 .consumer_supplies = &can_regulator_consumer,
406 .num_consumer_supplies = 1,
407 };
408
409 static struct fixed_voltage_config can_regulator_pdata = {
410 .supply_name = "CAN_SHDN",
411 .microvolts = 3300000,
412 .gpio = ZEUS_CAN_SHDN_GPIO,
413 .init_data = &can_regulator_init_data,
414 };
415
416 static struct platform_device can_regulator_device = {
417 .name = "reg-fixed-voltage",
418 .id = 0,
419 .dev = {
420 .platform_data = &can_regulator_pdata,
421 },
422 };
423
424 static struct mcp251x_platform_data zeus_mcp2515_pdata = {
425 .oscillator_frequency = 16*1000*1000,
426 };
427
428 static struct spi_board_info zeus_spi_board_info[] = {
429 [0] = {
430 .modalias = "mcp2515",
431 .platform_data = &zeus_mcp2515_pdata,
432 .irq = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
433 .max_speed_hz = 1*1000*1000,
434 .bus_num = 3,
435 .mode = SPI_MODE_0,
436 .chip_select = 0,
437 },
438 };
439
440 /* Leds */
441 static struct gpio_led zeus_leds[] = {
442 [0] = {
443 .name = "zeus:yellow:1",
444 .default_trigger = "heartbeat",
445 .gpio = ZEUS_EXT0_GPIO(3),
446 .active_low = 1,
447 },
448 [1] = {
449 .name = "zeus:yellow:2",
450 .default_trigger = "default-on",
451 .gpio = ZEUS_EXT0_GPIO(4),
452 .active_low = 1,
453 },
454 [2] = {
455 .name = "zeus:yellow:3",
456 .default_trigger = "default-on",
457 .gpio = ZEUS_EXT0_GPIO(5),
458 .active_low = 1,
459 },
460 };
461
462 static struct gpio_led_platform_data zeus_leds_info = {
463 .leds = zeus_leds,
464 .num_leds = ARRAY_SIZE(zeus_leds),
465 };
466
467 static struct platform_device zeus_leds_device = {
468 .name = "leds-gpio",
469 .id = -1,
470 .dev = {
471 .platform_data = &zeus_leds_info,
472 },
473 };
474
475 static void zeus_cf_reset(int state)
476 {
477 u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
478
479 if (state)
480 cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
481 else
482 cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
483
484 __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
485 }
486
487 static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
488 .cd_gpio = ZEUS_CF_CD_GPIO,
489 .rdy_gpio = ZEUS_CF_RDY_GPIO,
490 .pwr_gpio = ZEUS_CF_PWEN_GPIO,
491 .reset = zeus_cf_reset,
492 };
493
494 static struct platform_device zeus_pcmcia_device = {
495 .name = "zeus-pcmcia",
496 .id = -1,
497 .dev = {
498 .platform_data = &zeus_pcmcia_info,
499 },
500 };
501
502 static struct resource zeus_max6369_resource = {
503 .start = ZEUS_CPLD_EXTWDOG_PHYS,
504 .end = ZEUS_CPLD_EXTWDOG_PHYS,
505 .flags = IORESOURCE_MEM,
506 };
507
508 struct platform_device zeus_max6369_device = {
509 .name = "max6369_wdt",
510 .id = -1,
511 .resource = &zeus_max6369_resource,
512 .num_resources = 1,
513 };
514
515 /* AC'97 */
516 static pxa2xx_audio_ops_t zeus_ac97_info = {
517 .reset_gpio = 95,
518 };
519
520
521 /*
522 * USB host
523 */
524
525 static struct regulator_consumer_supply zeus_ohci_regulator_supplies[] = {
526 REGULATOR_SUPPLY("vbus2", "pxa27x-ohci"),
527 };
528
529 static struct regulator_init_data zeus_ohci_regulator_data = {
530 .constraints = {
531 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
532 },
533 .num_consumer_supplies = ARRAY_SIZE(zeus_ohci_regulator_supplies),
534 .consumer_supplies = zeus_ohci_regulator_supplies,
535 };
536
537 static struct fixed_voltage_config zeus_ohci_regulator_config = {
538 .supply_name = "vbus2",
539 .microvolts = 5000000, /* 5.0V */
540 .gpio = ZEUS_USB2_PWREN_GPIO,
541 .enable_high = 1,
542 .startup_delay = 0,
543 .init_data = &zeus_ohci_regulator_data,
544 };
545
546 static struct platform_device zeus_ohci_regulator_device = {
547 .name = "reg-fixed-voltage",
548 .id = 1,
549 .dev = {
550 .platform_data = &zeus_ohci_regulator_config,
551 },
552 };
553
554 static struct pxaohci_platform_data zeus_ohci_platform_data = {
555 .port_mode = PMM_NPS_MODE,
556 /* Clear Power Control Polarity Low and set Power Sense
557 * Polarity Low. Supply power to USB ports. */
558 .flags = ENABLE_PORT_ALL | POWER_SENSE_LOW,
559 };
560
561 static void zeus_register_ohci(void)
562 {
563 /* Port 2 is shared between host and client interface. */
564 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
565
566 pxa_set_ohci_info(&zeus_ohci_platform_data);
567 }
568
569 /*
570 * Flat Panel
571 */
572
573 static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
574 {
575 gpio_set_value(ZEUS_LCD_EN_GPIO, on);
576 }
577
578 static void zeus_backlight_power(int on)
579 {
580 gpio_set_value(ZEUS_BKLEN_GPIO, on);
581 }
582
583 static int zeus_setup_fb_gpios(void)
584 {
585 int err;
586
587 if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
588 goto out_err;
589
590 if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
591 goto out_err_lcd;
592
593 if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
594 goto out_err_lcd;
595
596 if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
597 goto out_err_bkl;
598
599 return 0;
600
601 out_err_bkl:
602 gpio_free(ZEUS_BKLEN_GPIO);
603 out_err_lcd:
604 gpio_free(ZEUS_LCD_EN_GPIO);
605 out_err:
606 return err;
607 }
608
609 static struct pxafb_mode_info zeus_fb_mode_info[] = {
610 {
611 .pixclock = 39722,
612
613 .xres = 640,
614 .yres = 480,
615
616 .bpp = 16,
617
618 .hsync_len = 63,
619 .left_margin = 16,
620 .right_margin = 81,
621
622 .vsync_len = 2,
623 .upper_margin = 12,
624 .lower_margin = 31,
625
626 .sync = 0,
627 },
628 };
629
630 static struct pxafb_mach_info zeus_fb_info = {
631 .modes = zeus_fb_mode_info,
632 .num_modes = 1,
633 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
634 .pxafb_lcd_power = zeus_lcd_power,
635 .pxafb_backlight_power = zeus_backlight_power,
636 };
637
638 /*
639 * MMC/SD Device
640 *
641 * The card detect interrupt isn't debounced so we delay it by 250ms
642 * to give the card a chance to fully insert/eject.
643 */
644
645 static struct pxamci_platform_data zeus_mci_platform_data = {
646 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
647 .detect_delay_ms = 250,
648 .gpio_card_detect = ZEUS_MMC_CD_GPIO,
649 .gpio_card_ro = ZEUS_MMC_WP_GPIO,
650 .gpio_card_ro_invert = 1,
651 .gpio_power = -1
652 };
653
654 /*
655 * USB Device Controller
656 */
657 static void zeus_udc_command(int cmd)
658 {
659 switch (cmd) {
660 case PXA2XX_UDC_CMD_DISCONNECT:
661 pr_info("zeus: disconnecting USB client\n");
662 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
663 break;
664
665 case PXA2XX_UDC_CMD_CONNECT:
666 pr_info("zeus: connecting USB client\n");
667 UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
668 break;
669 }
670 }
671
672 static struct pxa2xx_udc_mach_info zeus_udc_info = {
673 .udc_command = zeus_udc_command,
674 };
675
676 static struct platform_device *zeus_devices[] __initdata = {
677 &zeus_serial_device,
678 &zeus_mtd_devices[0],
679 &zeus_dm9k0_device,
680 &zeus_dm9k1_device,
681 &zeus_sram_device,
682 &zeus_leds_device,
683 &zeus_pcmcia_device,
684 &zeus_max6369_device,
685 &can_regulator_device,
686 &zeus_ohci_regulator_device,
687 };
688
689 #ifdef CONFIG_PM
690 static void zeus_power_off(void)
691 {
692 local_irq_disable();
693 cpu_suspend(PWRMODE_DEEPSLEEP, pxa27x_finish_suspend);
694 }
695 #else
696 #define zeus_power_off NULL
697 #endif
698
699 #ifdef CONFIG_APM_EMULATION
700 static void zeus_get_power_status(struct apm_power_info *info)
701 {
702 /* Power supply is always present */
703 info->ac_line_status = APM_AC_ONLINE;
704 info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT;
705 info->battery_flag = APM_BATTERY_FLAG_NOT_PRESENT;
706 }
707
708 static inline void zeus_setup_apm(void)
709 {
710 apm_get_power_status = zeus_get_power_status;
711 }
712 #else
713 static inline void zeus_setup_apm(void)
714 {
715 }
716 #endif
717
718 static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
719 unsigned ngpio, void *context)
720 {
721 int i;
722 u8 pcb_info = 0;
723
724 for (i = 0; i < 8; i++) {
725 int pcb_bit = gpio + i + 8;
726
727 if (gpio_request(pcb_bit, "pcb info")) {
728 dev_err(&client->dev, "Can't request pcb info %d\n", i);
729 continue;
730 }
731
732 if (gpio_direction_input(pcb_bit)) {
733 dev_err(&client->dev, "Can't read pcb info %d\n", i);
734 gpio_free(pcb_bit);
735 continue;
736 }
737
738 pcb_info |= !!gpio_get_value(pcb_bit) << i;
739
740 gpio_free(pcb_bit);
741 }
742
743 dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
744 pcb_info >> 4, pcb_info & 0xf);
745
746 return 0;
747 }
748
749 static struct pca953x_platform_data zeus_pca953x_pdata[] = {
750 [0] = { .gpio_base = ZEUS_EXT0_GPIO_BASE, },
751 [1] = {
752 .gpio_base = ZEUS_EXT1_GPIO_BASE,
753 .setup = zeus_get_pcb_info,
754 },
755 [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
756 };
757
758 static struct i2c_board_info __initdata zeus_i2c_devices[] = {
759 {
760 I2C_BOARD_INFO("pca9535", 0x21),
761 .platform_data = &zeus_pca953x_pdata[0],
762 },
763 {
764 I2C_BOARD_INFO("pca9535", 0x22),
765 .platform_data = &zeus_pca953x_pdata[1],
766 },
767 {
768 I2C_BOARD_INFO("pca9535", 0x20),
769 .platform_data = &zeus_pca953x_pdata[2],
770 .irq = PXA_GPIO_TO_IRQ(ZEUS_EXTGPIO_GPIO),
771 },
772 { I2C_BOARD_INFO("lm75a", 0x48) },
773 { I2C_BOARD_INFO("24c01", 0x50) },
774 { I2C_BOARD_INFO("isl1208", 0x6f) },
775 };
776
777 static mfp_cfg_t zeus_pin_config[] __initdata = {
778 /* AC97 */
779 GPIO28_AC97_BITCLK,
780 GPIO29_AC97_SDATA_IN_0,
781 GPIO30_AC97_SDATA_OUT,
782 GPIO31_AC97_SYNC,
783
784 GPIO15_nCS_1,
785 GPIO78_nCS_2,
786 GPIO80_nCS_4,
787 GPIO33_nCS_5,
788
789 GPIO22_GPIO,
790 GPIO32_MMC_CLK,
791 GPIO92_MMC_DAT_0,
792 GPIO109_MMC_DAT_1,
793 GPIO110_MMC_DAT_2,
794 GPIO111_MMC_DAT_3,
795 GPIO112_MMC_CMD,
796
797 GPIO88_USBH1_PWR,
798 GPIO89_USBH1_PEN,
799 GPIO119_USBH2_PWR,
800 GPIO120_USBH2_PEN,
801
802 GPIO86_LCD_LDD_16,
803 GPIO87_LCD_LDD_17,
804
805 GPIO102_GPIO,
806 GPIO104_CIF_DD_2,
807 GPIO105_CIF_DD_1,
808
809 GPIO81_SSP3_TXD,
810 GPIO82_SSP3_RXD,
811 GPIO83_SSP3_SFRM,
812 GPIO84_SSP3_SCLK,
813
814 GPIO48_nPOE,
815 GPIO49_nPWE,
816 GPIO50_nPIOR,
817 GPIO51_nPIOW,
818 GPIO85_nPCE_1,
819 GPIO54_nPCE_2,
820 GPIO79_PSKTSEL,
821 GPIO55_nPREG,
822 GPIO56_nPWAIT,
823 GPIO57_nIOIS16,
824 GPIO36_GPIO, /* CF CD */
825 GPIO97_GPIO, /* CF PWREN */
826 GPIO99_GPIO, /* CF RDY */
827 };
828
829 /*
830 * DM9k MSCx settings: SRAM, 16 bits
831 * 17 cycles delay first access
832 * 5 cycles delay next access
833 * 13 cycles recovery time
834 * faster device
835 */
836 #define DM9K_MSC_VALUE 0xe4c9
837
838 static void __init zeus_init(void)
839 {
840 u16 dm9000_msc = DM9K_MSC_VALUE;
841 u32 msc0, msc1;
842
843 system_rev = __raw_readw(ZEUS_CPLD_VERSION);
844 pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
845
846 /* Fix timings for dm9000s (CS1/CS2)*/
847 msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
848 msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
849 __raw_writel(msc0, MSC0);
850 __raw_writel(msc1, MSC1);
851
852 pm_power_off = zeus_power_off;
853 zeus_setup_apm();
854
855 pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
856
857 platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
858
859 zeus_register_ohci();
860
861 if (zeus_setup_fb_gpios())
862 pr_err("Failed to setup fb gpios\n");
863 else
864 pxa_set_fb_info(NULL, &zeus_fb_info);
865
866 pxa_set_mci_info(&zeus_mci_platform_data);
867 pxa_set_udc_info(&zeus_udc_info);
868 pxa_set_ac97_info(&zeus_ac97_info);
869 pxa_set_i2c_info(NULL);
870 i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
871 pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
872 spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
873
874 regulator_has_full_constraints();
875 }
876
877 static struct map_desc zeus_io_desc[] __initdata = {
878 {
879 .virtual = (unsigned long)ZEUS_CPLD_VERSION,
880 .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
881 .length = 0x1000,
882 .type = MT_DEVICE,
883 },
884 {
885 .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ,
886 .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
887 .length = 0x1000,
888 .type = MT_DEVICE,
889 },
890 {
891 .virtual = (unsigned long)ZEUS_CPLD_CONTROL,
892 .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
893 .length = 0x1000,
894 .type = MT_DEVICE,
895 },
896 {
897 .virtual = (unsigned long)ZEUS_PC104IO,
898 .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS),
899 .length = 0x00800000,
900 .type = MT_DEVICE,
901 },
902 };
903
904 static void __init zeus_map_io(void)
905 {
906 pxa27x_map_io();
907
908 iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
909
910 /* Clear PSPR to ensure a full restart on wake-up. */
911 PMCR = PSPR = 0;
912
913 /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
914 writel(readl(OSCC) | OSCC_OON, OSCC);
915
916 /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
917 * float chip selects and PCMCIA */
918 PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
919 }
920
921 MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
922 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
923 .atag_offset = 0x100,
924 .map_io = zeus_map_io,
925 .nr_irqs = ZEUS_NR_IRQS,
926 .init_irq = zeus_init_irq,
927 .handle_irq = pxa27x_handle_irq,
928 .init_time = pxa_timer_init,
929 .init_machine = zeus_init,
930 .restart = pxa_restart,
931 MACHINE_END
932
Linux with added FPC-III support