2 * Asm versions of Xen pv-ops, suitable for either direct use or
3 * inlining. The inline versions are the same as the direct-use
4 * versions, with the pre- and post-amble chopped off.
6 * This code is encoded for size rather than absolute efficiency, with
7 * a view to being able to inline as much as possible.
9 * We only bother with direct forms (ie, vcpu in percpu data) of the
10 * operations here; the indirect forms are better handled in C, since
11 * they're generally too large to inline anyway.
14 #include <asm/asm-offsets.h>
15 #include <asm/percpu.h>
16 #include <asm/processor-flags.h>
17 #include <asm/frame.h>
22 * Enable events. This clears the event mask and tests the pending
23 * event status with one and operation. If there are pending events,
24 * then enter the hypervisor to get them handled.
26 ENTRY(xen_irq_enable_direct)
29 movb $0, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask
32 * Preempt here doesn't matter because that will deal with any
33 * pending interrupts. The pending check may end up being run
34 * on the wrong CPU, but that doesn't hurt.
37 /* Test for pending */
38 testb $0xff, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending
43 ENDPATCH(xen_irq_enable_direct)
46 ENDPROC(xen_irq_enable_direct)
47 RELOC(xen_irq_enable_direct, 2b+1)
51 * Disabling events is simply a matter of making the event mask
54 ENTRY(xen_irq_disable_direct)
55 movb $1, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask
56 ENDPATCH(xen_irq_disable_direct)
58 ENDPROC(xen_irq_disable_direct)
59 RELOC(xen_irq_disable_direct, 0)
62 * (xen_)save_fl is used to get the current interrupt enable status.
63 * Callers expect the status to be in X86_EFLAGS_IF, and other bits
64 * may be set in the return value. We take advantage of this by
65 * making sure that X86_EFLAGS_IF has the right value (and other bits
66 * in that byte are 0), but other bits in the return value are
67 * undefined. We need to toggle the state of the bit, because Xen and
68 * x86 use opposite senses (mask vs enable).
70 ENTRY(xen_save_fl_direct)
71 testb $0xff, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask
74 ENDPATCH(xen_save_fl_direct)
76 ENDPROC(xen_save_fl_direct)
77 RELOC(xen_save_fl_direct, 0)
81 * In principle the caller should be passing us a value return from
82 * xen_save_fl_direct, but for robustness sake we test only the
83 * X86_EFLAGS_IF flag rather than the whole byte. After setting the
84 * interrupt mask state, it checks for unmasked pending events and
85 * enters the hypervisor to get them delivered if so.
87 ENTRY(xen_restore_fl_direct)
90 testw $X86_EFLAGS_IF, %di
92 testb $X86_EFLAGS_IF>>8, %ah
94 setz PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask
96 * Preempt here doesn't matter because that will deal with any
97 * pending interrupts. The pending check may end up being run
98 * on the wrong CPU, but that doesn't hurt.
101 /* check for unmasked and pending */
102 cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending
106 ENDPATCH(xen_restore_fl_direct)
109 ENDPROC(xen_restore_fl_direct)
110 RELOC(xen_restore_fl_direct, 2b+1)
114 * Force an event check by making a hypercall, but preserve regs
115 * before making the call.
123 call xen_force_evtchn_callback
137 call xen_force_evtchn_callback
150 ENDPROC(check_events)