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ARM: mm: Recreate kernel mappings in early_paging_init()
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-pci.c
blobd7d6bc8968d2422d8b2e9fb44a695b35b17927d4
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/scatterlist.h>
24 #include <linux/io.h>
25 #include <linux/gpio.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/mmc/sdhci-pci-data.h>
28
29 #include "sdhci.h"
30
31 /*
32 * PCI device IDs
33 */
34 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
35 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
36 #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14
37 #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
38 #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
39 #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
40
41 /*
42 * PCI registers
43 */
44
45 #define PCI_SDHCI_IFPIO 0x00
46 #define PCI_SDHCI_IFDMA 0x01
47 #define PCI_SDHCI_IFVENDOR 0x02
48
49 #define PCI_SLOT_INFO 0x40 /* 8 bits */
50 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
51 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
52
53 #define MAX_SLOTS 8
54
55 struct sdhci_pci_chip;
56 struct sdhci_pci_slot;
57
58 struct sdhci_pci_fixes {
59 unsigned int quirks;
60 unsigned int quirks2;
61 bool allow_runtime_pm;
62
63 int (*probe) (struct sdhci_pci_chip *);
64
65 int (*probe_slot) (struct sdhci_pci_slot *);
66 void (*remove_slot) (struct sdhci_pci_slot *, int);
67
68 int (*suspend) (struct sdhci_pci_chip *);
69 int (*resume) (struct sdhci_pci_chip *);
70 };
71
72 struct sdhci_pci_slot {
73 struct sdhci_pci_chip *chip;
74 struct sdhci_host *host;
75 struct sdhci_pci_data *data;
76
77 int pci_bar;
78 int rst_n_gpio;
79 int cd_gpio;
80 int cd_irq;
81
82 void (*hw_reset)(struct sdhci_host *host);
83 };
84
85 struct sdhci_pci_chip {
86 struct pci_dev *pdev;
87
88 unsigned int quirks;
89 unsigned int quirks2;
90 bool allow_runtime_pm;
91 const struct sdhci_pci_fixes *fixes;
92
93 int num_slots; /* Slots on controller */
94 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
95 };
96
97
98 /*****************************************************************************\
99 * *
100 * Hardware specific quirk handling *
101 * *
102 \*****************************************************************************/
103
104 static int ricoh_probe(struct sdhci_pci_chip *chip)
105 {
106 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
107 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
108 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
109 return 0;
110 }
111
112 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
113 {
114 slot->host->caps =
115 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
116 & SDHCI_TIMEOUT_CLK_MASK) |
117
118 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
119 & SDHCI_CLOCK_BASE_MASK) |
120
121 SDHCI_TIMEOUT_CLK_UNIT |
122 SDHCI_CAN_VDD_330 |
123 SDHCI_CAN_DO_HISPD |
124 SDHCI_CAN_DO_SDMA;
125 return 0;
126 }
127
128 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
129 {
130 /* Apply a delay to allow controller to settle */
131 /* Otherwise it becomes confused if card state changed
132 during suspend */
133 msleep(500);
134 return 0;
135 }
136
137 static const struct sdhci_pci_fixes sdhci_ricoh = {
138 .probe = ricoh_probe,
139 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
140 SDHCI_QUIRK_FORCE_DMA |
141 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
142 };
143
144 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
145 .probe_slot = ricoh_mmc_probe_slot,
146 .resume = ricoh_mmc_resume,
147 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
148 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
149 SDHCI_QUIRK_NO_CARD_NO_RESET |
150 SDHCI_QUIRK_MISSING_CAPS
151 };
152
153 static const struct sdhci_pci_fixes sdhci_ene_712 = {
154 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
155 SDHCI_QUIRK_BROKEN_DMA,
156 };
157
158 static const struct sdhci_pci_fixes sdhci_ene_714 = {
159 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
160 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
161 SDHCI_QUIRK_BROKEN_DMA,
162 };
163
164 static const struct sdhci_pci_fixes sdhci_cafe = {
165 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
166 SDHCI_QUIRK_NO_BUSY_IRQ |
167 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
168 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
169 };
170
171 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
172 {
173 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
174 return 0;
175 }
176
177 /*
178 * ADMA operation is disabled for Moorestown platform due to
179 * hardware bugs.
180 */
181 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
182 {
183 /*
184 * slots number is fixed here for MRST as SDIO3/5 are never used and
185 * have hardware bugs.
186 */
187 chip->num_slots = 1;
188 return 0;
189 }
190
191 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
192 {
193 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
194 return 0;
195 }
196
197 #ifdef CONFIG_PM_RUNTIME
198
199 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
200 {
201 struct sdhci_pci_slot *slot = dev_id;
202 struct sdhci_host *host = slot->host;
203
204 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
205 return IRQ_HANDLED;
206 }
207
208 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
209 {
210 int err, irq, gpio = slot->cd_gpio;
211
212 slot->cd_gpio = -EINVAL;
213 slot->cd_irq = -EINVAL;
214
215 if (!gpio_is_valid(gpio))
216 return;
217
218 err = gpio_request(gpio, "sd_cd");
219 if (err < 0)
220 goto out;
221
222 err = gpio_direction_input(gpio);
223 if (err < 0)
224 goto out_free;
225
226 irq = gpio_to_irq(gpio);
227 if (irq < 0)
228 goto out_free;
229
230 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
231 IRQF_TRIGGER_FALLING, "sd_cd", slot);
232 if (err)
233 goto out_free;
234
235 slot->cd_gpio = gpio;
236 slot->cd_irq = irq;
237
238 return;
239
240 out_free:
241 gpio_free(gpio);
242 out:
243 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
244 }
245
246 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
247 {
248 if (slot->cd_irq >= 0)
249 free_irq(slot->cd_irq, slot);
250 if (gpio_is_valid(slot->cd_gpio))
251 gpio_free(slot->cd_gpio);
252 }
253
254 #else
255
256 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
257 {
258 }
259
260 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
261 {
262 }
263
264 #endif
265
266 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
267 {
268 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
269 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
270 MMC_CAP2_HC_ERASE_SZ;
271 return 0;
272 }
273
274 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
275 {
276 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
277 return 0;
278 }
279
280 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
281 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
282 .probe_slot = mrst_hc_probe_slot,
283 };
284
285 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
286 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
287 .probe = mrst_hc_probe,
288 };
289
290 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
291 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
292 .allow_runtime_pm = true,
293 };
294
295 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
296 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
297 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
298 .allow_runtime_pm = true,
299 .probe_slot = mfd_sdio_probe_slot,
300 };
301
302 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
303 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
304 .allow_runtime_pm = true,
305 .probe_slot = mfd_emmc_probe_slot,
306 };
307
308 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
309 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
310 .probe_slot = pch_hc_probe_slot,
311 };
312
313 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
314 {
315 u8 reg;
316
317 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
318 reg |= 0x10;
319 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
320 /* For eMMC, minimum is 1us but give it 9us for good measure */
321 udelay(9);
322 reg &= ~0x10;
323 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
324 /* For eMMC, minimum is 200us but give it 300us for good measure */
325 usleep_range(300, 1000);
326 }
327
328 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
329 {
330 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
331 MMC_CAP_HW_RESET;
332 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
333 slot->hw_reset = sdhci_pci_int_hw_reset;
334 return 0;
335 }
336
337 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
338 {
339 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
340 return 0;
341 }
342
343 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
344 .allow_runtime_pm = true,
345 .probe_slot = byt_emmc_probe_slot,
346 };
347
348 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
349 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
350 .allow_runtime_pm = true,
351 .probe_slot = byt_sdio_probe_slot,
352 };
353
354 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
355 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON,
356 .allow_runtime_pm = true,
357 };
358
359 /* O2Micro extra registers */
360 #define O2_SD_LOCK_WP 0xD3
361 #define O2_SD_MULTI_VCC3V 0xEE
362 #define O2_SD_CLKREQ 0xEC
363 #define O2_SD_CAPS 0xE0
364 #define O2_SD_ADMA1 0xE2
365 #define O2_SD_ADMA2 0xE7
366 #define O2_SD_INF_MOD 0xF1
367
368 static int o2_probe(struct sdhci_pci_chip *chip)
369 {
370 int ret;
371 u8 scratch;
372
373 switch (chip->pdev->device) {
374 case PCI_DEVICE_ID_O2_8220:
375 case PCI_DEVICE_ID_O2_8221:
376 case PCI_DEVICE_ID_O2_8320:
377 case PCI_DEVICE_ID_O2_8321:
378 /* This extra setup is required due to broken ADMA. */
379 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
380 if (ret)
381 return ret;
382 scratch &= 0x7f;
383 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
384
385 /* Set Multi 3 to VCC3V# */
386 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
387
388 /* Disable CLK_REQ# support after media DET */
389 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
390 if (ret)
391 return ret;
392 scratch |= 0x20;
393 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
394
395 /* Choose capabilities, enable SDMA. We have to write 0x01
396 * to the capabilities register first to unlock it.
397 */
398 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
399 if (ret)
400 return ret;
401 scratch |= 0x01;
402 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
403 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
404
405 /* Disable ADMA1/2 */
406 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
407 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
408
409 /* Disable the infinite transfer mode */
410 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
411 if (ret)
412 return ret;
413 scratch |= 0x08;
414 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
415
416 /* Lock WP */
417 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
418 if (ret)
419 return ret;
420 scratch |= 0x80;
421 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
422 }
423
424 return 0;
425 }
426
427 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
428 {
429 u8 scratch;
430 int ret;
431
432 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
433 if (ret)
434 return ret;
435
436 /*
437 * Turn PMOS on [bit 0], set over current detection to 2.4 V
438 * [bit 1:2] and enable over current debouncing [bit 6].
439 */
440 if (on)
441 scratch |= 0x47;
442 else
443 scratch &= ~0x47;
444
445 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
446 if (ret)
447 return ret;
448
449 return 0;
450 }
451
452 static int jmicron_probe(struct sdhci_pci_chip *chip)
453 {
454 int ret;
455 u16 mmcdev = 0;
456
457 if (chip->pdev->revision == 0) {
458 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
459 SDHCI_QUIRK_32BIT_DMA_SIZE |
460 SDHCI_QUIRK_32BIT_ADMA_SIZE |
461 SDHCI_QUIRK_RESET_AFTER_REQUEST |
462 SDHCI_QUIRK_BROKEN_SMALL_PIO;
463 }
464
465 /*
466 * JMicron chips can have two interfaces to the same hardware
467 * in order to work around limitations in Microsoft's driver.
468 * We need to make sure we only bind to one of them.
469 *
470 * This code assumes two things:
471 *
472 * 1. The PCI code adds subfunctions in order.
473 *
474 * 2. The MMC interface has a lower subfunction number
475 * than the SD interface.
476 */
477 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
478 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
479 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
480 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
481
482 if (mmcdev) {
483 struct pci_dev *sd_dev;
484
485 sd_dev = NULL;
486 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
487 mmcdev, sd_dev)) != NULL) {
488 if ((PCI_SLOT(chip->pdev->devfn) ==
489 PCI_SLOT(sd_dev->devfn)) &&
490 (chip->pdev->bus == sd_dev->bus))
491 break;
492 }
493
494 if (sd_dev) {
495 pci_dev_put(sd_dev);
496 dev_info(&chip->pdev->dev, "Refusing to bind to "
497 "secondary interface.\n");
498 return -ENODEV;
499 }
500 }
501
502 /*
503 * JMicron chips need a bit of a nudge to enable the power
504 * output pins.
505 */
506 ret = jmicron_pmos(chip, 1);
507 if (ret) {
508 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
509 return ret;
510 }
511
512 /* quirk for unsable RO-detection on JM388 chips */
513 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
514 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
515 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
516
517 return 0;
518 }
519
520 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
521 {
522 u8 scratch;
523
524 scratch = readb(host->ioaddr + 0xC0);
525
526 if (on)
527 scratch |= 0x01;
528 else
529 scratch &= ~0x01;
530
531 writeb(scratch, host->ioaddr + 0xC0);
532 }
533
534 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
535 {
536 if (slot->chip->pdev->revision == 0) {
537 u16 version;
538
539 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
540 version = (version & SDHCI_VENDOR_VER_MASK) >>
541 SDHCI_VENDOR_VER_SHIFT;
542
543 /*
544 * Older versions of the chip have lots of nasty glitches
545 * in the ADMA engine. It's best just to avoid it
546 * completely.
547 */
548 if (version < 0xAC)
549 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
550 }
551
552 /* JM388 MMC doesn't support 1.8V while SD supports it */
553 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
554 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
555 MMC_VDD_29_30 | MMC_VDD_30_31 |
556 MMC_VDD_165_195; /* allow 1.8V */
557 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
558 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
559 }
560
561 /*
562 * The secondary interface requires a bit set to get the
563 * interrupts.
564 */
565 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
566 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
567 jmicron_enable_mmc(slot->host, 1);
568
569 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
570
571 return 0;
572 }
573
574 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
575 {
576 if (dead)
577 return;
578
579 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
580 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
581 jmicron_enable_mmc(slot->host, 0);
582 }
583
584 static int jmicron_suspend(struct sdhci_pci_chip *chip)
585 {
586 int i;
587
588 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
589 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
590 for (i = 0; i < chip->num_slots; i++)
591 jmicron_enable_mmc(chip->slots[i]->host, 0);
592 }
593
594 return 0;
595 }
596
597 static int jmicron_resume(struct sdhci_pci_chip *chip)
598 {
599 int ret, i;
600
601 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
602 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
603 for (i = 0; i < chip->num_slots; i++)
604 jmicron_enable_mmc(chip->slots[i]->host, 1);
605 }
606
607 ret = jmicron_pmos(chip, 1);
608 if (ret) {
609 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
610 return ret;
611 }
612
613 return 0;
614 }
615
616 static const struct sdhci_pci_fixes sdhci_o2 = {
617 .probe = o2_probe,
618 };
619
620 static const struct sdhci_pci_fixes sdhci_jmicron = {
621 .probe = jmicron_probe,
622
623 .probe_slot = jmicron_probe_slot,
624 .remove_slot = jmicron_remove_slot,
625
626 .suspend = jmicron_suspend,
627 .resume = jmicron_resume,
628 };
629
630 /* SysKonnect CardBus2SDIO extra registers */
631 #define SYSKT_CTRL 0x200
632 #define SYSKT_RDFIFO_STAT 0x204
633 #define SYSKT_WRFIFO_STAT 0x208
634 #define SYSKT_POWER_DATA 0x20c
635 #define SYSKT_POWER_330 0xef
636 #define SYSKT_POWER_300 0xf8
637 #define SYSKT_POWER_184 0xcc
638 #define SYSKT_POWER_CMD 0x20d
639 #define SYSKT_POWER_START (1 << 7)
640 #define SYSKT_POWER_STATUS 0x20e
641 #define SYSKT_POWER_STATUS_OK (1 << 0)
642 #define SYSKT_BOARD_REV 0x210
643 #define SYSKT_CHIP_REV 0x211
644 #define SYSKT_CONF_DATA 0x212
645 #define SYSKT_CONF_DATA_1V8 (1 << 2)
646 #define SYSKT_CONF_DATA_2V5 (1 << 1)
647 #define SYSKT_CONF_DATA_3V3 (1 << 0)
648
649 static int syskt_probe(struct sdhci_pci_chip *chip)
650 {
651 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
652 chip->pdev->class &= ~0x0000FF;
653 chip->pdev->class |= PCI_SDHCI_IFDMA;
654 }
655 return 0;
656 }
657
658 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
659 {
660 int tm, ps;
661
662 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
663 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
664 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
665 "board rev %d.%d, chip rev %d.%d\n",
666 board_rev >> 4, board_rev & 0xf,
667 chip_rev >> 4, chip_rev & 0xf);
668 if (chip_rev >= 0x20)
669 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
670
671 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
672 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
673 udelay(50);
674 tm = 10; /* Wait max 1 ms */
675 do {
676 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
677 if (ps & SYSKT_POWER_STATUS_OK)
678 break;
679 udelay(100);
680 } while (--tm);
681 if (!tm) {
682 dev_err(&slot->chip->pdev->dev,
683 "power regulator never stabilized");
684 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
685 return -ENODEV;
686 }
687
688 return 0;
689 }
690
691 static const struct sdhci_pci_fixes sdhci_syskt = {
692 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
693 .probe = syskt_probe,
694 .probe_slot = syskt_probe_slot,
695 };
696
697 static int via_probe(struct sdhci_pci_chip *chip)
698 {
699 if (chip->pdev->revision == 0x10)
700 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
701
702 return 0;
703 }
704
705 static const struct sdhci_pci_fixes sdhci_via = {
706 .probe = via_probe,
707 };
708
709 static const struct pci_device_id pci_ids[] = {
710 {
711 .vendor = PCI_VENDOR_ID_RICOH,
712 .device = PCI_DEVICE_ID_RICOH_R5C822,
713 .subvendor = PCI_ANY_ID,
714 .subdevice = PCI_ANY_ID,
715 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
716 },
717
718 {
719 .vendor = PCI_VENDOR_ID_RICOH,
720 .device = 0x843,
721 .subvendor = PCI_ANY_ID,
722 .subdevice = PCI_ANY_ID,
723 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
724 },
725
726 {
727 .vendor = PCI_VENDOR_ID_RICOH,
728 .device = 0xe822,
729 .subvendor = PCI_ANY_ID,
730 .subdevice = PCI_ANY_ID,
731 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
732 },
733
734 {
735 .vendor = PCI_VENDOR_ID_RICOH,
736 .device = 0xe823,
737 .subvendor = PCI_ANY_ID,
738 .subdevice = PCI_ANY_ID,
739 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
740 },
741
742 {
743 .vendor = PCI_VENDOR_ID_ENE,
744 .device = PCI_DEVICE_ID_ENE_CB712_SD,
745 .subvendor = PCI_ANY_ID,
746 .subdevice = PCI_ANY_ID,
747 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
748 },
749
750 {
751 .vendor = PCI_VENDOR_ID_ENE,
752 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
753 .subvendor = PCI_ANY_ID,
754 .subdevice = PCI_ANY_ID,
755 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
756 },
757
758 {
759 .vendor = PCI_VENDOR_ID_ENE,
760 .device = PCI_DEVICE_ID_ENE_CB714_SD,
761 .subvendor = PCI_ANY_ID,
762 .subdevice = PCI_ANY_ID,
763 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
764 },
765
766 {
767 .vendor = PCI_VENDOR_ID_ENE,
768 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
769 .subvendor = PCI_ANY_ID,
770 .subdevice = PCI_ANY_ID,
771 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
772 },
773
774 {
775 .vendor = PCI_VENDOR_ID_MARVELL,
776 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
777 .subvendor = PCI_ANY_ID,
778 .subdevice = PCI_ANY_ID,
779 .driver_data = (kernel_ulong_t)&sdhci_cafe,
780 },
781
782 {
783 .vendor = PCI_VENDOR_ID_JMICRON,
784 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
785 .subvendor = PCI_ANY_ID,
786 .subdevice = PCI_ANY_ID,
787 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
788 },
789
790 {
791 .vendor = PCI_VENDOR_ID_JMICRON,
792 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
793 .subvendor = PCI_ANY_ID,
794 .subdevice = PCI_ANY_ID,
795 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
796 },
797
798 {
799 .vendor = PCI_VENDOR_ID_JMICRON,
800 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
801 .subvendor = PCI_ANY_ID,
802 .subdevice = PCI_ANY_ID,
803 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
804 },
805
806 {
807 .vendor = PCI_VENDOR_ID_JMICRON,
808 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
809 .subvendor = PCI_ANY_ID,
810 .subdevice = PCI_ANY_ID,
811 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
812 },
813
814 {
815 .vendor = PCI_VENDOR_ID_SYSKONNECT,
816 .device = 0x8000,
817 .subvendor = PCI_ANY_ID,
818 .subdevice = PCI_ANY_ID,
819 .driver_data = (kernel_ulong_t)&sdhci_syskt,
820 },
821
822 {
823 .vendor = PCI_VENDOR_ID_VIA,
824 .device = 0x95d0,
825 .subvendor = PCI_ANY_ID,
826 .subdevice = PCI_ANY_ID,
827 .driver_data = (kernel_ulong_t)&sdhci_via,
828 },
829
830 {
831 .vendor = PCI_VENDOR_ID_INTEL,
832 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
833 .subvendor = PCI_ANY_ID,
834 .subdevice = PCI_ANY_ID,
835 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
836 },
837
838 {
839 .vendor = PCI_VENDOR_ID_INTEL,
840 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
841 .subvendor = PCI_ANY_ID,
842 .subdevice = PCI_ANY_ID,
843 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
844 },
845
846 {
847 .vendor = PCI_VENDOR_ID_INTEL,
848 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
849 .subvendor = PCI_ANY_ID,
850 .subdevice = PCI_ANY_ID,
851 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
852 },
853
854 {
855 .vendor = PCI_VENDOR_ID_INTEL,
856 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
857 .subvendor = PCI_ANY_ID,
858 .subdevice = PCI_ANY_ID,
859 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
860 },
861
862 {
863 .vendor = PCI_VENDOR_ID_INTEL,
864 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
865 .subvendor = PCI_ANY_ID,
866 .subdevice = PCI_ANY_ID,
867 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
868 },
869
870 {
871 .vendor = PCI_VENDOR_ID_INTEL,
872 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
873 .subvendor = PCI_ANY_ID,
874 .subdevice = PCI_ANY_ID,
875 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
876 },
877
878 {
879 .vendor = PCI_VENDOR_ID_INTEL,
880 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
881 .subvendor = PCI_ANY_ID,
882 .subdevice = PCI_ANY_ID,
883 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
884 },
885
886 {
887 .vendor = PCI_VENDOR_ID_INTEL,
888 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
889 .subvendor = PCI_ANY_ID,
890 .subdevice = PCI_ANY_ID,
891 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
892 },
893
894 {
895 .vendor = PCI_VENDOR_ID_INTEL,
896 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
897 .subvendor = PCI_ANY_ID,
898 .subdevice = PCI_ANY_ID,
899 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
900 },
901
902 {
903 .vendor = PCI_VENDOR_ID_INTEL,
904 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
905 .subvendor = PCI_ANY_ID,
906 .subdevice = PCI_ANY_ID,
907 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
908 },
909
910 {
911 .vendor = PCI_VENDOR_ID_INTEL,
912 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
913 .subvendor = PCI_ANY_ID,
914 .subdevice = PCI_ANY_ID,
915 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
916 },
917
918 {
919 .vendor = PCI_VENDOR_ID_INTEL,
920 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
921 .subvendor = PCI_ANY_ID,
922 .subdevice = PCI_ANY_ID,
923 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
924 },
925
926 {
927 .vendor = PCI_VENDOR_ID_INTEL,
928 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
929 .subvendor = PCI_ANY_ID,
930 .subdevice = PCI_ANY_ID,
931 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
932 },
933
934 {
935 .vendor = PCI_VENDOR_ID_INTEL,
936 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
937 .subvendor = PCI_ANY_ID,
938 .subdevice = PCI_ANY_ID,
939 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
940 },
941
942 {
943 .vendor = PCI_VENDOR_ID_O2,
944 .device = PCI_DEVICE_ID_O2_8120,
945 .subvendor = PCI_ANY_ID,
946 .subdevice = PCI_ANY_ID,
947 .driver_data = (kernel_ulong_t)&sdhci_o2,
948 },
949
950 {
951 .vendor = PCI_VENDOR_ID_O2,
952 .device = PCI_DEVICE_ID_O2_8220,
953 .subvendor = PCI_ANY_ID,
954 .subdevice = PCI_ANY_ID,
955 .driver_data = (kernel_ulong_t)&sdhci_o2,
956 },
957
958 {
959 .vendor = PCI_VENDOR_ID_O2,
960 .device = PCI_DEVICE_ID_O2_8221,
961 .subvendor = PCI_ANY_ID,
962 .subdevice = PCI_ANY_ID,
963 .driver_data = (kernel_ulong_t)&sdhci_o2,
964 },
965
966 {
967 .vendor = PCI_VENDOR_ID_O2,
968 .device = PCI_DEVICE_ID_O2_8320,
969 .subvendor = PCI_ANY_ID,
970 .subdevice = PCI_ANY_ID,
971 .driver_data = (kernel_ulong_t)&sdhci_o2,
972 },
973
974 {
975 .vendor = PCI_VENDOR_ID_O2,
976 .device = PCI_DEVICE_ID_O2_8321,
977 .subvendor = PCI_ANY_ID,
978 .subdevice = PCI_ANY_ID,
979 .driver_data = (kernel_ulong_t)&sdhci_o2,
980 },
981
982 { /* Generic SD host controller */
983 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
984 },
985
986 { /* end: all zeroes */ },
987 };
988
989 MODULE_DEVICE_TABLE(pci, pci_ids);
990
991 /*****************************************************************************\
992 * *
993 * SDHCI core callbacks *
994 * *
995 \*****************************************************************************/
996
997 static int sdhci_pci_enable_dma(struct sdhci_host *host)
998 {
999 struct sdhci_pci_slot *slot;
1000 struct pci_dev *pdev;
1001 int ret;
1002
1003 slot = sdhci_priv(host);
1004 pdev = slot->chip->pdev;
1005
1006 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1007 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1008 (host->flags & SDHCI_USE_SDMA)) {
1009 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1010 "doesn't fully claim to support it.\n");
1011 }
1012
1013 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1014 if (ret)
1015 return ret;
1016
1017 pci_set_master(pdev);
1018
1019 return 0;
1020 }
1021
1022 static int sdhci_pci_bus_width(struct sdhci_host *host, int width)
1023 {
1024 u8 ctrl;
1025
1026 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1027
1028 switch (width) {
1029 case MMC_BUS_WIDTH_8:
1030 ctrl |= SDHCI_CTRL_8BITBUS;
1031 ctrl &= ~SDHCI_CTRL_4BITBUS;
1032 break;
1033 case MMC_BUS_WIDTH_4:
1034 ctrl |= SDHCI_CTRL_4BITBUS;
1035 ctrl &= ~SDHCI_CTRL_8BITBUS;
1036 break;
1037 default:
1038 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1039 break;
1040 }
1041
1042 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1043
1044 return 0;
1045 }
1046
1047 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1048 {
1049 struct sdhci_pci_slot *slot = sdhci_priv(host);
1050 int rst_n_gpio = slot->rst_n_gpio;
1051
1052 if (!gpio_is_valid(rst_n_gpio))
1053 return;
1054 gpio_set_value_cansleep(rst_n_gpio, 0);
1055 /* For eMMC, minimum is 1us but give it 10us for good measure */
1056 udelay(10);
1057 gpio_set_value_cansleep(rst_n_gpio, 1);
1058 /* For eMMC, minimum is 200us but give it 300us for good measure */
1059 usleep_range(300, 1000);
1060 }
1061
1062 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1063 {
1064 struct sdhci_pci_slot *slot = sdhci_priv(host);
1065
1066 if (slot->hw_reset)
1067 slot->hw_reset(host);
1068 }
1069
1070 static const struct sdhci_ops sdhci_pci_ops = {
1071 .enable_dma = sdhci_pci_enable_dma,
1072 .platform_bus_width = sdhci_pci_bus_width,
1073 .hw_reset = sdhci_pci_hw_reset,
1074 };
1075
1076 /*****************************************************************************\
1077 * *
1078 * Suspend/resume *
1079 * *
1080 \*****************************************************************************/
1081
1082 #ifdef CONFIG_PM
1083
1084 static int sdhci_pci_suspend(struct device *dev)
1085 {
1086 struct pci_dev *pdev = to_pci_dev(dev);
1087 struct sdhci_pci_chip *chip;
1088 struct sdhci_pci_slot *slot;
1089 mmc_pm_flag_t slot_pm_flags;
1090 mmc_pm_flag_t pm_flags = 0;
1091 int i, ret;
1092
1093 chip = pci_get_drvdata(pdev);
1094 if (!chip)
1095 return 0;
1096
1097 for (i = 0; i < chip->num_slots; i++) {
1098 slot = chip->slots[i];
1099 if (!slot)
1100 continue;
1101
1102 ret = sdhci_suspend_host(slot->host);
1103
1104 if (ret)
1105 goto err_pci_suspend;
1106
1107 slot_pm_flags = slot->host->mmc->pm_flags;
1108 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1109 sdhci_enable_irq_wakeups(slot->host);
1110
1111 pm_flags |= slot_pm_flags;
1112 }
1113
1114 if (chip->fixes && chip->fixes->suspend) {
1115 ret = chip->fixes->suspend(chip);
1116 if (ret)
1117 goto err_pci_suspend;
1118 }
1119
1120 pci_save_state(pdev);
1121 if (pm_flags & MMC_PM_KEEP_POWER) {
1122 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
1123 pci_pme_active(pdev, true);
1124 pci_enable_wake(pdev, PCI_D3hot, 1);
1125 }
1126 pci_set_power_state(pdev, PCI_D3hot);
1127 } else {
1128 pci_enable_wake(pdev, PCI_D3hot, 0);
1129 pci_disable_device(pdev);
1130 pci_set_power_state(pdev, PCI_D3hot);
1131 }
1132
1133 return 0;
1134
1135 err_pci_suspend:
1136 while (--i >= 0)
1137 sdhci_resume_host(chip->slots[i]->host);
1138 return ret;
1139 }
1140
1141 static int sdhci_pci_resume(struct device *dev)
1142 {
1143 struct pci_dev *pdev = to_pci_dev(dev);
1144 struct sdhci_pci_chip *chip;
1145 struct sdhci_pci_slot *slot;
1146 int i, ret;
1147
1148 chip = pci_get_drvdata(pdev);
1149 if (!chip)
1150 return 0;
1151
1152 pci_set_power_state(pdev, PCI_D0);
1153 pci_restore_state(pdev);
1154 ret = pci_enable_device(pdev);
1155 if (ret)
1156 return ret;
1157
1158 if (chip->fixes && chip->fixes->resume) {
1159 ret = chip->fixes->resume(chip);
1160 if (ret)
1161 return ret;
1162 }
1163
1164 for (i = 0; i < chip->num_slots; i++) {
1165 slot = chip->slots[i];
1166 if (!slot)
1167 continue;
1168
1169 ret = sdhci_resume_host(slot->host);
1170 if (ret)
1171 return ret;
1172 }
1173
1174 return 0;
1175 }
1176
1177 #else /* CONFIG_PM */
1178
1179 #define sdhci_pci_suspend NULL
1180 #define sdhci_pci_resume NULL
1181
1182 #endif /* CONFIG_PM */
1183
1184 #ifdef CONFIG_PM_RUNTIME
1185
1186 static int sdhci_pci_runtime_suspend(struct device *dev)
1187 {
1188 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1189 struct sdhci_pci_chip *chip;
1190 struct sdhci_pci_slot *slot;
1191 int i, ret;
1192
1193 chip = pci_get_drvdata(pdev);
1194 if (!chip)
1195 return 0;
1196
1197 for (i = 0; i < chip->num_slots; i++) {
1198 slot = chip->slots[i];
1199 if (!slot)
1200 continue;
1201
1202 ret = sdhci_runtime_suspend_host(slot->host);
1203
1204 if (ret)
1205 goto err_pci_runtime_suspend;
1206 }
1207
1208 if (chip->fixes && chip->fixes->suspend) {
1209 ret = chip->fixes->suspend(chip);
1210 if (ret)
1211 goto err_pci_runtime_suspend;
1212 }
1213
1214 return 0;
1215
1216 err_pci_runtime_suspend:
1217 while (--i >= 0)
1218 sdhci_runtime_resume_host(chip->slots[i]->host);
1219 return ret;
1220 }
1221
1222 static int sdhci_pci_runtime_resume(struct device *dev)
1223 {
1224 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1225 struct sdhci_pci_chip *chip;
1226 struct sdhci_pci_slot *slot;
1227 int i, ret;
1228
1229 chip = pci_get_drvdata(pdev);
1230 if (!chip)
1231 return 0;
1232
1233 if (chip->fixes && chip->fixes->resume) {
1234 ret = chip->fixes->resume(chip);
1235 if (ret)
1236 return ret;
1237 }
1238
1239 for (i = 0; i < chip->num_slots; i++) {
1240 slot = chip->slots[i];
1241 if (!slot)
1242 continue;
1243
1244 ret = sdhci_runtime_resume_host(slot->host);
1245 if (ret)
1246 return ret;
1247 }
1248
1249 return 0;
1250 }
1251
1252 static int sdhci_pci_runtime_idle(struct device *dev)
1253 {
1254 return 0;
1255 }
1256
1257 #else
1258
1259 #define sdhci_pci_runtime_suspend NULL
1260 #define sdhci_pci_runtime_resume NULL
1261 #define sdhci_pci_runtime_idle NULL
1262
1263 #endif
1264
1265 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1266 .suspend = sdhci_pci_suspend,
1267 .resume = sdhci_pci_resume,
1268 .runtime_suspend = sdhci_pci_runtime_suspend,
1269 .runtime_resume = sdhci_pci_runtime_resume,
1270 .runtime_idle = sdhci_pci_runtime_idle,
1271 };
1272
1273 /*****************************************************************************\
1274 * *
1275 * Device probing/removal *
1276 * *
1277 \*****************************************************************************/
1278
1279 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1280 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1281 int slotno)
1282 {
1283 struct sdhci_pci_slot *slot;
1284 struct sdhci_host *host;
1285 int ret, bar = first_bar + slotno;
1286
1287 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1288 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1289 return ERR_PTR(-ENODEV);
1290 }
1291
1292 if (pci_resource_len(pdev, bar) < 0x100) {
1293 dev_err(&pdev->dev, "Invalid iomem size. You may "
1294 "experience problems.\n");
1295 }
1296
1297 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1298 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1299 return ERR_PTR(-ENODEV);
1300 }
1301
1302 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1303 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1304 return ERR_PTR(-ENODEV);
1305 }
1306
1307 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1308 if (IS_ERR(host)) {
1309 dev_err(&pdev->dev, "cannot allocate host\n");
1310 return ERR_CAST(host);
1311 }
1312
1313 slot = sdhci_priv(host);
1314
1315 slot->chip = chip;
1316 slot->host = host;
1317 slot->pci_bar = bar;
1318 slot->rst_n_gpio = -EINVAL;
1319 slot->cd_gpio = -EINVAL;
1320
1321 /* Retrieve platform data if there is any */
1322 if (*sdhci_pci_get_data)
1323 slot->data = sdhci_pci_get_data(pdev, slotno);
1324
1325 if (slot->data) {
1326 if (slot->data->setup) {
1327 ret = slot->data->setup(slot->data);
1328 if (ret) {
1329 dev_err(&pdev->dev, "platform setup failed\n");
1330 goto free;
1331 }
1332 }
1333 slot->rst_n_gpio = slot->data->rst_n_gpio;
1334 slot->cd_gpio = slot->data->cd_gpio;
1335 }
1336
1337 host->hw_name = "PCI";
1338 host->ops = &sdhci_pci_ops;
1339 host->quirks = chip->quirks;
1340 host->quirks2 = chip->quirks2;
1341
1342 host->irq = pdev->irq;
1343
1344 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1345 if (ret) {
1346 dev_err(&pdev->dev, "cannot request region\n");
1347 goto cleanup;
1348 }
1349
1350 host->ioaddr = pci_ioremap_bar(pdev, bar);
1351 if (!host->ioaddr) {
1352 dev_err(&pdev->dev, "failed to remap registers\n");
1353 ret = -ENOMEM;
1354 goto release;
1355 }
1356
1357 if (chip->fixes && chip->fixes->probe_slot) {
1358 ret = chip->fixes->probe_slot(slot);
1359 if (ret)
1360 goto unmap;
1361 }
1362
1363 if (gpio_is_valid(slot->rst_n_gpio)) {
1364 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1365 gpio_direction_output(slot->rst_n_gpio, 1);
1366 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1367 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1368 } else {
1369 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1370 slot->rst_n_gpio = -EINVAL;
1371 }
1372 }
1373
1374 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1375 host->mmc->slotno = slotno;
1376 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1377
1378 ret = sdhci_add_host(host);
1379 if (ret)
1380 goto remove;
1381
1382 sdhci_pci_add_own_cd(slot);
1383
1384 return slot;
1385
1386 remove:
1387 if (gpio_is_valid(slot->rst_n_gpio))
1388 gpio_free(slot->rst_n_gpio);
1389
1390 if (chip->fixes && chip->fixes->remove_slot)
1391 chip->fixes->remove_slot(slot, 0);
1392
1393 unmap:
1394 iounmap(host->ioaddr);
1395
1396 release:
1397 pci_release_region(pdev, bar);
1398
1399 cleanup:
1400 if (slot->data && slot->data->cleanup)
1401 slot->data->cleanup(slot->data);
1402
1403 free:
1404 sdhci_free_host(host);
1405
1406 return ERR_PTR(ret);
1407 }
1408
1409 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1410 {
1411 int dead;
1412 u32 scratch;
1413
1414 sdhci_pci_remove_own_cd(slot);
1415
1416 dead = 0;
1417 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1418 if (scratch == (u32)-1)
1419 dead = 1;
1420
1421 sdhci_remove_host(slot->host, dead);
1422
1423 if (gpio_is_valid(slot->rst_n_gpio))
1424 gpio_free(slot->rst_n_gpio);
1425
1426 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1427 slot->chip->fixes->remove_slot(slot, dead);
1428
1429 if (slot->data && slot->data->cleanup)
1430 slot->data->cleanup(slot->data);
1431
1432 pci_release_region(slot->chip->pdev, slot->pci_bar);
1433
1434 sdhci_free_host(slot->host);
1435 }
1436
1437 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1438 {
1439 pm_runtime_put_noidle(dev);
1440 pm_runtime_allow(dev);
1441 pm_runtime_set_autosuspend_delay(dev, 50);
1442 pm_runtime_use_autosuspend(dev);
1443 pm_suspend_ignore_children(dev, 1);
1444 }
1445
1446 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1447 {
1448 pm_runtime_forbid(dev);
1449 pm_runtime_get_noresume(dev);
1450 }
1451
1452 static int sdhci_pci_probe(struct pci_dev *pdev,
1453 const struct pci_device_id *ent)
1454 {
1455 struct sdhci_pci_chip *chip;
1456 struct sdhci_pci_slot *slot;
1457
1458 u8 slots, first_bar;
1459 int ret, i;
1460
1461 BUG_ON(pdev == NULL);
1462 BUG_ON(ent == NULL);
1463
1464 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1465 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1466
1467 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1468 if (ret)
1469 return ret;
1470
1471 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1472 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1473 if (slots == 0)
1474 return -ENODEV;
1475
1476 BUG_ON(slots > MAX_SLOTS);
1477
1478 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1479 if (ret)
1480 return ret;
1481
1482 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1483
1484 if (first_bar > 5) {
1485 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1486 return -ENODEV;
1487 }
1488
1489 ret = pci_enable_device(pdev);
1490 if (ret)
1491 return ret;
1492
1493 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1494 if (!chip) {
1495 ret = -ENOMEM;
1496 goto err;
1497 }
1498
1499 chip->pdev = pdev;
1500 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1501 if (chip->fixes) {
1502 chip->quirks = chip->fixes->quirks;
1503 chip->quirks2 = chip->fixes->quirks2;
1504 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1505 }
1506 chip->num_slots = slots;
1507
1508 pci_set_drvdata(pdev, chip);
1509
1510 if (chip->fixes && chip->fixes->probe) {
1511 ret = chip->fixes->probe(chip);
1512 if (ret)
1513 goto free;
1514 }
1515
1516 slots = chip->num_slots; /* Quirk may have changed this */
1517
1518 for (i = 0; i < slots; i++) {
1519 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1520 if (IS_ERR(slot)) {
1521 for (i--; i >= 0; i--)
1522 sdhci_pci_remove_slot(chip->slots[i]);
1523 ret = PTR_ERR(slot);
1524 goto free;
1525 }
1526
1527 chip->slots[i] = slot;
1528 }
1529
1530 if (chip->allow_runtime_pm)
1531 sdhci_pci_runtime_pm_allow(&pdev->dev);
1532
1533 return 0;
1534
1535 free:
1536 pci_set_drvdata(pdev, NULL);
1537 kfree(chip);
1538
1539 err:
1540 pci_disable_device(pdev);
1541 return ret;
1542 }
1543
1544 static void sdhci_pci_remove(struct pci_dev *pdev)
1545 {
1546 int i;
1547 struct sdhci_pci_chip *chip;
1548
1549 chip = pci_get_drvdata(pdev);
1550
1551 if (chip) {
1552 if (chip->allow_runtime_pm)
1553 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1554
1555 for (i = 0; i < chip->num_slots; i++)
1556 sdhci_pci_remove_slot(chip->slots[i]);
1557
1558 pci_set_drvdata(pdev, NULL);
1559 kfree(chip);
1560 }
1561
1562 pci_disable_device(pdev);
1563 }
1564
1565 static struct pci_driver sdhci_driver = {
1566 .name = "sdhci-pci",
1567 .id_table = pci_ids,
1568 .probe = sdhci_pci_probe,
1569 .remove = sdhci_pci_remove,
1570 .driver = {
1571 .pm = &sdhci_pci_pm_ops
1572 },
1573 };
1574
1575 module_pci_driver(sdhci_driver);
1576
1577 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1578 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1579 MODULE_LICENSE("GPL");
Linux with added FPC-III support