drivers/net/ieee802154/mrf24j40.c

   1 /*
   2  * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
   3  *
   4  * Copyright (C) 2012 Alan Ott <alan@signal11.us>
   5  *                    Signal 11 Software
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/spi/spi.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <net/wpan-phy.h>
  26 #include <net/mac802154.h>
  27 #include <net/ieee802154.h>
  28
  29 /* MRF24J40 Short Address Registers */
  30 #define REG_RXMCR    0x00  /* Receive MAC control */
  31 #define REG_PANIDL   0x01  /* PAN ID (low) */
  32 #define REG_PANIDH   0x02  /* PAN ID (high) */
  33 #define REG_SADRL    0x03  /* Short address (low) */
  34 #define REG_SADRH    0x04  /* Short address (high) */
  35 #define REG_EADR0    0x05  /* Long address (low) (high is EADR7) */
  36 #define REG_TXMCR    0x11  /* Transmit MAC control */
  37 #define REG_PACON0   0x16  /* Power Amplifier Control */
  38 #define REG_PACON1   0x17  /* Power Amplifier Control */
  39 #define REG_PACON2   0x18  /* Power Amplifier Control */
  40 #define REG_TXNCON   0x1B  /* Transmit Normal FIFO Control */
  41 #define REG_TXSTAT   0x24  /* TX MAC Status Register */
  42 #define REG_SOFTRST  0x2A  /* Soft Reset */
  43 #define REG_TXSTBL   0x2E  /* TX Stabilization */
  44 #define REG_INTSTAT  0x31  /* Interrupt Status */
  45 #define REG_INTCON   0x32  /* Interrupt Control */
  46 #define REG_RFCTL    0x36  /* RF Control Mode Register */
  47 #define REG_BBREG1   0x39  /* Baseband Registers */
  48 #define REG_BBREG2   0x3A  /* */
  49 #define REG_BBREG6   0x3E  /* */
  50 #define REG_CCAEDTH  0x3F  /* Energy Detection Threshold */
  51
  52 /* MRF24J40 Long Address Registers */
  53 #define REG_RFCON0     0x200  /* RF Control Registers */
  54 #define REG_RFCON1     0x201
  55 #define REG_RFCON2     0x202
  56 #define REG_RFCON3     0x203
  57 #define REG_RFCON5     0x205
  58 #define REG_RFCON6     0x206
  59 #define REG_RFCON7     0x207
  60 #define REG_RFCON8     0x208
  61 #define REG_RSSI       0x210
  62 #define REG_SLPCON0    0x211  /* Sleep Clock Control Registers */
  63 #define REG_SLPCON1    0x220
  64 #define REG_WAKETIMEL  0x222  /* Wake-up Time Match Value Low */
  65 #define REG_WAKETIMEH  0x223  /* Wake-up Time Match Value High */
  66 #define REG_RX_FIFO    0x300  /* Receive FIFO */
  67
  68 /* Device configuration: Only channels 11-26 on page 0 are supported. */
  69 #define MRF24J40_CHAN_MIN 11
  70 #define MRF24J40_CHAN_MAX 26
  71 #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
  72                       - ((u32)1 << MRF24J40_CHAN_MIN))
  73
  74 #define TX_FIFO_SIZE 128 /* From datasheet */
  75 #define RX_FIFO_SIZE 144 /* From datasheet */
  76 #define SET_CHANNEL_DELAY_US 192 /* From datasheet */
  77
  78 /* Device Private Data */
  79 struct mrf24j40 {
  80         struct spi_device *spi;
  81         struct ieee802154_dev *dev;
  82
  83         struct mutex buffer_mutex; /* only used to protect buf */
  84         struct completion tx_complete;
  85         struct work_struct irqwork;
  86         u8 *buf; /* 3 bytes. Used for SPI single-register transfers. */
  87 };
  88
  89 /* Read/Write SPI Commands for Short and Long Address registers. */
  90 #define MRF24J40_READSHORT(reg) ((reg) << 1)
  91 #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
  92 #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
  93 #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
  94
  95 /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
  96 #define MAX_SPI_SPEED_HZ 10000000
  97
  98 #define printdev(X) (&X->spi->dev)
  99
 100 static int write_short_reg(struct mrf24j40 *devrec, u8 reg, u8 value)
 101 {
 102         int ret;
 103         struct spi_message msg;
 104         struct spi_transfer xfer = {
 105                 .len = 2,
 106                 .tx_buf = devrec->buf,
 107                 .rx_buf = devrec->buf,
 108         };
 109
 110         spi_message_init(&msg);
 111         spi_message_add_tail(&xfer, &msg);
 112
 113         mutex_lock(&devrec->buffer_mutex);
 114         devrec->buf[0] = MRF24J40_WRITESHORT(reg);
 115         devrec->buf[1] = value;
 116
 117         ret = spi_sync(devrec->spi, &msg);
 118         if (ret)
 119                 dev_err(printdev(devrec),
 120                         "SPI write Failed for short register 0x%hhx\n", reg);
 121
 122         mutex_unlock(&devrec->buffer_mutex);
 123         return ret;
 124 }
 125
 126 static int read_short_reg(struct mrf24j40 *devrec, u8 reg, u8 *val)
 127 {
 128         int ret = -1;
 129         struct spi_message msg;
 130         struct spi_transfer xfer = {
 131                 .len = 2,
 132                 .tx_buf = devrec->buf,
 133                 .rx_buf = devrec->buf,
 134         };
 135
 136         spi_message_init(&msg);
 137         spi_message_add_tail(&xfer, &msg);
 138
 139         mutex_lock(&devrec->buffer_mutex);
 140         devrec->buf[0] = MRF24J40_READSHORT(reg);
 141         devrec->buf[1] = 0;
 142
 143         ret = spi_sync(devrec->spi, &msg);
 144         if (ret)
 145                 dev_err(printdev(devrec),
 146                         "SPI read Failed for short register 0x%hhx\n", reg);
 147         else
 148                 *val = devrec->buf[1];
 149
 150         mutex_unlock(&devrec->buffer_mutex);
 151         return ret;
 152 }
 153
 154 static int read_long_reg(struct mrf24j40 *devrec, u16 reg, u8 *value)
 155 {
 156         int ret;
 157         u16 cmd;
 158         struct spi_message msg;
 159         struct spi_transfer xfer = {
 160                 .len = 3,
 161                 .tx_buf = devrec->buf,
 162                 .rx_buf = devrec->buf,
 163         };
 164
 165         spi_message_init(&msg);
 166         spi_message_add_tail(&xfer, &msg);
 167
 168         cmd = MRF24J40_READLONG(reg);
 169         mutex_lock(&devrec->buffer_mutex);
 170         devrec->buf[0] = cmd >> 8 & 0xff;
 171         devrec->buf[1] = cmd & 0xff;
 172         devrec->buf[2] = 0;
 173
 174         ret = spi_sync(devrec->spi, &msg);
 175         if (ret)
 176                 dev_err(printdev(devrec),
 177                         "SPI read Failed for long register 0x%hx\n", reg);
 178         else
 179                 *value = devrec->buf[2];
 180
 181         mutex_unlock(&devrec->buffer_mutex);
 182         return ret;
 183 }
 184
 185 static int write_long_reg(struct mrf24j40 *devrec, u16 reg, u8 val)
 186 {
 187         int ret;
 188         u16 cmd;
 189         struct spi_message msg;
 190         struct spi_transfer xfer = {
 191                 .len = 3,
 192                 .tx_buf = devrec->buf,
 193                 .rx_buf = devrec->buf,
 194         };
 195
 196         spi_message_init(&msg);
 197         spi_message_add_tail(&xfer, &msg);
 198
 199         cmd = MRF24J40_WRITELONG(reg);
 200         mutex_lock(&devrec->buffer_mutex);
 201         devrec->buf[0] = cmd >> 8 & 0xff;
 202         devrec->buf[1] = cmd & 0xff;
 203         devrec->buf[2] = val;
 204
 205         ret = spi_sync(devrec->spi, &msg);
 206         if (ret)
 207                 dev_err(printdev(devrec),
 208                         "SPI write Failed for long register 0x%hx\n", reg);
 209
 210         mutex_unlock(&devrec->buffer_mutex);
 211         return ret;
 212 }
 213
 214 /* This function relies on an undocumented write method. Once a write command
 215    and address is set, as many bytes of data as desired can be clocked into
 216    the device. The datasheet only shows setting one byte at a time. */
 217 static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
 218                         const u8 *data, size_t length)
 219 {
 220         int ret;
 221         u16 cmd;
 222         u8 lengths[2];
 223         struct spi_message msg;
 224         struct spi_transfer addr_xfer = {
 225                 .len = 2,
 226                 .tx_buf = devrec->buf,
 227         };
 228         struct spi_transfer lengths_xfer = {
 229                 .len = 2,
 230                 .tx_buf = &lengths, /* TODO: Is DMA really required for SPI? */
 231         };
 232         struct spi_transfer data_xfer = {
 233                 .len = length,
 234                 .tx_buf = data,
 235         };
 236
 237         /* Range check the length. 2 bytes are used for the length fields.*/
 238         if (length > TX_FIFO_SIZE-2) {
 239                 dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
 240                 length = TX_FIFO_SIZE-2;
 241         }
 242
 243         spi_message_init(&msg);
 244         spi_message_add_tail(&addr_xfer, &msg);
 245         spi_message_add_tail(&lengths_xfer, &msg);
 246         spi_message_add_tail(&data_xfer, &msg);
 247
 248         cmd = MRF24J40_WRITELONG(reg);
 249         mutex_lock(&devrec->buffer_mutex);
 250         devrec->buf[0] = cmd >> 8 & 0xff;
 251         devrec->buf[1] = cmd & 0xff;
 252         lengths[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
 253         lengths[1] = length; /* Total length */
 254
 255         ret = spi_sync(devrec->spi, &msg);
 256         if (ret)
 257                 dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
 258
 259         mutex_unlock(&devrec->buffer_mutex);
 260         return ret;
 261 }
 262
 263 static int mrf24j40_read_rx_buf(struct mrf24j40 *devrec,
 264                                 u8 *data, u8 *len, u8 *lqi)
 265 {
 266         u8 rx_len;
 267         u8 addr[2];
 268         u8 lqi_rssi[2];
 269         u16 cmd;
 270         int ret;
 271         struct spi_message msg;
 272         struct spi_transfer addr_xfer = {
 273                 .len = 2,
 274                 .tx_buf = &addr,
 275         };
 276         struct spi_transfer data_xfer = {
 277                 .len = 0x0, /* set below */
 278                 .rx_buf = data,
 279         };
 280         struct spi_transfer status_xfer = {
 281                 .len = 2,
 282                 .rx_buf = &lqi_rssi,
 283         };
 284
 285         /* Get the length of the data in the RX FIFO. The length in this
 286          * register exclues the 1-byte length field at the beginning. */
 287         ret = read_long_reg(devrec, REG_RX_FIFO, &rx_len);
 288         if (ret)
 289                 goto out;
 290
 291         /* Range check the RX FIFO length, accounting for the one-byte
 292          * length field at the begining. */
 293         if (rx_len > RX_FIFO_SIZE-1) {
 294                 dev_err(printdev(devrec), "Invalid length read from device. Performing short read.\n");
 295                 rx_len = RX_FIFO_SIZE-1;
 296         }
 297
 298         if (rx_len > *len) {
 299                 /* Passed in buffer wasn't big enough. Should never happen. */
 300                 dev_err(printdev(devrec), "Buffer not big enough. Performing short read\n");
 301                 rx_len = *len;
 302         }
 303
 304         /* Set up the commands to read the data. */
 305         cmd = MRF24J40_READLONG(REG_RX_FIFO+1);
 306         addr[0] = cmd >> 8 & 0xff;
 307         addr[1] = cmd & 0xff;
 308         data_xfer.len = rx_len;
 309
 310         spi_message_init(&msg);
 311         spi_message_add_tail(&addr_xfer, &msg);
 312         spi_message_add_tail(&data_xfer, &msg);
 313         spi_message_add_tail(&status_xfer, &msg);
 314
 315         ret = spi_sync(devrec->spi, &msg);
 316         if (ret) {
 317                 dev_err(printdev(devrec), "SPI RX Buffer Read Failed.\n");
 318                 goto out;
 319         }
 320
 321         *lqi = lqi_rssi[0];
 322         *len = rx_len;
 323
 324 #ifdef DEBUG
 325         print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ",
 326                 DUMP_PREFIX_OFFSET, 16, 1, data, *len, 0);
 327         printk(KERN_DEBUG "mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
 328                 lqi_rssi[0], lqi_rssi[1]);
 329 #endif
 330
 331 out:
 332         return ret;
 333 }
 334
 335 static int mrf24j40_tx(struct ieee802154_dev *dev, struct sk_buff *skb)
 336 {
 337         struct mrf24j40 *devrec = dev->priv;
 338         u8 val;
 339         int ret = 0;
 340
 341         dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
 342
 343         ret = write_tx_buf(devrec, 0x000, skb->data, skb->len);
 344         if (ret)
 345                 goto err;
 346
 347         /* Set TXNTRIG bit of TXNCON to send packet */
 348         ret = read_short_reg(devrec, REG_TXNCON, &val);
 349         if (ret)
 350                 goto err;
 351         val |= 0x1;
 352         /* Set TXNACKREQ if the ACK bit is set in the packet. */
 353         if (skb->data[0] & IEEE802154_FC_ACK_REQ)
 354                 val |= 0x4;
 355         write_short_reg(devrec, REG_TXNCON, val);
 356
 357         INIT_COMPLETION(devrec->tx_complete);
 358
 359         /* Wait for the device to send the TX complete interrupt. */
 360         ret = wait_for_completion_interruptible_timeout(
 361                                                 &devrec->tx_complete,
 362                                                 5 * HZ);
 363         if (ret == -ERESTARTSYS)
 364                 goto err;
 365         if (ret == 0) {
 366                 dev_warn(printdev(devrec), "Timeout waiting for TX interrupt\n");
 367                 ret = -ETIMEDOUT;
 368                 goto err;
 369         }
 370
 371         /* Check for send error from the device. */
 372         ret = read_short_reg(devrec, REG_TXSTAT, &val);
 373         if (ret)
 374                 goto err;
 375         if (val & 0x1) {
 376                 dev_dbg(printdev(devrec), "Error Sending. Retry count exceeded\n");
 377                 ret = -ECOMM; /* TODO: Better error code ? */
 378         } else
 379                 dev_dbg(printdev(devrec), "Packet Sent\n");
 380
 381 err:
 382
 383         return ret;
 384 }
 385
 386 static int mrf24j40_ed(struct ieee802154_dev *dev, u8 *level)
 387 {
 388         /* TODO: */
 389         printk(KERN_WARNING "mrf24j40: ed not implemented\n");
 390         *level = 0;
 391         return 0;
 392 }
 393
 394 static int mrf24j40_start(struct ieee802154_dev *dev)
 395 {
 396         struct mrf24j40 *devrec = dev->priv;
 397         u8 val;
 398         int ret;
 399
 400         dev_dbg(printdev(devrec), "start\n");
 401
 402         ret = read_short_reg(devrec, REG_INTCON, &val);
 403         if (ret)
 404                 return ret;
 405         val &= ~(0x1|0x8); /* Clear TXNIE and RXIE. Enable interrupts */
 406         write_short_reg(devrec, REG_INTCON, val);
 407
 408         return 0;
 409 }
 410
 411 static void mrf24j40_stop(struct ieee802154_dev *dev)
 412 {
 413         struct mrf24j40 *devrec = dev->priv;
 414         u8 val;
 415         int ret;
 416         dev_dbg(printdev(devrec), "stop\n");
 417
 418         ret = read_short_reg(devrec, REG_INTCON, &val);
 419         if (ret)
 420                 return;
 421         val |= 0x1|0x8; /* Set TXNIE and RXIE. Disable Interrupts */
 422         write_short_reg(devrec, REG_INTCON, val);
 423
 424         return;
 425 }
 426
 427 static int mrf24j40_set_channel(struct ieee802154_dev *dev,
 428                                 int page, int channel)
 429 {
 430         struct mrf24j40 *devrec = dev->priv;
 431         u8 val;
 432         int ret;
 433
 434         dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
 435
 436         WARN_ON(page != 0);
 437         WARN_ON(channel < MRF24J40_CHAN_MIN);
 438         WARN_ON(channel > MRF24J40_CHAN_MAX);
 439
 440         /* Set Channel TODO */
 441         val = (channel-11) << 4 | 0x03;
 442         write_long_reg(devrec, REG_RFCON0, val);
 443
 444         /* RF Reset */
 445         ret = read_short_reg(devrec, REG_RFCTL, &val);
 446         if (ret)
 447                 return ret;
 448         val |= 0x04;
 449         write_short_reg(devrec, REG_RFCTL, val);
 450         val &= ~0x04;
 451         write_short_reg(devrec, REG_RFCTL, val);
 452
 453         udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
 454
 455         return 0;
 456 }
 457
 458 static int mrf24j40_filter(struct ieee802154_dev *dev,
 459                            struct ieee802154_hw_addr_filt *filt,
 460                            unsigned long changed)
 461 {
 462         struct mrf24j40 *devrec = dev->priv;
 463
 464         dev_dbg(printdev(devrec), "filter\n");
 465
 466         if (changed & IEEE802515_AFILT_SADDR_CHANGED) {
 467                 /* Short Addr */
 468                 u8 addrh, addrl;
 469                 addrh = filt->short_addr >> 8 & 0xff;
 470                 addrl = filt->short_addr & 0xff;
 471
 472                 write_short_reg(devrec, REG_SADRH, addrh);
 473                 write_short_reg(devrec, REG_SADRL, addrl);
 474                 dev_dbg(printdev(devrec),
 475                         "Set short addr to %04hx\n", filt->short_addr);
 476         }
 477
 478         if (changed & IEEE802515_AFILT_IEEEADDR_CHANGED) {
 479                 /* Device Address */
 480                 int i;
 481                 for (i = 0; i < 8; i++)
 482                         write_short_reg(devrec, REG_EADR0+i,
 483                                         filt->ieee_addr[7-i]);
 484
 485 #ifdef DEBUG
 486                 printk(KERN_DEBUG "Set long addr to: ");
 487                 for (i = 0; i < 8; i++)
 488                         printk("%02hhx ", filt->ieee_addr[i]);
 489                 printk(KERN_DEBUG "\n");
 490 #endif
 491         }
 492
 493         if (changed & IEEE802515_AFILT_PANID_CHANGED) {
 494                 /* PAN ID */
 495                 u8 panidl, panidh;
 496                 panidh = filt->pan_id >> 8 & 0xff;
 497                 panidl = filt->pan_id & 0xff;
 498                 write_short_reg(devrec, REG_PANIDH, panidh);
 499                 write_short_reg(devrec, REG_PANIDL, panidl);
 500
 501                 dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
 502         }
 503
 504         if (changed & IEEE802515_AFILT_PANC_CHANGED) {
 505                 /* Pan Coordinator */
 506                 u8 val;
 507                 int ret;
 508
 509                 ret = read_short_reg(devrec, REG_RXMCR, &val);
 510                 if (ret)
 511                         return ret;
 512                 if (filt->pan_coord)
 513                         val |= 0x8;
 514                 else
 515                         val &= ~0x8;
 516                 write_short_reg(devrec, REG_RXMCR, val);
 517
 518                 /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
 519                  * REG_ORDER is maintained as default (no beacon/superframe).
 520                  */
 521
 522                 dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
 523                                         filt->pan_coord ? "on" : "off");
 524         }
 525
 526         return 0;
 527 }
 528
 529 static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
 530 {
 531         u8 len = RX_FIFO_SIZE;
 532         u8 lqi = 0;
 533         u8 val;
 534         int ret = 0;
 535         struct sk_buff *skb;
 536
 537         /* Turn off reception of packets off the air. This prevents the
 538          * device from overwriting the buffer while we're reading it. */
 539         ret = read_short_reg(devrec, REG_BBREG1, &val);
 540         if (ret)
 541                 goto out;
 542         val |= 4; /* SET RXDECINV */
 543         write_short_reg(devrec, REG_BBREG1, val);
 544
 545         skb = alloc_skb(len, GFP_KERNEL);
 546         if (!skb) {
 547                 ret = -ENOMEM;
 548                 goto out;
 549         }
 550
 551         ret = mrf24j40_read_rx_buf(devrec, skb_put(skb, len), &len, &lqi);
 552         if (ret < 0) {
 553                 dev_err(printdev(devrec), "Failure reading RX FIFO\n");
 554                 kfree_skb(skb);
 555                 ret = -EINVAL;
 556                 goto out;
 557         }
 558
 559         /* Cut off the checksum */
 560         skb_trim(skb, len-2);
 561
 562         /* TODO: Other drivers call ieee20154_rx_irqsafe() here (eg: cc2040,
 563          * also from a workqueue).  I think irqsafe is not necessary here.
 564          * Can someone confirm? */
 565         ieee802154_rx_irqsafe(devrec->dev, skb, lqi);
 566
 567         dev_dbg(printdev(devrec), "RX Handled\n");
 568
 569 out:
 570         /* Turn back on reception of packets off the air. */
 571         ret = read_short_reg(devrec, REG_BBREG1, &val);
 572         if (ret)
 573                 return ret;
 574         val &= ~0x4; /* Clear RXDECINV */
 575         write_short_reg(devrec, REG_BBREG1, val);
 576
 577         return ret;
 578 }
 579
 580 static struct ieee802154_ops mrf24j40_ops = {
 581         .owner = THIS_MODULE,
 582         .xmit = mrf24j40_tx,
 583         .ed = mrf24j40_ed,
 584         .start = mrf24j40_start,
 585         .stop = mrf24j40_stop,
 586         .set_channel = mrf24j40_set_channel,
 587         .set_hw_addr_filt = mrf24j40_filter,
 588 };
 589
 590 static irqreturn_t mrf24j40_isr(int irq, void *data)
 591 {
 592         struct mrf24j40 *devrec = data;
 593
 594         disable_irq_nosync(irq);
 595
 596         schedule_work(&devrec->irqwork);
 597
 598         return IRQ_HANDLED;
 599 }
 600
 601 static void mrf24j40_isrwork(struct work_struct *work)
 602 {
 603         struct mrf24j40 *devrec = container_of(work, struct mrf24j40, irqwork);
 604         u8 intstat;
 605         int ret;
 606
 607         /* Read the interrupt status */
 608         ret = read_short_reg(devrec, REG_INTSTAT, &intstat);
 609         if (ret)
 610                 goto out;
 611
 612         /* Check for TX complete */
 613         if (intstat & 0x1)
 614                 complete(&devrec->tx_complete);
 615
 616         /* Check for Rx */
 617         if (intstat & 0x8)
 618                 mrf24j40_handle_rx(devrec);
 619
 620 out:
 621         enable_irq(devrec->spi->irq);
 622 }
 623
 624 static int mrf24j40_probe(struct spi_device *spi)
 625 {
 626         int ret = -ENOMEM;
 627         u8 val;
 628         struct mrf24j40 *devrec;
 629
 630         printk(KERN_INFO "mrf24j40: probe(). IRQ: %d\n", spi->irq);
 631
 632         devrec = kzalloc(sizeof(struct mrf24j40), GFP_KERNEL);
 633         if (!devrec)
 634                 goto err_devrec;
 635         devrec->buf = kzalloc(3, GFP_KERNEL);
 636         if (!devrec->buf)
 637                 goto err_buf;
 638
 639         spi->mode = SPI_MODE_0; /* TODO: Is this appropriate for right here? */
 640         if (spi->max_speed_hz > MAX_SPI_SPEED_HZ)
 641                 spi->max_speed_hz = MAX_SPI_SPEED_HZ;
 642
 643         mutex_init(&devrec->buffer_mutex);
 644         init_completion(&devrec->tx_complete);
 645         INIT_WORK(&devrec->irqwork, mrf24j40_isrwork);
 646         devrec->spi = spi;
 647         spi_set_drvdata(spi, devrec);
 648
 649         /* Register with the 802154 subsystem */
 650
 651         devrec->dev = ieee802154_alloc_device(0, &mrf24j40_ops);
 652         if (!devrec->dev)
 653                 goto err_alloc_dev;
 654
 655         devrec->dev->priv = devrec;
 656         devrec->dev->parent = &devrec->spi->dev;
 657         devrec->dev->phy->channels_supported[0] = CHANNEL_MASK;
 658         devrec->dev->flags = IEEE802154_HW_OMIT_CKSUM|IEEE802154_HW_AACK;
 659
 660         dev_dbg(printdev(devrec), "registered mrf24j40\n");
 661         ret = ieee802154_register_device(devrec->dev);
 662         if (ret)
 663                 goto err_register_device;
 664
 665         /* Initialize the device.
 666                 From datasheet section 3.2: Initialization. */
 667         write_short_reg(devrec, REG_SOFTRST, 0x07);
 668         write_short_reg(devrec, REG_PACON2, 0x98);
 669         write_short_reg(devrec, REG_TXSTBL, 0x95);
 670         write_long_reg(devrec, REG_RFCON0, 0x03);
 671         write_long_reg(devrec, REG_RFCON1, 0x01);
 672         write_long_reg(devrec, REG_RFCON2, 0x80);
 673         write_long_reg(devrec, REG_RFCON6, 0x90);
 674         write_long_reg(devrec, REG_RFCON7, 0x80);
 675         write_long_reg(devrec, REG_RFCON8, 0x10);
 676         write_long_reg(devrec, REG_SLPCON1, 0x21);
 677         write_short_reg(devrec, REG_BBREG2, 0x80);
 678         write_short_reg(devrec, REG_CCAEDTH, 0x60);
 679         write_short_reg(devrec, REG_BBREG6, 0x40);
 680         write_short_reg(devrec, REG_RFCTL, 0x04);
 681         write_short_reg(devrec, REG_RFCTL, 0x0);
 682         udelay(192);
 683
 684         /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
 685         ret = read_short_reg(devrec, REG_RXMCR, &val);
 686         if (ret)
 687                 goto err_read_reg;
 688         val &= ~0x3; /* Clear RX mode (normal) */
 689         write_short_reg(devrec, REG_RXMCR, val);
 690
 691         ret = request_irq(spi->irq,
 692                           mrf24j40_isr,
 693                           IRQF_TRIGGER_FALLING,
 694                           dev_name(&spi->dev),
 695                           devrec);
 696
 697         if (ret) {
 698                 dev_err(printdev(devrec), "Unable to get IRQ");
 699                 goto err_irq;
 700         }
 701
 702         return 0;
 703
 704 err_irq:
 705 err_read_reg:
 706         ieee802154_unregister_device(devrec->dev);
 707 err_register_device:
 708         ieee802154_free_device(devrec->dev);
 709 err_alloc_dev:
 710         kfree(devrec->buf);
 711 err_buf:
 712         kfree(devrec);
 713 err_devrec:
 714         return ret;
 715 }
 716
 717 static int mrf24j40_remove(struct spi_device *spi)
 718 {
 719         struct mrf24j40 *devrec = spi_get_drvdata(spi);
 720
 721         dev_dbg(printdev(devrec), "remove\n");
 722
 723         free_irq(spi->irq, devrec);
 724         flush_work(&devrec->irqwork); /* TODO: Is this the right call? */
 725         ieee802154_unregister_device(devrec->dev);
 726         ieee802154_free_device(devrec->dev);
 727         /* TODO: Will ieee802154_free_device() wait until ->xmit() is
 728          * complete? */
 729
 730         /* Clean up the SPI stuff. */
 731         spi_set_drvdata(spi, NULL);
 732         kfree(devrec->buf);
 733         kfree(devrec);
 734         return 0;
 735 }
 736
 737 static const struct spi_device_id mrf24j40_ids[] = {
 738         { "mrf24j40", 0 },
 739         { "mrf24j40ma", 0 },
 740         { },
 741 };
 742 MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
 743
 744 static struct spi_driver mrf24j40_driver = {
 745         .driver = {
 746                 .name = "mrf24j40",
 747                 .bus = &spi_bus_type,
 748                 .owner = THIS_MODULE,
 749         },
 750         .id_table = mrf24j40_ids,
 751         .probe = mrf24j40_probe,
 752         .remove = mrf24j40_remove,
 753 };
 754
 755 module_spi_driver(mrf24j40_driver);
 756
 757 MODULE_LICENSE("GPL");
 758 MODULE_AUTHOR("Alan Ott");
 759 MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");