drivers/net/phy/micrel.c

   1 /*
   2  * drivers/net/phy/micrel.c
   3  *
   4  * Driver for Micrel PHYs
   5  *
   6  * Author: David J. Choi
   7  *
   8  * Copyright (c) 2010-2013 Micrel, Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  * Support : Micrel Phys:
  16  *              Giga phys: ksz9021, ksz9031
  17  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  18  *                         ksz8021, ksz8031, ksz8051,
  19  *                         ksz8081, ksz8091,
  20  *                         ksz8061,
  21  *              Switch : ksz8873, ksz886x
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/phy.h>
  27 #include <linux/micrel_phy.h>
  28 #include <linux/of.h>
  29
  30 /* Operation Mode Strap Override */
  31 #define MII_KSZPHY_OMSO                         0x16
  32 #define KSZPHY_OMSO_B_CAST_OFF                  (1 << 9)
  33 #define KSZPHY_OMSO_RMII_OVERRIDE               (1 << 1)
  34 #define KSZPHY_OMSO_MII_OVERRIDE                (1 << 0)
  35
  36 /* general Interrupt control/status reg in vendor specific block. */
  37 #define MII_KSZPHY_INTCS                        0x1B
  38 #define KSZPHY_INTCS_JABBER                     (1 << 15)
  39 #define KSZPHY_INTCS_RECEIVE_ERR                (1 << 14)
  40 #define KSZPHY_INTCS_PAGE_RECEIVE               (1 << 13)
  41 #define KSZPHY_INTCS_PARELLEL                   (1 << 12)
  42 #define KSZPHY_INTCS_LINK_PARTNER_ACK           (1 << 11)
  43 #define KSZPHY_INTCS_LINK_DOWN                  (1 << 10)
  44 #define KSZPHY_INTCS_REMOTE_FAULT               (1 << 9)
  45 #define KSZPHY_INTCS_LINK_UP                    (1 << 8)
  46 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  47                                                 KSZPHY_INTCS_LINK_DOWN)
  48
  49 /* general PHY control reg in vendor specific block. */
  50 #define MII_KSZPHY_CTRL                 0x1F
  51 /* bitmap of PHY register to set interrupt mode */
  52 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             (1 << 9)
  53 #define KSZ9021_CTRL_INT_ACTIVE_HIGH            (1 << 14)
  54 #define KS8737_CTRL_INT_ACTIVE_HIGH             (1 << 14)
  55 #define KSZ8051_RMII_50MHZ_CLK                  (1 << 7)
  56
  57 /* Write/read to/from extended registers */
  58 #define MII_KSZPHY_EXTREG                       0x0b
  59 #define KSZPHY_EXTREG_WRITE                     0x8000
  60
  61 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
  62 #define MII_KSZPHY_EXTREG_READ                  0x0d
  63
  64 /* Extended registers */
  65 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
  66 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
  67 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
  68
  69 #define PS_TO_REG                               200
  70
  71 static int ksz_config_flags(struct phy_device *phydev)
  72 {
  73         int regval;
  74
  75         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
  76                 regval = phy_read(phydev, MII_KSZPHY_CTRL);
  77                 regval |= KSZ8051_RMII_50MHZ_CLK;
  78                 return phy_write(phydev, MII_KSZPHY_CTRL, regval);
  79         }
  80         return 0;
  81 }
  82
  83 static int kszphy_extended_write(struct phy_device *phydev,
  84                                  u32 regnum, u16 val)
  85 {
  86         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
  87         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
  88 }
  89
  90 static int kszphy_extended_read(struct phy_device *phydev,
  91                                  u32 regnum)
  92 {
  93         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
  94         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
  95 }
  96
  97 static int kszphy_ack_interrupt(struct phy_device *phydev)
  98 {
  99         /* bit[7..0] int status, which is a read and clear register. */
 100         int rc;
 101
 102         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 103
 104         return (rc < 0) ? rc : 0;
 105 }
 106
 107 static int kszphy_set_interrupt(struct phy_device *phydev)
 108 {
 109         int temp;
 110         temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
 111                 KSZPHY_INTCS_ALL : 0;
 112         return phy_write(phydev, MII_KSZPHY_INTCS, temp);
 113 }
 114
 115 static int kszphy_config_intr(struct phy_device *phydev)
 116 {
 117         int temp, rc;
 118
 119         /* set the interrupt pin active low */
 120         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 121         temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
 122         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 123         rc = kszphy_set_interrupt(phydev);
 124         return rc < 0 ? rc : 0;
 125 }
 126
 127 static int ksz9021_config_intr(struct phy_device *phydev)
 128 {
 129         int temp, rc;
 130
 131         /* set the interrupt pin active low */
 132         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 133         temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
 134         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 135         rc = kszphy_set_interrupt(phydev);
 136         return rc < 0 ? rc : 0;
 137 }
 138
 139 static int ks8737_config_intr(struct phy_device *phydev)
 140 {
 141         int temp, rc;
 142
 143         /* set the interrupt pin active low */
 144         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 145         temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
 146         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 147         rc = kszphy_set_interrupt(phydev);
 148         return rc < 0 ? rc : 0;
 149 }
 150
 151 static int kszphy_config_init(struct phy_device *phydev)
 152 {
 153         return 0;
 154 }
 155
 156 static int ksz8021_config_init(struct phy_device *phydev)
 157 {
 158         int rc;
 159         const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
 160         phy_write(phydev, MII_KSZPHY_OMSO, val);
 161         rc = ksz_config_flags(phydev);
 162         return rc < 0 ? rc : 0;
 163 }
 164
 165 static int ks8051_config_init(struct phy_device *phydev)
 166 {
 167         int rc;
 168
 169         rc = ksz_config_flags(phydev);
 170         return rc < 0 ? rc : 0;
 171 }
 172
 173 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 174                                        struct device_node *of_node, u16 reg,
 175                                        char *field1, char *field2,
 176                                        char *field3, char *field4)
 177 {
 178         int val1 = -1;
 179         int val2 = -2;
 180         int val3 = -3;
 181         int val4 = -4;
 182         int newval;
 183         int matches = 0;
 184
 185         if (!of_property_read_u32(of_node, field1, &val1))
 186                 matches++;
 187
 188         if (!of_property_read_u32(of_node, field2, &val2))
 189                 matches++;
 190
 191         if (!of_property_read_u32(of_node, field3, &val3))
 192                 matches++;
 193
 194         if (!of_property_read_u32(of_node, field4, &val4))
 195                 matches++;
 196
 197         if (!matches)
 198                 return 0;
 199
 200         if (matches < 4)
 201                 newval = kszphy_extended_read(phydev, reg);
 202         else
 203                 newval = 0;
 204
 205         if (val1 != -1)
 206                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 207
 208         if (val2 != -1)
 209                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 210
 211         if (val3 != -1)
 212                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 213
 214         if (val4 != -1)
 215                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 216
 217         return kszphy_extended_write(phydev, reg, newval);
 218 }
 219
 220 static int ksz9021_config_init(struct phy_device *phydev)
 221 {
 222         struct device *dev = &phydev->dev;
 223         struct device_node *of_node = dev->of_node;
 224
 225         if (!of_node && dev->parent->of_node)
 226                 of_node = dev->parent->of_node;
 227
 228         if (of_node) {
 229                 ksz9021_load_values_from_of(phydev, of_node,
 230                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 231                                     "txen-skew-ps", "txc-skew-ps",
 232                                     "rxdv-skew-ps", "rxc-skew-ps");
 233                 ksz9021_load_values_from_of(phydev, of_node,
 234                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 235                                     "rxd0-skew-ps", "rxd1-skew-ps",
 236                                     "rxd2-skew-ps", "rxd3-skew-ps");
 237                 ksz9021_load_values_from_of(phydev, of_node,
 238                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 239                                     "txd0-skew-ps", "txd1-skew-ps",
 240                                     "txd2-skew-ps", "txd3-skew-ps");
 241         }
 242         return 0;
 243 }
 244
 245 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
 246 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      (1 << 6)
 247 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       (1 << 4)
 248 static int ksz8873mll_read_status(struct phy_device *phydev)
 249 {
 250         int regval;
 251
 252         /* dummy read */
 253         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 254
 255         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 256
 257         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
 258                 phydev->duplex = DUPLEX_HALF;
 259         else
 260                 phydev->duplex = DUPLEX_FULL;
 261
 262         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
 263                 phydev->speed = SPEED_10;
 264         else
 265                 phydev->speed = SPEED_100;
 266
 267         phydev->link = 1;
 268         phydev->pause = phydev->asym_pause = 0;
 269
 270         return 0;
 271 }
 272
 273 static int ksz8873mll_config_aneg(struct phy_device *phydev)
 274 {
 275         return 0;
 276 }
 277
 278 static struct phy_driver ksphy_driver[] = {
 279 {
 280         .phy_id         = PHY_ID_KS8737,
 281         .phy_id_mask    = 0x00fffff0,
 282         .name           = "Micrel KS8737",
 283         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 284         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 285         .config_init    = kszphy_config_init,
 286         .config_aneg    = genphy_config_aneg,
 287         .read_status    = genphy_read_status,
 288         .ack_interrupt  = kszphy_ack_interrupt,
 289         .config_intr    = ks8737_config_intr,
 290         .driver         = { .owner = THIS_MODULE,},
 291 }, {
 292         .phy_id         = PHY_ID_KSZ8021,
 293         .phy_id_mask    = 0x00ffffff,
 294         .name           = "Micrel KSZ8021 or KSZ8031",
 295         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
 296                            SUPPORTED_Asym_Pause),
 297         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 298         .config_init    = ksz8021_config_init,
 299         .config_aneg    = genphy_config_aneg,
 300         .read_status    = genphy_read_status,
 301         .ack_interrupt  = kszphy_ack_interrupt,
 302         .config_intr    = kszphy_config_intr,
 303         .driver         = { .owner = THIS_MODULE,},
 304 }, {
 305         .phy_id         = PHY_ID_KSZ8031,
 306         .phy_id_mask    = 0x00ffffff,
 307         .name           = "Micrel KSZ8031",
 308         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
 309                            SUPPORTED_Asym_Pause),
 310         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 311         .config_init    = ksz8021_config_init,
 312         .config_aneg    = genphy_config_aneg,
 313         .read_status    = genphy_read_status,
 314         .ack_interrupt  = kszphy_ack_interrupt,
 315         .config_intr    = kszphy_config_intr,
 316         .driver         = { .owner = THIS_MODULE,},
 317 }, {
 318         .phy_id         = PHY_ID_KSZ8041,
 319         .phy_id_mask    = 0x00fffff0,
 320         .name           = "Micrel KSZ8041",
 321         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause
 322                                 | SUPPORTED_Asym_Pause),
 323         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 324         .config_init    = kszphy_config_init,
 325         .config_aneg    = genphy_config_aneg,
 326         .read_status    = genphy_read_status,
 327         .ack_interrupt  = kszphy_ack_interrupt,
 328         .config_intr    = kszphy_config_intr,
 329         .driver         = { .owner = THIS_MODULE,},
 330 }, {
 331         .phy_id         = PHY_ID_KSZ8051,
 332         .phy_id_mask    = 0x00fffff0,
 333         .name           = "Micrel KSZ8051",
 334         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause
 335                                 | SUPPORTED_Asym_Pause),
 336         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 337         .config_init    = ks8051_config_init,
 338         .config_aneg    = genphy_config_aneg,
 339         .read_status    = genphy_read_status,
 340         .ack_interrupt  = kszphy_ack_interrupt,
 341         .config_intr    = kszphy_config_intr,
 342         .driver         = { .owner = THIS_MODULE,},
 343 }, {
 344         .phy_id         = PHY_ID_KSZ8001,
 345         .name           = "Micrel KSZ8001 or KS8721",
 346         .phy_id_mask    = 0x00ffffff,
 347         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 348         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 349         .config_init    = kszphy_config_init,
 350         .config_aneg    = genphy_config_aneg,
 351         .read_status    = genphy_read_status,
 352         .ack_interrupt  = kszphy_ack_interrupt,
 353         .config_intr    = kszphy_config_intr,
 354         .driver         = { .owner = THIS_MODULE,},
 355 }, {
 356         .phy_id         = PHY_ID_KSZ8081,
 357         .name           = "Micrel KSZ8081 or KSZ8091",
 358         .phy_id_mask    = 0x00fffff0,
 359         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 360         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 361         .config_init    = kszphy_config_init,
 362         .config_aneg    = genphy_config_aneg,
 363         .read_status    = genphy_read_status,
 364         .ack_interrupt  = kszphy_ack_interrupt,
 365         .config_intr    = kszphy_config_intr,
 366         .driver         = { .owner = THIS_MODULE,},
 367 }, {
 368         .phy_id         = PHY_ID_KSZ8061,
 369         .name           = "Micrel KSZ8061",
 370         .phy_id_mask    = 0x00fffff0,
 371         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 372         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 373         .config_init    = kszphy_config_init,
 374         .config_aneg    = genphy_config_aneg,
 375         .read_status    = genphy_read_status,
 376         .ack_interrupt  = kszphy_ack_interrupt,
 377         .config_intr    = kszphy_config_intr,
 378         .driver         = { .owner = THIS_MODULE,},
 379 }, {
 380         .phy_id         = PHY_ID_KSZ9021,
 381         .phy_id_mask    = 0x000ffffe,
 382         .name           = "Micrel KSZ9021 Gigabit PHY",
 383         .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 384         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 385         .config_init    = ksz9021_config_init,
 386         .config_aneg    = genphy_config_aneg,
 387         .read_status    = genphy_read_status,
 388         .ack_interrupt  = kszphy_ack_interrupt,
 389         .config_intr    = ksz9021_config_intr,
 390         .driver         = { .owner = THIS_MODULE, },
 391 }, {
 392         .phy_id         = PHY_ID_KSZ9031,
 393         .phy_id_mask    = 0x00fffff0,
 394         .name           = "Micrel KSZ9031 Gigabit PHY",
 395         .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause
 396                                 | SUPPORTED_Asym_Pause),
 397         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 398         .config_init    = kszphy_config_init,
 399         .config_aneg    = genphy_config_aneg,
 400         .read_status    = genphy_read_status,
 401         .ack_interrupt  = kszphy_ack_interrupt,
 402         .config_intr    = ksz9021_config_intr,
 403         .driver         = { .owner = THIS_MODULE, },
 404 }, {
 405         .phy_id         = PHY_ID_KSZ8873MLL,
 406         .phy_id_mask    = 0x00fffff0,
 407         .name           = "Micrel KSZ8873MLL Switch",
 408         .features       = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
 409         .flags          = PHY_HAS_MAGICANEG,
 410         .config_init    = kszphy_config_init,
 411         .config_aneg    = ksz8873mll_config_aneg,
 412         .read_status    = ksz8873mll_read_status,
 413         .driver         = { .owner = THIS_MODULE, },
 414 }, {
 415         .phy_id         = PHY_ID_KSZ886X,
 416         .phy_id_mask    = 0x00fffff0,
 417         .name           = "Micrel KSZ886X Switch",
 418         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 419         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 420         .config_init    = kszphy_config_init,
 421         .config_aneg    = genphy_config_aneg,
 422         .read_status    = genphy_read_status,
 423         .driver         = { .owner = THIS_MODULE, },
 424 } };
 425
 426 static int __init ksphy_init(void)
 427 {
 428         return phy_drivers_register(ksphy_driver,
 429                 ARRAY_SIZE(ksphy_driver));
 430 }
 431
 432 static void __exit ksphy_exit(void)
 433 {
 434         phy_drivers_unregister(ksphy_driver,
 435                 ARRAY_SIZE(ksphy_driver));
 436 }
 437
 438 module_init(ksphy_init);
 439 module_exit(ksphy_exit);
 440
 441 MODULE_DESCRIPTION("Micrel PHY driver");
 442 MODULE_AUTHOR("David J. Choi");
 443 MODULE_LICENSE("GPL");
 444
 445 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
 446         { PHY_ID_KSZ9021, 0x000ffffe },
 447         { PHY_ID_KSZ9031, 0x00fffff0 },
 448         { PHY_ID_KSZ8001, 0x00ffffff },
 449         { PHY_ID_KS8737, 0x00fffff0 },
 450         { PHY_ID_KSZ8021, 0x00ffffff },
 451         { PHY_ID_KSZ8031, 0x00ffffff },
 452         { PHY_ID_KSZ8041, 0x00fffff0 },
 453         { PHY_ID_KSZ8051, 0x00fffff0 },
 454         { PHY_ID_KSZ8061, 0x00fffff0 },
 455         { PHY_ID_KSZ8081, 0x00fffff0 },
 456         { PHY_ID_KSZ8873MLL, 0x00fffff0 },
 457         { PHY_ID_KSZ886X, 0x00fffff0 },
 458         { }
 459 };
 460
 461 MODULE_DEVICE_TABLE(mdio, micrel_tbl);