ARM: mm: Recreate kernel mappings in early_paging_init()
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath6kl / hif.h
blob61f6b21fb0aeeaa4e6ef20dfca3baddf6ad638cd
1 /*
2 * Copyright (c) 2004-2011 Atheros Communications Inc.
3 * Copyright (c) 2011 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #ifndef HIF_H
19 #define HIF_H
21 #include "common.h"
22 #include "core.h"
24 #include <linux/scatterlist.h>
26 #define BUS_REQUEST_MAX_NUM 64
27 #define HIF_MBOX_BLOCK_SIZE 128
28 #define HIF_MBOX0_BLOCK_SIZE 1
30 #define HIF_DMA_BUFFER_SIZE (32 * 1024)
31 #define CMD53_FIXED_ADDRESS 1
32 #define CMD53_INCR_ADDRESS 2
34 #define MAX_SCATTER_REQUESTS 4
35 #define MAX_SCATTER_ENTRIES_PER_REQ 16
36 #define MAX_SCATTER_REQ_TRANSFER_SIZE (32 * 1024)
38 #define MANUFACTURER_ID_AR6003_BASE 0x300
39 #define MANUFACTURER_ID_AR6004_BASE 0x400
40 /* SDIO manufacturer ID and Codes */
41 #define MANUFACTURER_ID_ATH6KL_BASE_MASK 0xFF00
42 #define MANUFACTURER_CODE 0x271 /* Atheros */
44 /* Mailbox address in SDIO address space */
45 #define HIF_MBOX_BASE_ADDR 0x800
46 #define HIF_MBOX_WIDTH 0x800
48 #define HIF_MBOX_END_ADDR (HTC_MAILBOX_NUM_MAX * HIF_MBOX_WIDTH - 1)
50 /* version 1 of the chip has only a 12K extended mbox range */
51 #define HIF_MBOX0_EXT_BASE_ADDR 0x4000
52 #define HIF_MBOX0_EXT_WIDTH (12*1024)
54 /* GMBOX addresses */
55 #define HIF_GMBOX_BASE_ADDR 0x7000
56 #define HIF_GMBOX_WIDTH 0x4000
58 /* interrupt mode register */
59 #define CCCR_SDIO_IRQ_MODE_REG 0xF0
61 /* mode to enable special 4-bit interrupt assertion without clock */
62 #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ (1 << 0)
64 /* HTC runs over mailbox 0 */
65 #define HTC_MAILBOX 0
67 #define ATH6KL_TARGET_DEBUG_INTR_MASK 0x01
69 /* FIXME: are these duplicates with MAX_SCATTER_ values in hif.h? */
70 #define ATH6KL_SCATTER_ENTRIES_PER_REQ 16
71 #define ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER (16 * 1024)
72 #define ATH6KL_SCATTER_REQS 4
74 #define ATH6KL_HIF_COMMUNICATION_TIMEOUT 1000
76 struct bus_request {
77 struct list_head list;
79 /* request data */
80 u32 address;
82 u8 *buffer;
83 u32 length;
84 u32 request;
85 struct htc_packet *packet;
86 int status;
88 /* this is a scatter request */
89 struct hif_scatter_req *scat_req;
92 /* direction of transfer (read/write) */
93 #define HIF_READ 0x00000001
94 #define HIF_WRITE 0x00000002
95 #define HIF_DIR_MASK (HIF_READ | HIF_WRITE)
98 * emode - This indicates the whether the command is to be executed in a
99 * blocking or non-blocking fashion (HIF_SYNCHRONOUS/
100 * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
101 * implemented using the asynchronous mode allowing the the bus
102 * driver to indicate the completion of operation through the
103 * registered callback routine. The requirement primarily comes
104 * from the contexts these operations get called from (a driver's
105 * transmit context or the ISR context in case of receive).
106 * Support for both of these modes is essential.
108 #define HIF_SYNCHRONOUS 0x00000010
109 #define HIF_ASYNCHRONOUS 0x00000020
110 #define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)
113 * dmode - An interface may support different kinds of commands based on
114 * the tradeoff between the amount of data it can carry and the
115 * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
116 * HIF_BLOCK_BASIS). In case of latter, the data is rounded off
117 * to the nearest block size by padding. The size of the block is
118 * configurable at compile time using the HIF_BLOCK_SIZE and is
119 * negotiated with the target during initialization after the
120 * ATH6KL interrupts are enabled.
122 #define HIF_BYTE_BASIS 0x00000040
123 #define HIF_BLOCK_BASIS 0x00000080
124 #define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)
127 * amode - This indicates if the address has to be incremented on ATH6KL
128 * after every read/write operation (HIF?FIXED_ADDRESS/
129 * HIF_INCREMENTAL_ADDRESS).
131 #define HIF_FIXED_ADDRESS 0x00000100
132 #define HIF_INCREMENTAL_ADDRESS 0x00000200
133 #define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)
135 #define HIF_WR_ASYNC_BYTE_INC \
136 (HIF_WRITE | HIF_ASYNCHRONOUS | \
137 HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
139 #define HIF_WR_ASYNC_BLOCK_INC \
140 (HIF_WRITE | HIF_ASYNCHRONOUS | \
141 HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
143 #define HIF_WR_SYNC_BYTE_FIX \
144 (HIF_WRITE | HIF_SYNCHRONOUS | \
145 HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
147 #define HIF_WR_SYNC_BYTE_INC \
148 (HIF_WRITE | HIF_SYNCHRONOUS | \
149 HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
151 #define HIF_WR_SYNC_BLOCK_INC \
152 (HIF_WRITE | HIF_SYNCHRONOUS | \
153 HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
155 #define HIF_RD_SYNC_BYTE_INC \
156 (HIF_READ | HIF_SYNCHRONOUS | \
157 HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
159 #define HIF_RD_SYNC_BYTE_FIX \
160 (HIF_READ | HIF_SYNCHRONOUS | \
161 HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
163 #define HIF_RD_ASYNC_BLOCK_FIX \
164 (HIF_READ | HIF_ASYNCHRONOUS | \
165 HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
167 #define HIF_RD_SYNC_BLOCK_FIX \
168 (HIF_READ | HIF_SYNCHRONOUS | \
169 HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
171 struct hif_scatter_item {
172 u8 *buf;
173 int len;
174 struct htc_packet *packet;
177 struct hif_scatter_req {
178 struct list_head list;
179 /* address for the read/write operation */
180 u32 addr;
182 /* request flags */
183 u32 req;
185 /* total length of entire transfer */
186 u32 len;
188 bool virt_scat;
190 void (*complete) (struct htc_target *, struct hif_scatter_req *);
191 int status;
192 int scat_entries;
194 struct bus_request *busrequest;
195 struct scatterlist *sgentries;
197 /* bounce buffer for upper layers to copy to/from */
198 u8 *virt_dma_buf;
200 struct hif_scatter_item scat_list[1];
202 u32 scat_q_depth;
205 struct ath6kl_irq_proc_registers {
206 u8 host_int_status;
207 u8 cpu_int_status;
208 u8 error_int_status;
209 u8 counter_int_status;
210 u8 mbox_frame;
211 u8 rx_lkahd_valid;
212 u8 host_int_status2;
213 u8 gmbox_rx_avail;
214 __le32 rx_lkahd[2];
215 __le32 rx_gmbox_lkahd_alias[2];
216 } __packed;
218 struct ath6kl_irq_enable_reg {
219 u8 int_status_en;
220 u8 cpu_int_status_en;
221 u8 err_int_status_en;
222 u8 cntr_int_status_en;
223 } __packed;
225 struct ath6kl_device {
226 /* protects irq_proc_reg and irq_en_reg below */
227 spinlock_t lock;
228 struct ath6kl_irq_proc_registers irq_proc_reg;
229 struct ath6kl_irq_enable_reg irq_en_reg;
230 struct htc_target *htc_cnxt;
231 struct ath6kl *ar;
234 struct ath6kl_hif_ops {
235 int (*read_write_sync)(struct ath6kl *ar, u32 addr, u8 *buf,
236 u32 len, u32 request);
237 int (*write_async)(struct ath6kl *ar, u32 address, u8 *buffer,
238 u32 length, u32 request, struct htc_packet *packet);
240 void (*irq_enable)(struct ath6kl *ar);
241 void (*irq_disable)(struct ath6kl *ar);
243 struct hif_scatter_req *(*scatter_req_get)(struct ath6kl *ar);
244 void (*scatter_req_add)(struct ath6kl *ar,
245 struct hif_scatter_req *s_req);
246 int (*enable_scatter)(struct ath6kl *ar);
247 int (*scat_req_rw) (struct ath6kl *ar,
248 struct hif_scatter_req *scat_req);
249 void (*cleanup_scatter)(struct ath6kl *ar);
250 int (*suspend)(struct ath6kl *ar, struct cfg80211_wowlan *wow);
251 int (*resume)(struct ath6kl *ar);
252 int (*diag_read32)(struct ath6kl *ar, u32 address, u32 *value);
253 int (*diag_write32)(struct ath6kl *ar, u32 address, __le32 value);
254 int (*bmi_read)(struct ath6kl *ar, u8 *buf, u32 len);
255 int (*bmi_write)(struct ath6kl *ar, u8 *buf, u32 len);
256 int (*power_on)(struct ath6kl *ar);
257 int (*power_off)(struct ath6kl *ar);
258 void (*stop)(struct ath6kl *ar);
259 int (*pipe_send)(struct ath6kl *ar, u8 pipe, struct sk_buff *hdr_buf,
260 struct sk_buff *buf);
261 void (*pipe_get_default)(struct ath6kl *ar, u8 *pipe_ul, u8 *pipe_dl);
262 int (*pipe_map_service)(struct ath6kl *ar, u16 service_id, u8 *pipe_ul,
263 u8 *pipe_dl);
264 u16 (*pipe_get_free_queue_number)(struct ath6kl *ar, u8 pipe);
267 int ath6kl_hif_setup(struct ath6kl_device *dev);
268 int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev);
269 int ath6kl_hif_mask_intrs(struct ath6kl_device *dev);
270 int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev,
271 u32 *lk_ahd, int timeout);
272 int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx);
273 int ath6kl_hif_disable_intrs(struct ath6kl_device *dev);
275 int ath6kl_hif_rw_comp_handler(void *context, int status);
276 int ath6kl_hif_intr_bh_handler(struct ath6kl *ar);
278 /* Scatter Function and Definitions */
279 int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev,
280 struct hif_scatter_req *scat_req, bool read);
282 #endif