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ARM: mm: Recreate kernel mappings in early_paging_init()
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / ar5008_phy.c
blob08656473c63e5a796b37bcd25f087504d85433fb
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "hw-ops.h"
19 #include "../regd.h"
20 #include "ar9002_phy.h"
21 #include "ar5008_initvals.h"
22
23 /* All code below is for AR5008, AR9001, AR9002 */
24
25 static const int firstep_table[] =
26 /* level: 0 1 2 3 4 5 6 7 8 */
27 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
28
29 static const int cycpwrThr1_table[] =
30 /* level: 0 1 2 3 4 5 6 7 8 */
31 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
32
33 /*
34 * register values to turn OFDM weak signal detection OFF
35 */
36 static const int m1ThreshLow_off = 127;
37 static const int m2ThreshLow_off = 127;
38 static const int m1Thresh_off = 127;
39 static const int m2Thresh_off = 127;
40 static const int m2CountThr_off = 31;
41 static const int m2CountThrLow_off = 63;
42 static const int m1ThreshLowExt_off = 127;
43 static const int m2ThreshLowExt_off = 127;
44 static const int m1ThreshExt_off = 127;
45 static const int m2ThreshExt_off = 127;
46
47 static const struct ar5416IniArray bank0 = STATIC_INI_ARRAY(ar5416Bank0);
48 static const struct ar5416IniArray bank1 = STATIC_INI_ARRAY(ar5416Bank1);
49 static const struct ar5416IniArray bank2 = STATIC_INI_ARRAY(ar5416Bank2);
50 static const struct ar5416IniArray bank3 = STATIC_INI_ARRAY(ar5416Bank3);
51 static const struct ar5416IniArray bank7 = STATIC_INI_ARRAY(ar5416Bank7);
52
53 static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt)
54 {
55 struct ar5416IniArray *array = &ah->iniBank6;
56 u32 *data = ah->analogBank6Data;
57 int r;
58
59 ENABLE_REGWRITE_BUFFER(ah);
60
61 for (r = 0; r < array->ia_rows; r++) {
62 REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
63 DO_DELAY(*writecnt);
64 }
65
66 REGWRITE_BUFFER_FLUSH(ah);
67 }
68
69 /**
70 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
71 * @rfbuf:
72 * @reg32:
73 * @numBits:
74 * @firstBit:
75 * @column:
76 *
77 * Performs analog "swizzling" of parameters into their location.
78 * Used on external AR2133/AR5133 radios.
79 */
80 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
81 u32 numBits, u32 firstBit,
82 u32 column)
83 {
84 u32 tmp32, mask, arrayEntry, lastBit;
85 int32_t bitPosition, bitsLeft;
86
87 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
88 arrayEntry = (firstBit - 1) / 8;
89 bitPosition = (firstBit - 1) % 8;
90 bitsLeft = numBits;
91 while (bitsLeft > 0) {
92 lastBit = (bitPosition + bitsLeft > 8) ?
93 8 : bitPosition + bitsLeft;
94 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
95 (column * 8);
96 rfBuf[arrayEntry] &= ~mask;
97 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
98 (column * 8)) & mask;
99 bitsLeft -= 8 - bitPosition;
100 tmp32 = tmp32 >> (8 - bitPosition);
101 bitPosition = 0;
102 arrayEntry++;
103 }
104 }
105
106 /*
107 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
108 * rf_pwd_icsyndiv.
109 *
110 * Theoretical Rules:
111 * if 2 GHz band
112 * if forceBiasAuto
113 * if synth_freq < 2412
114 * bias = 0
115 * else if 2412 <= synth_freq <= 2422
116 * bias = 1
117 * else // synth_freq > 2422
118 * bias = 2
119 * else if forceBias > 0
120 * bias = forceBias & 7
121 * else
122 * no change, use value from ini file
123 * else
124 * no change, invalid band
125 *
126 * 1st Mod:
127 * 2422 also uses value of 2
128 * <approved>
129 *
130 * 2nd Mod:
131 * Less than 2412 uses value of 0, 2412 and above uses value of 2
132 */
133 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
134 {
135 struct ath_common *common = ath9k_hw_common(ah);
136 u32 tmp_reg;
137 int reg_writes = 0;
138 u32 new_bias = 0;
139
140 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
141 return;
142
143 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
144
145 if (synth_freq < 2412)
146 new_bias = 0;
147 else if (synth_freq < 2422)
148 new_bias = 1;
149 else
150 new_bias = 2;
151
152 /* pre-reverse this field */
153 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
154
155 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
156 new_bias, synth_freq);
157
158 /* swizzle rf_pwd_icsyndiv */
159 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
160
161 /* write Bank 6 with new params */
162 ar5008_write_bank6(ah, &reg_writes);
163 }
164
165 /**
166 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
167 * @ah: atheros hardware structure
168 * @chan:
169 *
170 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
171 * the channel value. Assumes writes enabled to analog bus and bank6 register
172 * cache in ah->analogBank6Data.
173 */
174 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
175 {
176 struct ath_common *common = ath9k_hw_common(ah);
177 u32 channelSel = 0;
178 u32 bModeSynth = 0;
179 u32 aModeRefSel = 0;
180 u32 reg32 = 0;
181 u16 freq;
182 struct chan_centers centers;
183
184 ath9k_hw_get_channel_centers(ah, chan, &centers);
185 freq = centers.synth_center;
186
187 if (freq < 4800) {
188 u32 txctl;
189
190 if (((freq - 2192) % 5) == 0) {
191 channelSel = ((freq - 672) * 2 - 3040) / 10;
192 bModeSynth = 0;
193 } else if (((freq - 2224) % 5) == 0) {
194 channelSel = ((freq - 704) * 2 - 3040) / 10;
195 bModeSynth = 1;
196 } else {
197 ath_err(common, "Invalid channel %u MHz\n", freq);
198 return -EINVAL;
199 }
200
201 channelSel = (channelSel << 2) & 0xff;
202 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
203
204 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
205 if (freq == 2484) {
206
207 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
208 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
209 } else {
210 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
211 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
212 }
213
214 } else if ((freq % 20) == 0 && freq >= 5120) {
215 channelSel =
216 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
217 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
218 } else if ((freq % 10) == 0) {
219 channelSel =
220 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
221 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
222 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
223 else
224 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
225 } else if ((freq % 5) == 0) {
226 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
227 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
228 } else {
229 ath_err(common, "Invalid channel %u MHz\n", freq);
230 return -EINVAL;
231 }
232
233 ar5008_hw_force_bias(ah, freq);
234
235 reg32 =
236 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
237 (1 << 5) | 0x1;
238
239 REG_WRITE(ah, AR_PHY(0x37), reg32);
240
241 ah->curchan = chan;
242
243 return 0;
244 }
245
246 /**
247 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
248 * @ah: atheros hardware structure
249 * @chan:
250 *
251 * For non single-chip solutions. Converts to baseband spur frequency given the
252 * input channel frequency and compute register settings below.
253 */
254 static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
255 struct ath9k_channel *chan)
256 {
257 int bb_spur = AR_NO_SPUR;
258 int bin, cur_bin;
259 int spur_freq_sd;
260 int spur_delta_phase;
261 int denominator;
262 int upper, lower, cur_vit_mask;
263 int tmp, new;
264 int i;
265 static int pilot_mask_reg[4] = {
266 AR_PHY_TIMING7, AR_PHY_TIMING8,
267 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
268 };
269 static int chan_mask_reg[4] = {
270 AR_PHY_TIMING9, AR_PHY_TIMING10,
271 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
272 };
273 static int inc[4] = { 0, 100, 0, 0 };
274
275 int8_t mask_m[123];
276 int8_t mask_p[123];
277 int8_t mask_amt;
278 int tmp_mask;
279 int cur_bb_spur;
280 bool is2GHz = IS_CHAN_2GHZ(chan);
281
282 memset(&mask_m, 0, sizeof(int8_t) * 123);
283 memset(&mask_p, 0, sizeof(int8_t) * 123);
284
285 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
286 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
287 if (AR_NO_SPUR == cur_bb_spur)
288 break;
289 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
290 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
291 bb_spur = cur_bb_spur;
292 break;
293 }
294 }
295
296 if (AR_NO_SPUR == bb_spur)
297 return;
298
299 bin = bb_spur * 32;
300
301 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
302 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
303 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
304 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
305 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
306
307 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
308
309 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
310 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
311 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
312 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
313 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
314 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
315
316 spur_delta_phase = ((bb_spur * 524288) / 100) &
317 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
318
319 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
320 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
321
322 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
323 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
324 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
325 REG_WRITE(ah, AR_PHY_TIMING11, new);
326
327 cur_bin = -6000;
328 upper = bin + 100;
329 lower = bin - 100;
330
331 for (i = 0; i < 4; i++) {
332 int pilot_mask = 0;
333 int chan_mask = 0;
334 int bp = 0;
335 for (bp = 0; bp < 30; bp++) {
336 if ((cur_bin > lower) && (cur_bin < upper)) {
337 pilot_mask = pilot_mask | 0x1 << bp;
338 chan_mask = chan_mask | 0x1 << bp;
339 }
340 cur_bin += 100;
341 }
342 cur_bin += inc[i];
343 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
344 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
345 }
346
347 cur_vit_mask = 6100;
348 upper = bin + 120;
349 lower = bin - 120;
350
351 for (i = 0; i < 123; i++) {
352 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
353
354 /* workaround for gcc bug #37014 */
355 volatile int tmp_v = abs(cur_vit_mask - bin);
356
357 if (tmp_v < 75)
358 mask_amt = 1;
359 else
360 mask_amt = 0;
361 if (cur_vit_mask < 0)
362 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
363 else
364 mask_p[cur_vit_mask / 100] = mask_amt;
365 }
366 cur_vit_mask -= 100;
367 }
368
369 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
370 | (mask_m[48] << 26) | (mask_m[49] << 24)
371 | (mask_m[50] << 22) | (mask_m[51] << 20)
372 | (mask_m[52] << 18) | (mask_m[53] << 16)
373 | (mask_m[54] << 14) | (mask_m[55] << 12)
374 | (mask_m[56] << 10) | (mask_m[57] << 8)
375 | (mask_m[58] << 6) | (mask_m[59] << 4)
376 | (mask_m[60] << 2) | (mask_m[61] << 0);
377 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
378 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
379
380 tmp_mask = (mask_m[31] << 28)
381 | (mask_m[32] << 26) | (mask_m[33] << 24)
382 | (mask_m[34] << 22) | (mask_m[35] << 20)
383 | (mask_m[36] << 18) | (mask_m[37] << 16)
384 | (mask_m[48] << 14) | (mask_m[39] << 12)
385 | (mask_m[40] << 10) | (mask_m[41] << 8)
386 | (mask_m[42] << 6) | (mask_m[43] << 4)
387 | (mask_m[44] << 2) | (mask_m[45] << 0);
388 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
389 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
390
391 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
392 | (mask_m[18] << 26) | (mask_m[18] << 24)
393 | (mask_m[20] << 22) | (mask_m[20] << 20)
394 | (mask_m[22] << 18) | (mask_m[22] << 16)
395 | (mask_m[24] << 14) | (mask_m[24] << 12)
396 | (mask_m[25] << 10) | (mask_m[26] << 8)
397 | (mask_m[27] << 6) | (mask_m[28] << 4)
398 | (mask_m[29] << 2) | (mask_m[30] << 0);
399 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
400 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
401
402 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
403 | (mask_m[2] << 26) | (mask_m[3] << 24)
404 | (mask_m[4] << 22) | (mask_m[5] << 20)
405 | (mask_m[6] << 18) | (mask_m[7] << 16)
406 | (mask_m[8] << 14) | (mask_m[9] << 12)
407 | (mask_m[10] << 10) | (mask_m[11] << 8)
408 | (mask_m[12] << 6) | (mask_m[13] << 4)
409 | (mask_m[14] << 2) | (mask_m[15] << 0);
410 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
411 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
412
413 tmp_mask = (mask_p[15] << 28)
414 | (mask_p[14] << 26) | (mask_p[13] << 24)
415 | (mask_p[12] << 22) | (mask_p[11] << 20)
416 | (mask_p[10] << 18) | (mask_p[9] << 16)
417 | (mask_p[8] << 14) | (mask_p[7] << 12)
418 | (mask_p[6] << 10) | (mask_p[5] << 8)
419 | (mask_p[4] << 6) | (mask_p[3] << 4)
420 | (mask_p[2] << 2) | (mask_p[1] << 0);
421 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
422 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
423
424 tmp_mask = (mask_p[30] << 28)
425 | (mask_p[29] << 26) | (mask_p[28] << 24)
426 | (mask_p[27] << 22) | (mask_p[26] << 20)
427 | (mask_p[25] << 18) | (mask_p[24] << 16)
428 | (mask_p[23] << 14) | (mask_p[22] << 12)
429 | (mask_p[21] << 10) | (mask_p[20] << 8)
430 | (mask_p[19] << 6) | (mask_p[18] << 4)
431 | (mask_p[17] << 2) | (mask_p[16] << 0);
432 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
433 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
434
435 tmp_mask = (mask_p[45] << 28)
436 | (mask_p[44] << 26) | (mask_p[43] << 24)
437 | (mask_p[42] << 22) | (mask_p[41] << 20)
438 | (mask_p[40] << 18) | (mask_p[39] << 16)
439 | (mask_p[38] << 14) | (mask_p[37] << 12)
440 | (mask_p[36] << 10) | (mask_p[35] << 8)
441 | (mask_p[34] << 6) | (mask_p[33] << 4)
442 | (mask_p[32] << 2) | (mask_p[31] << 0);
443 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
444 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
445
446 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
447 | (mask_p[59] << 26) | (mask_p[58] << 24)
448 | (mask_p[57] << 22) | (mask_p[56] << 20)
449 | (mask_p[55] << 18) | (mask_p[54] << 16)
450 | (mask_p[53] << 14) | (mask_p[52] << 12)
451 | (mask_p[51] << 10) | (mask_p[50] << 8)
452 | (mask_p[49] << 6) | (mask_p[48] << 4)
453 | (mask_p[47] << 2) | (mask_p[46] << 0);
454 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
455 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
456 }
457
458 /**
459 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
460 * @ah: atheros hardware structure
461 *
462 * Only required for older devices with external AR2133/AR5133 radios.
463 */
464 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
465 {
466 int size = ah->iniBank6.ia_rows * sizeof(u32);
467
468 if (AR_SREV_9280_20_OR_LATER(ah))
469 return 0;
470
471 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL);
472 if (!ah->analogBank6Data)
473 return -ENOMEM;
474
475 return 0;
476 }
477
478
479 /* *
480 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
481 * @ah: atheros hardware structure
482 * @chan:
483 * @modesIndex:
484 *
485 * Used for the external AR2133/AR5133 radios.
486 *
487 * Reads the EEPROM header info from the device structure and programs
488 * all rf registers. This routine requires access to the analog
489 * rf device. This is not required for single-chip devices.
490 */
491 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
492 struct ath9k_channel *chan,
493 u16 modesIndex)
494 {
495 u32 eepMinorRev;
496 u32 ob5GHz = 0, db5GHz = 0;
497 u32 ob2GHz = 0, db2GHz = 0;
498 int regWrites = 0;
499 int i;
500
501 /*
502 * Software does not need to program bank data
503 * for single chip devices, that is AR9280 or anything
504 * after that.
505 */
506 if (AR_SREV_9280_20_OR_LATER(ah))
507 return true;
508
509 /* Setup rf parameters */
510 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
511
512 for (i = 0; i < ah->iniBank6.ia_rows; i++)
513 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex);
514
515 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
516 if (eepMinorRev >= 2) {
517 if (IS_CHAN_2GHZ(chan)) {
518 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
519 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
520 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
521 ob2GHz, 3, 197, 0);
522 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
523 db2GHz, 3, 194, 0);
524 } else {
525 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
526 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
527 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
528 ob5GHz, 3, 203, 0);
529 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
530 db5GHz, 3, 200, 0);
531 }
532 }
533
534 /* Write Analog registers */
535 REG_WRITE_ARRAY(&bank0, 1, regWrites);
536 REG_WRITE_ARRAY(&bank1, 1, regWrites);
537 REG_WRITE_ARRAY(&bank2, 1, regWrites);
538 REG_WRITE_ARRAY(&bank3, modesIndex, regWrites);
539 ar5008_write_bank6(ah, &regWrites);
540 REG_WRITE_ARRAY(&bank7, 1, regWrites);
541
542 return true;
543 }
544
545 static void ar5008_hw_init_bb(struct ath_hw *ah,
546 struct ath9k_channel *chan)
547 {
548 u32 synthDelay;
549
550 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
551
552 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
553
554 ath9k_hw_synth_delay(ah, chan, synthDelay);
555 }
556
557 static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
558 {
559 int rx_chainmask, tx_chainmask;
560
561 rx_chainmask = ah->rxchainmask;
562 tx_chainmask = ah->txchainmask;
563
564
565 switch (rx_chainmask) {
566 case 0x5:
567 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
568 AR_PHY_SWAP_ALT_CHAIN);
569 case 0x3:
570 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
571 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
572 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
573 break;
574 }
575 case 0x1:
576 case 0x2:
577 case 0x7:
578 ENABLE_REGWRITE_BUFFER(ah);
579 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
580 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
581 break;
582 default:
583 ENABLE_REGWRITE_BUFFER(ah);
584 break;
585 }
586
587 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
588
589 REGWRITE_BUFFER_FLUSH(ah);
590
591 if (tx_chainmask == 0x5) {
592 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
593 AR_PHY_SWAP_ALT_CHAIN);
594 }
595 if (AR_SREV_9100(ah))
596 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
597 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
598 }
599
600 static void ar5008_hw_override_ini(struct ath_hw *ah,
601 struct ath9k_channel *chan)
602 {
603 u32 val;
604
605 /*
606 * Set the RX_ABORT and RX_DIS and clear if off only after
607 * RXE is set for MAC. This prevents frames with corrupted
608 * descriptor status.
609 */
610 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
611
612 if (AR_SREV_9280_20_OR_LATER(ah)) {
613 /*
614 * For AR9280 and above, there is a new feature that allows
615 * Multicast search based on both MAC Address and Key ID.
616 * By default, this feature is enabled. But since the driver
617 * is not using this feature, we switch it off; otherwise
618 * multicast search based on MAC addr only will fail.
619 */
620 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
621 (~AR_ADHOC_MCAST_KEYID_ENABLE);
622
623 if (!AR_SREV_9271(ah))
624 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
625
626 if (AR_SREV_9287_11_OR_LATER(ah))
627 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
628
629 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
630 }
631
632 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
633 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
634
635 if (AR_SREV_9280_20_OR_LATER(ah))
636 return;
637 /*
638 * Disable BB clock gating
639 * Necessary to avoid issues on AR5416 2.0
640 */
641 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
642
643 /*
644 * Disable RIFS search on some chips to avoid baseband
645 * hang issues.
646 */
647 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
648 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
649 val &= ~AR_PHY_RIFS_INIT_DELAY;
650 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
651 }
652 }
653
654 static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
655 struct ath9k_channel *chan)
656 {
657 u32 phymode;
658 u32 enableDacFifo = 0;
659
660 if (AR_SREV_9285_12_OR_LATER(ah))
661 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
662 AR_PHY_FC_ENABLE_DAC_FIFO);
663
664 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
665 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
666
667 if (IS_CHAN_HT40(chan)) {
668 phymode |= AR_PHY_FC_DYN2040_EN;
669
670 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
671 (chan->chanmode == CHANNEL_G_HT40PLUS))
672 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
673
674 }
675 REG_WRITE(ah, AR_PHY_TURBO, phymode);
676
677 ath9k_hw_set11nmac2040(ah);
678
679 ENABLE_REGWRITE_BUFFER(ah);
680
681 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
682 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
683
684 REGWRITE_BUFFER_FLUSH(ah);
685 }
686
687
688 static int ar5008_hw_process_ini(struct ath_hw *ah,
689 struct ath9k_channel *chan)
690 {
691 struct ath_common *common = ath9k_hw_common(ah);
692 int i, regWrites = 0;
693 u32 modesIndex, freqIndex;
694
695 switch (chan->chanmode) {
696 case CHANNEL_A:
697 case CHANNEL_A_HT20:
698 modesIndex = 1;
699 freqIndex = 1;
700 break;
701 case CHANNEL_A_HT40PLUS:
702 case CHANNEL_A_HT40MINUS:
703 modesIndex = 2;
704 freqIndex = 1;
705 break;
706 case CHANNEL_G:
707 case CHANNEL_G_HT20:
708 case CHANNEL_B:
709 modesIndex = 4;
710 freqIndex = 2;
711 break;
712 case CHANNEL_G_HT40PLUS:
713 case CHANNEL_G_HT40MINUS:
714 modesIndex = 3;
715 freqIndex = 2;
716 break;
717
718 default:
719 return -EINVAL;
720 }
721
722 /*
723 * Set correct baseband to analog shift setting to
724 * access analog chips.
725 */
726 REG_WRITE(ah, AR_PHY(0), 0x00000007);
727
728 /* Write ADDAC shifts */
729 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
730 if (ah->eep_ops->set_addac)
731 ah->eep_ops->set_addac(ah, chan);
732
733 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
734 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
735
736 ENABLE_REGWRITE_BUFFER(ah);
737
738 for (i = 0; i < ah->iniModes.ia_rows; i++) {
739 u32 reg = INI_RA(&ah->iniModes, i, 0);
740 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
741
742 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
743 val &= ~AR_AN_TOP2_PWDCLKIND;
744
745 REG_WRITE(ah, reg, val);
746
747 if (reg >= 0x7800 && reg < 0x78a0
748 && ah->config.analog_shiftreg
749 && (common->bus_ops->ath_bus_type != ATH_USB)) {
750 udelay(100);
751 }
752
753 DO_DELAY(regWrites);
754 }
755
756 REGWRITE_BUFFER_FLUSH(ah);
757
758 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
759 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
760
761 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
762 AR_SREV_9287_11_OR_LATER(ah))
763 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
764
765 if (AR_SREV_9271_10(ah)) {
766 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA);
767 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa);
768 }
769
770 ENABLE_REGWRITE_BUFFER(ah);
771
772 /* Write common array parameters */
773 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
774 u32 reg = INI_RA(&ah->iniCommon, i, 0);
775 u32 val = INI_RA(&ah->iniCommon, i, 1);
776
777 REG_WRITE(ah, reg, val);
778
779 if (reg >= 0x7800 && reg < 0x78a0
780 && ah->config.analog_shiftreg
781 && (common->bus_ops->ath_bus_type != ATH_USB)) {
782 udelay(100);
783 }
784
785 DO_DELAY(regWrites);
786 }
787
788 REGWRITE_BUFFER_FLUSH(ah);
789
790 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
791
792 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
793 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex,
794 regWrites);
795
796 ar5008_hw_override_ini(ah, chan);
797 ar5008_hw_set_channel_regs(ah, chan);
798 ar5008_hw_init_chain_masks(ah);
799 ath9k_olc_init(ah);
800 ath9k_hw_apply_txpower(ah, chan, false);
801
802 /* Write analog registers */
803 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
804 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
805 return -EIO;
806 }
807
808 return 0;
809 }
810
811 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
812 {
813 u32 rfMode = 0;
814
815 if (chan == NULL)
816 return;
817
818 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
819 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
820
821 if (!AR_SREV_9280_20_OR_LATER(ah))
822 rfMode |= (IS_CHAN_5GHZ(chan)) ?
823 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
824
825 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
826 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
827
828 REG_WRITE(ah, AR_PHY_MODE, rfMode);
829 }
830
831 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
832 {
833 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
834 }
835
836 static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
837 struct ath9k_channel *chan)
838 {
839 u32 coef_scaled, ds_coef_exp, ds_coef_man;
840 u32 clockMhzScaled = 0x64000000;
841 struct chan_centers centers;
842
843 if (IS_CHAN_HALF_RATE(chan))
844 clockMhzScaled = clockMhzScaled >> 1;
845 else if (IS_CHAN_QUARTER_RATE(chan))
846 clockMhzScaled = clockMhzScaled >> 2;
847
848 ath9k_hw_get_channel_centers(ah, chan, &centers);
849 coef_scaled = clockMhzScaled / centers.synth_center;
850
851 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
852 &ds_coef_exp);
853
854 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
855 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
856 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
857 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
858
859 coef_scaled = (9 * coef_scaled) / 10;
860
861 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
862 &ds_coef_exp);
863
864 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
865 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
866 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
867 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
868 }
869
870 static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
871 {
872 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
873 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
874 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
875 }
876
877 static void ar5008_hw_rfbus_done(struct ath_hw *ah)
878 {
879 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
880
881 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
882
883 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
884 }
885
886 static void ar5008_restore_chainmask(struct ath_hw *ah)
887 {
888 int rx_chainmask = ah->rxchainmask;
889
890 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
891 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
892 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
893 }
894 }
895
896 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
897 struct ath9k_channel *chan)
898 {
899 u32 pll;
900
901 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
902
903 if (chan && IS_CHAN_HALF_RATE(chan))
904 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
905 else if (chan && IS_CHAN_QUARTER_RATE(chan))
906 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
907
908 if (chan && IS_CHAN_5GHZ(chan))
909 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
910 else
911 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
912
913 return pll;
914 }
915
916 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
917 struct ath9k_channel *chan)
918 {
919 u32 pll;
920
921 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
922
923 if (chan && IS_CHAN_HALF_RATE(chan))
924 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
925 else if (chan && IS_CHAN_QUARTER_RATE(chan))
926 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
927
928 if (chan && IS_CHAN_5GHZ(chan))
929 pll |= SM(0xa, AR_RTC_PLL_DIV);
930 else
931 pll |= SM(0xb, AR_RTC_PLL_DIV);
932
933 return pll;
934 }
935
936 static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
937 enum ath9k_ani_cmd cmd,
938 int param)
939 {
940 struct ath_common *common = ath9k_hw_common(ah);
941 struct ath9k_channel *chan = ah->curchan;
942 struct ar5416AniState *aniState = &ah->ani;
943 s32 value, value2;
944
945 switch (cmd & ah->ani_function) {
946 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
947 /*
948 * on == 1 means ofdm weak signal detection is ON
949 * on == 1 is the default, for less noise immunity
950 *
951 * on == 0 means ofdm weak signal detection is OFF
952 * on == 0 means more noise imm
953 */
954 u32 on = param ? 1 : 0;
955 /*
956 * make register setting for default
957 * (weak sig detect ON) come from INI file
958 */
959 int m1ThreshLow = on ?
960 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
961 int m2ThreshLow = on ?
962 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
963 int m1Thresh = on ?
964 aniState->iniDef.m1Thresh : m1Thresh_off;
965 int m2Thresh = on ?
966 aniState->iniDef.m2Thresh : m2Thresh_off;
967 int m2CountThr = on ?
968 aniState->iniDef.m2CountThr : m2CountThr_off;
969 int m2CountThrLow = on ?
970 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
971 int m1ThreshLowExt = on ?
972 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
973 int m2ThreshLowExt = on ?
974 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
975 int m1ThreshExt = on ?
976 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
977 int m2ThreshExt = on ?
978 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
979
980 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
981 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
982 m1ThreshLow);
983 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
984 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
985 m2ThreshLow);
986 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
987 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
988 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
989 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
990 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
991 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
992 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
993 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
994 m2CountThrLow);
995
996 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
997 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
998 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
999 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
1000 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1001 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
1002 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1003 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
1004
1005 if (on)
1006 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1007 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1008 else
1009 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1010 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1011
1012 if (on != aniState->ofdmWeakSigDetect) {
1013 ath_dbg(common, ANI,
1014 "** ch %d: ofdm weak signal: %s=>%s\n",
1015 chan->channel,
1016 aniState->ofdmWeakSigDetect ?
1017 "on" : "off",
1018 on ? "on" : "off");
1019 if (on)
1020 ah->stats.ast_ani_ofdmon++;
1021 else
1022 ah->stats.ast_ani_ofdmoff++;
1023 aniState->ofdmWeakSigDetect = on;
1024 }
1025 break;
1026 }
1027 case ATH9K_ANI_FIRSTEP_LEVEL:{
1028 u32 level = param;
1029
1030 if (level >= ARRAY_SIZE(firstep_table)) {
1031 ath_dbg(common, ANI,
1032 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1033 level, ARRAY_SIZE(firstep_table));
1034 return false;
1035 }
1036
1037 /*
1038 * make register setting relative to default
1039 * from INI file & cap value
1040 */
1041 value = firstep_table[level] -
1042 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1043 aniState->iniDef.firstep;
1044 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1045 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1046 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1047 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1048 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1049 AR_PHY_FIND_SIG_FIRSTEP,
1050 value);
1051 /*
1052 * we need to set first step low register too
1053 * make register setting relative to default
1054 * from INI file & cap value
1055 */
1056 value2 = firstep_table[level] -
1057 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1058 aniState->iniDef.firstepLow;
1059 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1060 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1061 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1062 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1063
1064 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1065 AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
1066
1067 if (level != aniState->firstepLevel) {
1068 ath_dbg(common, ANI,
1069 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1070 chan->channel,
1071 aniState->firstepLevel,
1072 level,
1073 ATH9K_ANI_FIRSTEP_LVL,
1074 value,
1075 aniState->iniDef.firstep);
1076 ath_dbg(common, ANI,
1077 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1078 chan->channel,
1079 aniState->firstepLevel,
1080 level,
1081 ATH9K_ANI_FIRSTEP_LVL,
1082 value2,
1083 aniState->iniDef.firstepLow);
1084 if (level > aniState->firstepLevel)
1085 ah->stats.ast_ani_stepup++;
1086 else if (level < aniState->firstepLevel)
1087 ah->stats.ast_ani_stepdown++;
1088 aniState->firstepLevel = level;
1089 }
1090 break;
1091 }
1092 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1093 u32 level = param;
1094
1095 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1096 ath_dbg(common, ANI,
1097 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1098 level, ARRAY_SIZE(cycpwrThr1_table));
1099 return false;
1100 }
1101 /*
1102 * make register setting relative to default
1103 * from INI file & cap value
1104 */
1105 value = cycpwrThr1_table[level] -
1106 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1107 aniState->iniDef.cycpwrThr1;
1108 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1109 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1110 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1111 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1112 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1113 AR_PHY_TIMING5_CYCPWR_THR1,
1114 value);
1115
1116 /*
1117 * set AR_PHY_EXT_CCA for extension channel
1118 * make register setting relative to default
1119 * from INI file & cap value
1120 */
1121 value2 = cycpwrThr1_table[level] -
1122 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1123 aniState->iniDef.cycpwrThr1Ext;
1124 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1125 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1126 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1127 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1128 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1129 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
1130
1131 if (level != aniState->spurImmunityLevel) {
1132 ath_dbg(common, ANI,
1133 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1134 chan->channel,
1135 aniState->spurImmunityLevel,
1136 level,
1137 ATH9K_ANI_SPUR_IMMUNE_LVL,
1138 value,
1139 aniState->iniDef.cycpwrThr1);
1140 ath_dbg(common, ANI,
1141 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1142 chan->channel,
1143 aniState->spurImmunityLevel,
1144 level,
1145 ATH9K_ANI_SPUR_IMMUNE_LVL,
1146 value2,
1147 aniState->iniDef.cycpwrThr1Ext);
1148 if (level > aniState->spurImmunityLevel)
1149 ah->stats.ast_ani_spurup++;
1150 else if (level < aniState->spurImmunityLevel)
1151 ah->stats.ast_ani_spurdown++;
1152 aniState->spurImmunityLevel = level;
1153 }
1154 break;
1155 }
1156 case ATH9K_ANI_MRC_CCK:
1157 /*
1158 * You should not see this as AR5008, AR9001, AR9002
1159 * does not have hardware support for MRC CCK.
1160 */
1161 WARN_ON(1);
1162 break;
1163 default:
1164 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1165 return false;
1166 }
1167
1168 ath_dbg(common, ANI,
1169 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1170 aniState->spurImmunityLevel,
1171 aniState->ofdmWeakSigDetect ? "on" : "off",
1172 aniState->firstepLevel,
1173 aniState->mrcCCK ? "on" : "off",
1174 aniState->listenTime,
1175 aniState->ofdmPhyErrCount,
1176 aniState->cckPhyErrCount);
1177 return true;
1178 }
1179
1180 static void ar5008_hw_do_getnf(struct ath_hw *ah,
1181 int16_t nfarray[NUM_NF_READINGS])
1182 {
1183 int16_t nf;
1184
1185 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1186 nfarray[0] = sign_extend32(nf, 8);
1187
1188 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
1189 nfarray[1] = sign_extend32(nf, 8);
1190
1191 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
1192 nfarray[2] = sign_extend32(nf, 8);
1193
1194 if (!IS_CHAN_HT40(ah->curchan))
1195 return;
1196
1197 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1198 nfarray[3] = sign_extend32(nf, 8);
1199
1200 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
1201 nfarray[4] = sign_extend32(nf, 8);
1202
1203 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
1204 nfarray[5] = sign_extend32(nf, 8);
1205 }
1206
1207 /*
1208 * Initialize the ANI register values with default (ini) values.
1209 * This routine is called during a (full) hardware reset after
1210 * all the registers are initialised from the INI.
1211 */
1212 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1213 {
1214 struct ath_common *common = ath9k_hw_common(ah);
1215 struct ath9k_channel *chan = ah->curchan;
1216 struct ar5416AniState *aniState = &ah->ani;
1217 struct ath9k_ani_default *iniDef;
1218 u32 val;
1219
1220 iniDef = &aniState->iniDef;
1221
1222 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1223 ah->hw_version.macVersion,
1224 ah->hw_version.macRev,
1225 ah->opmode,
1226 chan->channel,
1227 chan->channelFlags);
1228
1229 val = REG_READ(ah, AR_PHY_SFCORR);
1230 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1231 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1232 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1233
1234 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1235 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1236 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1237 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1238
1239 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1240 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1241 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1242 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1243 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1244 iniDef->firstep = REG_READ_FIELD(ah,
1245 AR_PHY_FIND_SIG,
1246 AR_PHY_FIND_SIG_FIRSTEP);
1247 iniDef->firstepLow = REG_READ_FIELD(ah,
1248 AR_PHY_FIND_SIG_LOW,
1249 AR_PHY_FIND_SIG_FIRSTEP_LOW);
1250 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1251 AR_PHY_TIMING5,
1252 AR_PHY_TIMING5_CYCPWR_THR1);
1253 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1254 AR_PHY_EXT_CCA,
1255 AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1256
1257 /* these levels just got reset to defaults by the INI */
1258 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1259 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1260 aniState->ofdmWeakSigDetect = true;
1261 aniState->mrcCCK = false; /* not available on pre AR9003 */
1262 }
1263
1264 static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1265 {
1266 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
1267 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
1268 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1269 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
1270 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
1271 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1272 }
1273
1274 static void ar5008_hw_set_radar_params(struct ath_hw *ah,
1275 struct ath_hw_radar_conf *conf)
1276 {
1277 u32 radar_0 = 0, radar_1 = 0;
1278
1279 if (!conf) {
1280 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1281 return;
1282 }
1283
1284 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1285 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1286 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1287 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1288 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1289 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1290
1291 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1292 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1293 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1294 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1295 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1296
1297 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1298 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1299 if (conf->ext_channel)
1300 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1301 else
1302 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1303 }
1304
1305 static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
1306 {
1307 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1308
1309 conf->fir_power = -33;
1310 conf->radar_rssi = 20;
1311 conf->pulse_height = 10;
1312 conf->pulse_rssi = 24;
1313 conf->pulse_inband = 15;
1314 conf->pulse_maxlen = 255;
1315 conf->pulse_inband_step = 12;
1316 conf->radar_inband = 8;
1317 }
1318
1319 int ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1320 {
1321 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1322 static const u32 ar5416_cca_regs[6] = {
1323 AR_PHY_CCA,
1324 AR_PHY_CH1_CCA,
1325 AR_PHY_CH2_CCA,
1326 AR_PHY_EXT_CCA,
1327 AR_PHY_CH1_EXT_CCA,
1328 AR_PHY_CH2_EXT_CCA
1329 };
1330 int ret;
1331
1332 ret = ar5008_hw_rf_alloc_ext_banks(ah);
1333 if (ret)
1334 return ret;
1335
1336 priv_ops->rf_set_freq = ar5008_hw_set_channel;
1337 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1338
1339 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1340 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1341 priv_ops->init_bb = ar5008_hw_init_bb;
1342 priv_ops->process_ini = ar5008_hw_process_ini;
1343 priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1344 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1345 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1346 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1347 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
1348 priv_ops->restore_chainmask = ar5008_restore_chainmask;
1349 priv_ops->do_getnf = ar5008_hw_do_getnf;
1350 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
1351
1352 priv_ops->ani_control = ar5008_hw_ani_control_new;
1353 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1354
1355 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
1356 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1357 else
1358 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
1359
1360 ar5008_hw_set_nf_limits(ah);
1361 ar5008_hw_set_radar_conf(ah);
1362 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
1363 return 0;
1364 }
Linux with added FPC-III support