?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ARM: mm: Recreate kernel mappings in early_paging_init()
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / mac.c
bloba3eff0986a3f95c1ea6b523fc71b02a1ac2b4eba
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "hw-ops.h"
19 #include <linux/export.h>
20
21 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
22 struct ath9k_tx_queue_info *qi)
23 {
24 ath_dbg(ath9k_hw_common(ah), INTERRUPT,
25 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
28 ah->txurn_interrupt_mask);
29
30 ENABLE_REGWRITE_BUFFER(ah);
31
32 REG_WRITE(ah, AR_IMR_S0,
33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
35 REG_WRITE(ah, AR_IMR_S1,
36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
38
39 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
40 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
42
43 REGWRITE_BUFFER_FLUSH(ah);
44 }
45
46 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
47 {
48 return REG_READ(ah, AR_QTXDP(q));
49 }
50 EXPORT_SYMBOL(ath9k_hw_gettxbuf);
51
52 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
53 {
54 REG_WRITE(ah, AR_QTXDP(q), txdp);
55 }
56 EXPORT_SYMBOL(ath9k_hw_puttxbuf);
57
58 void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
59 {
60 ath_dbg(ath9k_hw_common(ah), QUEUE, "Enable TXE on queue: %u\n", q);
61 REG_WRITE(ah, AR_Q_TXE, 1 << q);
62 }
63 EXPORT_SYMBOL(ath9k_hw_txstart);
64
65 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
66 {
67 u32 npend;
68
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
70 if (npend == 0) {
71
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
73 npend = 1;
74 }
75
76 return npend;
77 }
78 EXPORT_SYMBOL(ath9k_hw_numtxpending);
79
80 /**
81 * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
82 *
83 * @ah: atheros hardware struct
84 * @bIncTrigLevel: whether or not the frame trigger level should be updated
85 *
86 * The frame trigger level specifies the minimum number of bytes,
87 * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
88 * before the PCU will initiate sending the frame on the air. This can
89 * mean we initiate transmit before a full frame is on the PCU TX FIFO.
90 * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
91 * first)
92 *
93 * Caution must be taken to ensure to set the frame trigger level based
94 * on the DMA request size. For example if the DMA request size is set to
95 * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
96 * there need to be enough space in the tx FIFO for the requested transfer
97 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
98 * the threshold to a value beyond 6, then the transmit will hang.
99 *
100 * Current dual stream devices have a PCU TX FIFO size of 8 KB.
101 * Current single stream devices have a PCU TX FIFO size of 4 KB, however,
102 * there is a hardware issue which forces us to use 2 KB instead so the
103 * frame trigger level must not exceed 2 KB for these chipsets.
104 */
105 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
106 {
107 u32 txcfg, curLevel, newLevel;
108
109 if (ah->tx_trig_level >= ah->config.max_txtrig_level)
110 return false;
111
112 ath9k_hw_disable_interrupts(ah);
113
114 txcfg = REG_READ(ah, AR_TXCFG);
115 curLevel = MS(txcfg, AR_FTRIG);
116 newLevel = curLevel;
117 if (bIncTrigLevel) {
118 if (curLevel < ah->config.max_txtrig_level)
119 newLevel++;
120 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
121 newLevel--;
122 if (newLevel != curLevel)
123 REG_WRITE(ah, AR_TXCFG,
124 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
125
126 ath9k_hw_enable_interrupts(ah);
127
128 ah->tx_trig_level = newLevel;
129
130 return newLevel != curLevel;
131 }
132 EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
133
134 void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
135 {
136 int maxdelay = 1000;
137 int i, q;
138
139 if (ah->curchan) {
140 if (IS_CHAN_HALF_RATE(ah->curchan))
141 maxdelay *= 2;
142 else if (IS_CHAN_QUARTER_RATE(ah->curchan))
143 maxdelay *= 4;
144 }
145
146 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
147
148 REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
149 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
150 REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
151
152 for (q = 0; q < AR_NUM_QCU; q++) {
153 for (i = 0; i < maxdelay; i++) {
154 if (i)
155 udelay(5);
156
157 if (!ath9k_hw_numtxpending(ah, q))
158 break;
159 }
160 }
161
162 REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
163 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
164 REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
165
166 REG_WRITE(ah, AR_Q_TXD, 0);
167 }
168 EXPORT_SYMBOL(ath9k_hw_abort_tx_dma);
169
170 bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q)
171 {
172 #define ATH9K_TX_STOP_DMA_TIMEOUT 1000 /* usec */
173 #define ATH9K_TIME_QUANTUM 100 /* usec */
174 int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
175 int wait;
176
177 REG_WRITE(ah, AR_Q_TXD, 1 << q);
178
179 for (wait = wait_time; wait != 0; wait--) {
180 if (wait != wait_time)
181 udelay(ATH9K_TIME_QUANTUM);
182
183 if (ath9k_hw_numtxpending(ah, q) == 0)
184 break;
185 }
186
187 REG_WRITE(ah, AR_Q_TXD, 0);
188
189 return wait != 0;
190
191 #undef ATH9K_TX_STOP_DMA_TIMEOUT
192 #undef ATH9K_TIME_QUANTUM
193 }
194 EXPORT_SYMBOL(ath9k_hw_stop_dma_queue);
195
196 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
197 const struct ath9k_tx_queue_info *qinfo)
198 {
199 u32 cw;
200 struct ath_common *common = ath9k_hw_common(ah);
201 struct ath9k_tx_queue_info *qi;
202
203 qi = &ah->txq[q];
204 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
205 ath_dbg(common, QUEUE,
206 "Set TXQ properties, inactive queue: %u\n", q);
207 return false;
208 }
209
210 ath_dbg(common, QUEUE, "Set queue properties for: %u\n", q);
211
212 qi->tqi_ver = qinfo->tqi_ver;
213 qi->tqi_subtype = qinfo->tqi_subtype;
214 qi->tqi_qflags = qinfo->tqi_qflags;
215 qi->tqi_priority = qinfo->tqi_priority;
216 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
217 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
218 else
219 qi->tqi_aifs = INIT_AIFS;
220 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
221 cw = min(qinfo->tqi_cwmin, 1024U);
222 qi->tqi_cwmin = 1;
223 while (qi->tqi_cwmin < cw)
224 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
225 } else
226 qi->tqi_cwmin = qinfo->tqi_cwmin;
227 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
228 cw = min(qinfo->tqi_cwmax, 1024U);
229 qi->tqi_cwmax = 1;
230 while (qi->tqi_cwmax < cw)
231 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
232 } else
233 qi->tqi_cwmax = INIT_CWMAX;
234
235 if (qinfo->tqi_shretry != 0)
236 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
237 else
238 qi->tqi_shretry = INIT_SH_RETRY;
239 if (qinfo->tqi_lgretry != 0)
240 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
241 else
242 qi->tqi_lgretry = INIT_LG_RETRY;
243 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
244 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
245 qi->tqi_burstTime = qinfo->tqi_burstTime;
246 qi->tqi_readyTime = qinfo->tqi_readyTime;
247
248 switch (qinfo->tqi_subtype) {
249 case ATH9K_WME_UPSD:
250 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
251 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
252 break;
253 default:
254 break;
255 }
256
257 return true;
258 }
259 EXPORT_SYMBOL(ath9k_hw_set_txq_props);
260
261 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
262 struct ath9k_tx_queue_info *qinfo)
263 {
264 struct ath_common *common = ath9k_hw_common(ah);
265 struct ath9k_tx_queue_info *qi;
266
267 qi = &ah->txq[q];
268 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
269 ath_dbg(common, QUEUE,
270 "Get TXQ properties, inactive queue: %u\n", q);
271 return false;
272 }
273
274 qinfo->tqi_qflags = qi->tqi_qflags;
275 qinfo->tqi_ver = qi->tqi_ver;
276 qinfo->tqi_subtype = qi->tqi_subtype;
277 qinfo->tqi_qflags = qi->tqi_qflags;
278 qinfo->tqi_priority = qi->tqi_priority;
279 qinfo->tqi_aifs = qi->tqi_aifs;
280 qinfo->tqi_cwmin = qi->tqi_cwmin;
281 qinfo->tqi_cwmax = qi->tqi_cwmax;
282 qinfo->tqi_shretry = qi->tqi_shretry;
283 qinfo->tqi_lgretry = qi->tqi_lgretry;
284 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
285 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
286 qinfo->tqi_burstTime = qi->tqi_burstTime;
287 qinfo->tqi_readyTime = qi->tqi_readyTime;
288
289 return true;
290 }
291 EXPORT_SYMBOL(ath9k_hw_get_txq_props);
292
293 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
294 const struct ath9k_tx_queue_info *qinfo)
295 {
296 struct ath_common *common = ath9k_hw_common(ah);
297 struct ath9k_tx_queue_info *qi;
298 int q;
299
300 switch (type) {
301 case ATH9K_TX_QUEUE_BEACON:
302 q = ATH9K_NUM_TX_QUEUES - 1;
303 break;
304 case ATH9K_TX_QUEUE_CAB:
305 q = ATH9K_NUM_TX_QUEUES - 2;
306 break;
307 case ATH9K_TX_QUEUE_PSPOLL:
308 q = 1;
309 break;
310 case ATH9K_TX_QUEUE_UAPSD:
311 q = ATH9K_NUM_TX_QUEUES - 3;
312 break;
313 case ATH9K_TX_QUEUE_DATA:
314 for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++)
315 if (ah->txq[q].tqi_type ==
316 ATH9K_TX_QUEUE_INACTIVE)
317 break;
318 if (q == ATH9K_NUM_TX_QUEUES) {
319 ath_err(common, "No available TX queue\n");
320 return -1;
321 }
322 break;
323 default:
324 ath_err(common, "Invalid TX queue type: %u\n", type);
325 return -1;
326 }
327
328 ath_dbg(common, QUEUE, "Setup TX queue: %u\n", q);
329
330 qi = &ah->txq[q];
331 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
332 ath_err(common, "TX queue: %u already active\n", q);
333 return -1;
334 }
335 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
336 qi->tqi_type = type;
337 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
338 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
339
340 return q;
341 }
342 EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
343
344 static void ath9k_hw_clear_queue_interrupts(struct ath_hw *ah, u32 q)
345 {
346 ah->txok_interrupt_mask &= ~(1 << q);
347 ah->txerr_interrupt_mask &= ~(1 << q);
348 ah->txdesc_interrupt_mask &= ~(1 << q);
349 ah->txeol_interrupt_mask &= ~(1 << q);
350 ah->txurn_interrupt_mask &= ~(1 << q);
351 }
352
353 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
354 {
355 struct ath_common *common = ath9k_hw_common(ah);
356 struct ath9k_tx_queue_info *qi;
357
358 qi = &ah->txq[q];
359 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
360 ath_dbg(common, QUEUE, "Release TXQ, inactive queue: %u\n", q);
361 return false;
362 }
363
364 ath_dbg(common, QUEUE, "Release TX queue: %u\n", q);
365
366 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
367 ath9k_hw_clear_queue_interrupts(ah, q);
368 ath9k_hw_set_txq_interrupts(ah, qi);
369
370 return true;
371 }
372 EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
373
374 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
375 {
376 struct ath_common *common = ath9k_hw_common(ah);
377 struct ath9k_channel *chan = ah->curchan;
378 struct ath9k_tx_queue_info *qi;
379 u32 cwMin, chanCwMin, value;
380
381 qi = &ah->txq[q];
382 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
383 ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q);
384 return true;
385 }
386
387 ath_dbg(common, QUEUE, "Reset TX queue: %u\n", q);
388
389 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
390 if (chan && IS_CHAN_B(chan))
391 chanCwMin = INIT_CWMIN_11B;
392 else
393 chanCwMin = INIT_CWMIN;
394
395 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
396 } else
397 cwMin = qi->tqi_cwmin;
398
399 ENABLE_REGWRITE_BUFFER(ah);
400
401 REG_WRITE(ah, AR_DLCL_IFS(q),
402 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
403 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
404 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
405
406 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
407 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
408 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
409 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
410
411 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
412
413 if (AR_SREV_9340(ah) && !AR_SREV_9340_13_OR_LATER(ah))
414 REG_WRITE(ah, AR_DMISC(q),
415 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
416 else
417 REG_WRITE(ah, AR_DMISC(q),
418 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
419
420 if (qi->tqi_cbrPeriod) {
421 REG_WRITE(ah, AR_QCBRCFG(q),
422 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
423 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
424 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
425 (qi->tqi_cbrOverflowLimit ?
426 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
427 }
428 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
429 REG_WRITE(ah, AR_QRDYTIMECFG(q),
430 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
431 AR_Q_RDYTIMECFG_EN);
432 }
433
434 REG_WRITE(ah, AR_DCHNTIME(q),
435 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
436 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
437
438 if (qi->tqi_burstTime
439 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
440 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
441
442 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
443 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
444
445 REGWRITE_BUFFER_FLUSH(ah);
446
447 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
448 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
449
450 switch (qi->tqi_type) {
451 case ATH9K_TX_QUEUE_BEACON:
452 ENABLE_REGWRITE_BUFFER(ah);
453
454 REG_SET_BIT(ah, AR_QMISC(q),
455 AR_Q_MISC_FSP_DBA_GATED
456 | AR_Q_MISC_BEACON_USE
457 | AR_Q_MISC_CBR_INCR_DIS1);
458
459 REG_SET_BIT(ah, AR_DMISC(q),
460 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
461 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
462 | AR_D_MISC_BEACON_USE
463 | AR_D_MISC_POST_FR_BKOFF_DIS);
464
465 REGWRITE_BUFFER_FLUSH(ah);
466
467 /*
468 * cwmin and cwmax should be 0 for beacon queue
469 * but not for IBSS as we would create an imbalance
470 * on beaconing fairness for participating nodes.
471 */
472 if (AR_SREV_9300_20_OR_LATER(ah) &&
473 ah->opmode != NL80211_IFTYPE_ADHOC) {
474 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
475 | SM(0, AR_D_LCL_IFS_CWMAX)
476 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
477 }
478 break;
479 case ATH9K_TX_QUEUE_CAB:
480 ENABLE_REGWRITE_BUFFER(ah);
481
482 REG_SET_BIT(ah, AR_QMISC(q),
483 AR_Q_MISC_FSP_DBA_GATED
484 | AR_Q_MISC_CBR_INCR_DIS1
485 | AR_Q_MISC_CBR_INCR_DIS0);
486 value = (qi->tqi_readyTime -
487 (ah->config.sw_beacon_response_time -
488 ah->config.dma_beacon_response_time) -
489 ah->config.additional_swba_backoff) * 1024;
490 REG_WRITE(ah, AR_QRDYTIMECFG(q),
491 value | AR_Q_RDYTIMECFG_EN);
492 REG_SET_BIT(ah, AR_DMISC(q),
493 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
494 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
495
496 REGWRITE_BUFFER_FLUSH(ah);
497
498 break;
499 case ATH9K_TX_QUEUE_PSPOLL:
500 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
501 break;
502 case ATH9K_TX_QUEUE_UAPSD:
503 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
504 break;
505 default:
506 break;
507 }
508
509 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
510 REG_SET_BIT(ah, AR_DMISC(q),
511 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
512 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
513 AR_D_MISC_POST_FR_BKOFF_DIS);
514 }
515
516 if (AR_SREV_9300_20_OR_LATER(ah))
517 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
518
519 ath9k_hw_clear_queue_interrupts(ah, q);
520 if (qi->tqi_qflags & TXQ_FLAG_TXINT_ENABLE) {
521 ah->txok_interrupt_mask |= 1 << q;
522 ah->txerr_interrupt_mask |= 1 << q;
523 }
524 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
525 ah->txdesc_interrupt_mask |= 1 << q;
526 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
527 ah->txeol_interrupt_mask |= 1 << q;
528 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
529 ah->txurn_interrupt_mask |= 1 << q;
530 ath9k_hw_set_txq_interrupts(ah, qi);
531
532 return true;
533 }
534 EXPORT_SYMBOL(ath9k_hw_resettxqueue);
535
536 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
537 struct ath_rx_status *rs)
538 {
539 struct ar5416_desc ads;
540 struct ar5416_desc *adsp = AR5416DESC(ds);
541 u32 phyerr;
542
543 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
544 return -EINPROGRESS;
545
546 ads.u.rx = adsp->u.rx;
547
548 rs->rs_status = 0;
549 rs->rs_flags = 0;
550 rs->flag = 0;
551
552 rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
553 rs->rs_tstamp = ads.AR_RcvTimestamp;
554
555 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
556 rs->rs_rssi = ATH9K_RSSI_BAD;
557 rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
558 rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
559 rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
560 rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
561 rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
562 rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
563 } else {
564 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
565 rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
566 AR_RxRSSIAnt00);
567 rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
568 AR_RxRSSIAnt01);
569 rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
570 AR_RxRSSIAnt02);
571 rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
572 AR_RxRSSIAnt10);
573 rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
574 AR_RxRSSIAnt11);
575 rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
576 AR_RxRSSIAnt12);
577 }
578 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
579 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
580 else
581 rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
582
583 rs->rs_rate = MS(ads.ds_rxstatus0, AR_RxRate);
584 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
585
586 rs->rs_firstaggr = (ads.ds_rxstatus8 & AR_RxFirstAggr) ? 1 : 0;
587 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
588 rs->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
589 rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
590
591 /* directly mapped flags for ieee80211_rx_status */
592 rs->flag |=
593 (ads.ds_rxstatus3 & AR_GI) ? RX_FLAG_SHORT_GI : 0;
594 rs->flag |=
595 (ads.ds_rxstatus3 & AR_2040) ? RX_FLAG_40MHZ : 0;
596 if (AR_SREV_9280_20_OR_LATER(ah))
597 rs->flag |=
598 (ads.ds_rxstatus3 & AR_STBC) ?
599 /* we can only Nss=1 STBC */
600 (1 << RX_FLAG_STBC_SHIFT) : 0;
601
602 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
603 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
604 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
605 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
606 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
607 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
608
609 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
610 /*
611 * Treat these errors as mutually exclusive to avoid spurious
612 * extra error reports from the hardware. If a CRC error is
613 * reported, then decryption and MIC errors are irrelevant,
614 * the frame is going to be dropped either way
615 */
616 if (ads.ds_rxstatus8 & AR_PHYErr) {
617 rs->rs_status |= ATH9K_RXERR_PHY;
618 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
619 rs->rs_phyerr = phyerr;
620 } else if (ads.ds_rxstatus8 & AR_CRCErr)
621 rs->rs_status |= ATH9K_RXERR_CRC;
622 else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
623 rs->rs_status |= ATH9K_RXERR_DECRYPT;
624 else if (ads.ds_rxstatus8 & AR_MichaelErr)
625 rs->rs_status |= ATH9K_RXERR_MIC;
626 } else {
627 if (ads.ds_rxstatus8 &
628 (AR_CRCErr | AR_PHYErr | AR_DecryptCRCErr | AR_MichaelErr))
629 rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC;
630
631 /* Only up to MCS16 supported, everything above is invalid */
632 if (rs->rs_rate >= 0x90)
633 rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC;
634 }
635
636 if (ads.ds_rxstatus8 & AR_KeyMiss)
637 rs->rs_status |= ATH9K_RXERR_KEYMISS;
638
639 return 0;
640 }
641 EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
642
643 /*
644 * This can stop or re-enables RX.
645 *
646 * If bool is set this will kill any frame which is currently being
647 * transferred between the MAC and baseband and also prevent any new
648 * frames from getting started.
649 */
650 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
651 {
652 u32 reg;
653
654 if (set) {
655 REG_SET_BIT(ah, AR_DIAG_SW,
656 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
657
658 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
659 0, AH_WAIT_TIMEOUT)) {
660 REG_CLR_BIT(ah, AR_DIAG_SW,
661 (AR_DIAG_RX_DIS |
662 AR_DIAG_RX_ABORT));
663
664 reg = REG_READ(ah, AR_OBS_BUS_1);
665 ath_err(ath9k_hw_common(ah),
666 "RX failed to go idle in 10 ms RXSM=0x%x\n",
667 reg);
668
669 return false;
670 }
671 } else {
672 REG_CLR_BIT(ah, AR_DIAG_SW,
673 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
674 }
675
676 return true;
677 }
678 EXPORT_SYMBOL(ath9k_hw_setrxabort);
679
680 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
681 {
682 REG_WRITE(ah, AR_RXDP, rxdp);
683 }
684 EXPORT_SYMBOL(ath9k_hw_putrxbuf);
685
686 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
687 {
688 ath9k_enable_mib_counters(ah);
689
690 ath9k_ani_reset(ah, is_scanning);
691
692 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
693 }
694 EXPORT_SYMBOL(ath9k_hw_startpcureceive);
695
696 void ath9k_hw_abortpcurecv(struct ath_hw *ah)
697 {
698 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
699
700 ath9k_hw_disable_mib_counters(ah);
701 }
702 EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
703
704 bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset)
705 {
706 #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
707 struct ath_common *common = ath9k_hw_common(ah);
708 u32 mac_status, last_mac_status = 0;
709 int i;
710
711 /* Enable access to the DMA observation bus */
712 REG_WRITE(ah, AR_MACMISC,
713 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
714 (AR_MACMISC_MISC_OBS_BUS_1 <<
715 AR_MACMISC_MISC_OBS_BUS_MSB_S)));
716
717 REG_WRITE(ah, AR_CR, AR_CR_RXD);
718
719 /* Wait for rx enable bit to go low */
720 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
721 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
722 break;
723
724 if (!AR_SREV_9300_20_OR_LATER(ah)) {
725 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
726 if (mac_status == 0x1c0 && mac_status == last_mac_status) {
727 *reset = true;
728 break;
729 }
730
731 last_mac_status = mac_status;
732 }
733
734 udelay(AH_TIME_QUANTUM);
735 }
736
737 if (i == 0) {
738 ath_err(common,
739 "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
740 AH_RX_STOP_DMA_TIMEOUT / 1000,
741 REG_READ(ah, AR_CR),
742 REG_READ(ah, AR_DIAG_SW),
743 REG_READ(ah, AR_DMADBG_7));
744 return false;
745 } else {
746 return true;
747 }
748
749 #undef AH_RX_STOP_DMA_TIMEOUT
750 }
751 EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
752
753 int ath9k_hw_beaconq_setup(struct ath_hw *ah)
754 {
755 struct ath9k_tx_queue_info qi;
756
757 memset(&qi, 0, sizeof(qi));
758 qi.tqi_aifs = 1;
759 qi.tqi_cwmin = 0;
760 qi.tqi_cwmax = 0;
761
762 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
763 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
764
765 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
766 }
767 EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
768
769 bool ath9k_hw_intrpend(struct ath_hw *ah)
770 {
771 u32 host_isr;
772
773 if (AR_SREV_9100(ah))
774 return true;
775
776 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
777
778 if (((host_isr & AR_INTR_MAC_IRQ) ||
779 (host_isr & AR_INTR_ASYNC_MASK_MCI)) &&
780 (host_isr != AR_INTR_SPURIOUS))
781 return true;
782
783 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
784 if ((host_isr & AR_INTR_SYNC_DEFAULT)
785 && (host_isr != AR_INTR_SPURIOUS))
786 return true;
787
788 return false;
789 }
790 EXPORT_SYMBOL(ath9k_hw_intrpend);
791
792 void ath9k_hw_kill_interrupts(struct ath_hw *ah)
793 {
794 struct ath_common *common = ath9k_hw_common(ah);
795
796 ath_dbg(common, INTERRUPT, "disable IER\n");
797 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
798 (void) REG_READ(ah, AR_IER);
799 if (!AR_SREV_9100(ah)) {
800 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
801 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
802
803 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
804 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
805 }
806 }
807 EXPORT_SYMBOL(ath9k_hw_kill_interrupts);
808
809 void ath9k_hw_disable_interrupts(struct ath_hw *ah)
810 {
811 if (!(ah->imask & ATH9K_INT_GLOBAL))
812 atomic_set(&ah->intr_ref_cnt, -1);
813 else
814 atomic_dec(&ah->intr_ref_cnt);
815
816 ath9k_hw_kill_interrupts(ah);
817 }
818 EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
819
820 void ath9k_hw_enable_interrupts(struct ath_hw *ah)
821 {
822 struct ath_common *common = ath9k_hw_common(ah);
823 u32 sync_default = AR_INTR_SYNC_DEFAULT;
824 u32 async_mask;
825
826 if (!(ah->imask & ATH9K_INT_GLOBAL))
827 return;
828
829 if (!atomic_inc_and_test(&ah->intr_ref_cnt)) {
830 ath_dbg(common, INTERRUPT, "Do not enable IER ref count %d\n",
831 atomic_read(&ah->intr_ref_cnt));
832 return;
833 }
834
835 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
836 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
837
838 async_mask = AR_INTR_MAC_IRQ;
839
840 if (ah->imask & ATH9K_INT_MCI)
841 async_mask |= AR_INTR_ASYNC_MASK_MCI;
842
843 ath_dbg(common, INTERRUPT, "enable IER\n");
844 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
845 if (!AR_SREV_9100(ah)) {
846 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask);
847 REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask);
848
849 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
850 REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);
851 }
852 ath_dbg(common, INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
853 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
854 }
855 EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
856
857 void ath9k_hw_set_interrupts(struct ath_hw *ah)
858 {
859 enum ath9k_int ints = ah->imask;
860 u32 mask, mask2;
861 struct ath9k_hw_capabilities *pCap = &ah->caps;
862 struct ath_common *common = ath9k_hw_common(ah);
863
864 if (!(ints & ATH9K_INT_GLOBAL))
865 ath9k_hw_disable_interrupts(ah);
866
867 ath_dbg(common, INTERRUPT, "New interrupt mask 0x%x\n", ints);
868
869 mask = ints & ATH9K_INT_COMMON;
870 mask2 = 0;
871
872 if (ints & ATH9K_INT_TX) {
873 if (ah->config.tx_intr_mitigation)
874 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
875 else {
876 if (ah->txok_interrupt_mask)
877 mask |= AR_IMR_TXOK;
878 if (ah->txdesc_interrupt_mask)
879 mask |= AR_IMR_TXDESC;
880 }
881 if (ah->txerr_interrupt_mask)
882 mask |= AR_IMR_TXERR;
883 if (ah->txeol_interrupt_mask)
884 mask |= AR_IMR_TXEOL;
885 }
886 if (ints & ATH9K_INT_RX) {
887 if (AR_SREV_9300_20_OR_LATER(ah)) {
888 mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
889 if (ah->config.rx_intr_mitigation) {
890 mask &= ~AR_IMR_RXOK_LP;
891 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
892 } else {
893 mask |= AR_IMR_RXOK_LP;
894 }
895 } else {
896 if (ah->config.rx_intr_mitigation)
897 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
898 else
899 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
900 }
901 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
902 mask |= AR_IMR_GENTMR;
903 }
904
905 if (ints & ATH9K_INT_GENTIMER)
906 mask |= AR_IMR_GENTMR;
907
908 if (ints & (ATH9K_INT_BMISC)) {
909 mask |= AR_IMR_BCNMISC;
910 if (ints & ATH9K_INT_TIM)
911 mask2 |= AR_IMR_S2_TIM;
912 if (ints & ATH9K_INT_DTIM)
913 mask2 |= AR_IMR_S2_DTIM;
914 if (ints & ATH9K_INT_DTIMSYNC)
915 mask2 |= AR_IMR_S2_DTIMSYNC;
916 if (ints & ATH9K_INT_CABEND)
917 mask2 |= AR_IMR_S2_CABEND;
918 if (ints & ATH9K_INT_TSFOOR)
919 mask2 |= AR_IMR_S2_TSFOOR;
920 }
921
922 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
923 mask |= AR_IMR_BCNMISC;
924 if (ints & ATH9K_INT_GTT)
925 mask2 |= AR_IMR_S2_GTT;
926 if (ints & ATH9K_INT_CST)
927 mask2 |= AR_IMR_S2_CST;
928 }
929
930 ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask);
931 REG_WRITE(ah, AR_IMR, mask);
932 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
933 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
934 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
935 ah->imrs2_reg |= mask2;
936 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
937
938 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
939 if (ints & ATH9K_INT_TIM_TIMER)
940 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
941 else
942 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
943 }
944
945 return;
946 }
947 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
Linux with added FPC-III support