2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #define AR_CR_RXE (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004)
24 #define AR_CR_RXD 0x00000020
25 #define AR_CR_SWI 0x00000040
27 #define AR_RXDP 0x000C
30 #define AR_CFG_SWTD 0x00000001
31 #define AR_CFG_SWTB 0x00000002
32 #define AR_CFG_SWRD 0x00000004
33 #define AR_CFG_SWRB 0x00000008
34 #define AR_CFG_SWRG 0x00000010
35 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020
36 #define AR_CFG_PHOK 0x00000100
37 #define AR_CFG_CLK_GATE_DIS 0x00000400
38 #define AR_CFG_EEBS 0x00000200
39 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000
40 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17
42 #define AR_RXBP_THRESH 0x0018
43 #define AR_RXBP_THRESH_HP 0x0000000f
44 #define AR_RXBP_THRESH_HP_S 0
45 #define AR_RXBP_THRESH_LP 0x00003f00
46 #define AR_RXBP_THRESH_LP_S 8
48 #define AR_MIRT 0x0020
49 #define AR_MIRT_VAL 0x0000ffff
50 #define AR_MIRT_VAL_S 16
53 #define AR_IER_ENABLE 0x00000001
54 #define AR_IER_DISABLE 0x00000000
56 #define AR_TIMT 0x0028
57 #define AR_TIMT_LAST 0x0000ffff
58 #define AR_TIMT_LAST_S 0
59 #define AR_TIMT_FIRST 0xffff0000
60 #define AR_TIMT_FIRST_S 16
62 #define AR_RIMT 0x002C
63 #define AR_RIMT_LAST 0x0000ffff
64 #define AR_RIMT_LAST_S 0
65 #define AR_RIMT_FIRST 0xffff0000
66 #define AR_RIMT_FIRST_S 16
68 #define AR_DMASIZE_4B 0x00000000
69 #define AR_DMASIZE_8B 0x00000001
70 #define AR_DMASIZE_16B 0x00000002
71 #define AR_DMASIZE_32B 0x00000003
72 #define AR_DMASIZE_64B 0x00000004
73 #define AR_DMASIZE_128B 0x00000005
74 #define AR_DMASIZE_256B 0x00000006
75 #define AR_DMASIZE_512B 0x00000007
77 #define AR_TXCFG 0x0030
78 #define AR_TXCFG_DMASZ_MASK 0x00000007
79 #define AR_TXCFG_DMASZ_4B 0
80 #define AR_TXCFG_DMASZ_8B 1
81 #define AR_TXCFG_DMASZ_16B 2
82 #define AR_TXCFG_DMASZ_32B 3
83 #define AR_TXCFG_DMASZ_64B 4
84 #define AR_TXCFG_DMASZ_128B 5
85 #define AR_TXCFG_DMASZ_256B 6
86 #define AR_TXCFG_DMASZ_512B 7
87 #define AR_FTRIG 0x000003F0
89 #define AR_FTRIG_IMMED 0x00000000
90 #define AR_FTRIG_64B 0x00000010
91 #define AR_FTRIG_128B 0x00000020
92 #define AR_FTRIG_192B 0x00000030
93 #define AR_FTRIG_256B 0x00000040
94 #define AR_FTRIG_512B 0x00000080
95 #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800
97 #define AR_RXCFG 0x0034
98 #define AR_RXCFG_CHIRP 0x00000008
99 #define AR_RXCFG_ZLFDMA 0x00000010
100 #define AR_RXCFG_DMASZ_MASK 0x00000007
101 #define AR_RXCFG_DMASZ_4B 0
102 #define AR_RXCFG_DMASZ_8B 1
103 #define AR_RXCFG_DMASZ_16B 2
104 #define AR_RXCFG_DMASZ_32B 3
105 #define AR_RXCFG_DMASZ_64B 4
106 #define AR_RXCFG_DMASZ_128B 5
107 #define AR_RXCFG_DMASZ_256B 6
108 #define AR_RXCFG_DMASZ_512B 7
110 #define AR_TOPS 0x0044
111 #define AR_TOPS_MASK 0x0000FFFF
113 #define AR_RXNPTO 0x0048
114 #define AR_RXNPTO_MASK 0x000003FF
116 #define AR_TXNPTO 0x004C
117 #define AR_TXNPTO_MASK 0x000003FF
118 #define AR_TXNPTO_QCU_MASK 0x000FFC00
120 #define AR_RPGTO 0x0050
121 #define AR_RPGTO_MASK 0x000003FF
123 #define AR_RPCNT 0x0054
124 #define AR_RPCNT_MASK 0x0000001F
126 #define AR_MACMISC 0x0058
127 #define AR_MACMISC_PCI_EXT_FORCE 0x00000010
128 #define AR_MACMISC_DMA_OBS 0x000001E0
129 #define AR_MACMISC_DMA_OBS_S 5
130 #define AR_MACMISC_DMA_OBS_LINE_0 0
131 #define AR_MACMISC_DMA_OBS_LINE_1 1
132 #define AR_MACMISC_DMA_OBS_LINE_2 2
133 #define AR_MACMISC_DMA_OBS_LINE_3 3
134 #define AR_MACMISC_DMA_OBS_LINE_4 4
135 #define AR_MACMISC_DMA_OBS_LINE_5 5
136 #define AR_MACMISC_DMA_OBS_LINE_6 6
137 #define AR_MACMISC_DMA_OBS_LINE_7 7
138 #define AR_MACMISC_DMA_OBS_LINE_8 8
139 #define AR_MACMISC_MISC_OBS 0x00000E00
140 #define AR_MACMISC_MISC_OBS_S 9
141 #define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000
142 #define AR_MACMISC_MISC_OBS_BUS_LSB_S 12
143 #define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000
144 #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15
145 #define AR_MACMISC_MISC_OBS_BUS_1 1
147 #define AR_DATABUF_SIZE 0x0060
148 #define AR_DATABUF_SIZE_MASK 0x00000FFF
150 #define AR_GTXTO 0x0064
151 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF
152 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000
153 #define AR_GTXTO_TIMEOUT_LIMIT_S 16
155 #define AR_GTTM 0x0068
156 #define AR_GTTM_USEC 0x00000001
157 #define AR_GTTM_IGNORE_IDLE 0x00000002
158 #define AR_GTTM_RESET_IDLE 0x00000004
159 #define AR_GTTM_CST_USEC 0x00000008
161 #define AR_CST 0x006C
162 #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF
163 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000
164 #define AR_CST_TIMEOUT_LIMIT_S 16
166 #define AR_HP_RXDP 0x0074
167 #define AR_LP_RXDP 0x0078
169 #define AR_ISR 0x0080
170 #define AR_ISR_RXOK 0x00000001
171 #define AR_ISR_RXDESC 0x00000002
172 #define AR_ISR_HP_RXOK 0x00000001
173 #define AR_ISR_LP_RXOK 0x00000002
174 #define AR_ISR_RXERR 0x00000004
175 #define AR_ISR_RXNOPKT 0x00000008
176 #define AR_ISR_RXEOL 0x00000010
177 #define AR_ISR_RXORN 0x00000020
178 #define AR_ISR_TXOK 0x00000040
179 #define AR_ISR_TXDESC 0x00000080
180 #define AR_ISR_TXERR 0x00000100
181 #define AR_ISR_TXNOPKT 0x00000200
182 #define AR_ISR_TXEOL 0x00000400
183 #define AR_ISR_TXURN 0x00000800
184 #define AR_ISR_MIB 0x00001000
185 #define AR_ISR_SWI 0x00002000
186 #define AR_ISR_RXPHY 0x00004000
187 #define AR_ISR_RXKCM 0x00008000
188 #define AR_ISR_SWBA 0x00010000
189 #define AR_ISR_BRSSI 0x00020000
190 #define AR_ISR_BMISS 0x00040000
191 #define AR_ISR_BNR 0x00100000
192 #define AR_ISR_RXCHIRP 0x00200000
193 #define AR_ISR_BCNMISC 0x00800000
194 #define AR_ISR_TIM 0x00800000
195 #define AR_ISR_QCBROVF 0x02000000
196 #define AR_ISR_QCBRURN 0x04000000
197 #define AR_ISR_QTRIG 0x08000000
198 #define AR_ISR_GENTMR 0x10000000
200 #define AR_ISR_TXMINTR 0x00080000
201 #define AR_ISR_RXMINTR 0x01000000
202 #define AR_ISR_TXINTM 0x40000000
203 #define AR_ISR_RXINTM 0x80000000
205 #define AR_ISR_S0 0x0084
206 #define AR_ISR_S0_QCU_TXOK 0x000003FF
207 #define AR_ISR_S0_QCU_TXOK_S 0
208 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000
209 #define AR_ISR_S0_QCU_TXDESC_S 16
211 #define AR_ISR_S1 0x0088
212 #define AR_ISR_S1_QCU_TXERR 0x000003FF
213 #define AR_ISR_S1_QCU_TXERR_S 0
214 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000
215 #define AR_ISR_S1_QCU_TXEOL_S 16
217 #define AR_ISR_S2 0x008c
218 #define AR_ISR_S2_QCU_TXURN 0x000003FF
219 #define AR_ISR_S2_BB_WATCHDOG 0x00010000
220 #define AR_ISR_S2_CST 0x00400000
221 #define AR_ISR_S2_GTT 0x00800000
222 #define AR_ISR_S2_TIM 0x01000000
223 #define AR_ISR_S2_CABEND 0x02000000
224 #define AR_ISR_S2_DTIMSYNC 0x04000000
225 #define AR_ISR_S2_BCNTO 0x08000000
226 #define AR_ISR_S2_CABTO 0x10000000
227 #define AR_ISR_S2_DTIM 0x20000000
228 #define AR_ISR_S2_TSFOOR 0x40000000
229 #define AR_ISR_S2_TBTT_TIME 0x80000000
231 #define AR_ISR_S3 0x0090
232 #define AR_ISR_S3_QCU_QCBROVF 0x000003FF
233 #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000
235 #define AR_ISR_S4 0x0094
236 #define AR_ISR_S4_QCU_QTRIG 0x000003FF
237 #define AR_ISR_S4_RESV0 0xFFFFFC00
239 #define AR_ISR_S5 0x0098
240 #define AR_ISR_S5_TIMER_TRIG 0x000000FF
241 #define AR_ISR_S5_TIMER_THRESH 0x0007FE00
242 #define AR_ISR_S5_TIM_TIMER 0x00000010
243 #define AR_ISR_S5_DTIM_TIMER 0x00000020
244 #define AR_IMR_S5 0x00b8
245 #define AR_IMR_S5_TIM_TIMER 0x00000010
246 #define AR_IMR_S5_DTIM_TIMER 0x00000020
247 #define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80
248 #define AR_ISR_S5_GENTIMER_TRIG_S 0
249 #define AR_ISR_S5_GENTIMER_THRESH 0xFF800000
250 #define AR_ISR_S5_GENTIMER_THRESH_S 16
251 #define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80
252 #define AR_IMR_S5_GENTIMER_TRIG_S 0
253 #define AR_IMR_S5_GENTIMER_THRESH 0xFF800000
254 #define AR_IMR_S5_GENTIMER_THRESH_S 16
256 #define AR_IMR 0x00a0
257 #define AR_IMR_RXOK 0x00000001
258 #define AR_IMR_RXDESC 0x00000002
259 #define AR_IMR_RXOK_HP 0x00000001
260 #define AR_IMR_RXOK_LP 0x00000002
261 #define AR_IMR_RXERR 0x00000004
262 #define AR_IMR_RXNOPKT 0x00000008
263 #define AR_IMR_RXEOL 0x00000010
264 #define AR_IMR_RXORN 0x00000020
265 #define AR_IMR_TXOK 0x00000040
266 #define AR_IMR_TXDESC 0x00000080
267 #define AR_IMR_TXERR 0x00000100
268 #define AR_IMR_TXNOPKT 0x00000200
269 #define AR_IMR_TXEOL 0x00000400
270 #define AR_IMR_TXURN 0x00000800
271 #define AR_IMR_MIB 0x00001000
272 #define AR_IMR_SWI 0x00002000
273 #define AR_IMR_RXPHY 0x00004000
274 #define AR_IMR_RXKCM 0x00008000
275 #define AR_IMR_SWBA 0x00010000
276 #define AR_IMR_BRSSI 0x00020000
277 #define AR_IMR_BMISS 0x00040000
278 #define AR_IMR_BNR 0x00100000
279 #define AR_IMR_RXCHIRP 0x00200000
280 #define AR_IMR_BCNMISC 0x00800000
281 #define AR_IMR_TIM 0x00800000
282 #define AR_IMR_QCBROVF 0x02000000
283 #define AR_IMR_QCBRURN 0x04000000
284 #define AR_IMR_QTRIG 0x08000000
285 #define AR_IMR_GENTMR 0x10000000
287 #define AR_IMR_TXMINTR 0x00080000
288 #define AR_IMR_RXMINTR 0x01000000
289 #define AR_IMR_TXINTM 0x40000000
290 #define AR_IMR_RXINTM 0x80000000
292 #define AR_IMR_S0 0x00a4
293 #define AR_IMR_S0_QCU_TXOK 0x000003FF
294 #define AR_IMR_S0_QCU_TXOK_S 0
295 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000
296 #define AR_IMR_S0_QCU_TXDESC_S 16
298 #define AR_IMR_S1 0x00a8
299 #define AR_IMR_S1_QCU_TXERR 0x000003FF
300 #define AR_IMR_S1_QCU_TXERR_S 0
301 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000
302 #define AR_IMR_S1_QCU_TXEOL_S 16
304 #define AR_IMR_S2 0x00ac
305 #define AR_IMR_S2_QCU_TXURN 0x000003FF
306 #define AR_IMR_S2_QCU_TXURN_S 0
307 #define AR_IMR_S2_CST 0x00400000
308 #define AR_IMR_S2_GTT 0x00800000
309 #define AR_IMR_S2_TIM 0x01000000
310 #define AR_IMR_S2_CABEND 0x02000000
311 #define AR_IMR_S2_DTIMSYNC 0x04000000
312 #define AR_IMR_S2_BCNTO 0x08000000
313 #define AR_IMR_S2_CABTO 0x10000000
314 #define AR_IMR_S2_DTIM 0x20000000
315 #define AR_IMR_S2_TSFOOR 0x40000000
317 #define AR_IMR_S3 0x00b0
318 #define AR_IMR_S3_QCU_QCBROVF 0x000003FF
319 #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000
320 #define AR_IMR_S3_QCU_QCBRURN_S 16
322 #define AR_IMR_S4 0x00b4
323 #define AR_IMR_S4_QCU_QTRIG 0x000003FF
324 #define AR_IMR_S4_RESV0 0xFFFFFC00
326 #define AR_IMR_S5 0x00b8
327 #define AR_IMR_S5_TIMER_TRIG 0x000000FF
328 #define AR_IMR_S5_TIMER_THRESH 0x0000FF00
331 #define AR_ISR_RAC 0x00c0
332 #define AR_ISR_S0_S 0x00c4
333 #define AR_ISR_S0_QCU_TXOK 0x000003FF
334 #define AR_ISR_S0_QCU_TXOK_S 0
335 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000
336 #define AR_ISR_S0_QCU_TXDESC_S 16
338 #define AR_ISR_S1_S 0x00c8
339 #define AR_ISR_S1_QCU_TXERR 0x000003FF
340 #define AR_ISR_S1_QCU_TXERR_S 0
341 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000
342 #define AR_ISR_S1_QCU_TXEOL_S 16
344 #define AR_ISR_S2_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d0 : 0x00cc)
345 #define AR_ISR_S3_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d4 : 0x00d0)
346 #define AR_ISR_S4_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d8 : 0x00d4)
347 #define AR_ISR_S5_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00dc : 0x00d8)
348 #define AR_DMADBG_0 0x00e0
349 #define AR_DMADBG_1 0x00e4
350 #define AR_DMADBG_2 0x00e8
351 #define AR_DMADBG_3 0x00ec
352 #define AR_DMADBG_4 0x00f0
353 #define AR_DMADBG_5 0x00f4
354 #define AR_DMADBG_6 0x00f8
355 #define AR_DMADBG_7 0x00fc
357 #define AR_NUM_QCU 10
358 #define AR_QCU_0 0x0001
359 #define AR_QCU_1 0x0002
360 #define AR_QCU_2 0x0004
361 #define AR_QCU_3 0x0008
362 #define AR_QCU_4 0x0010
363 #define AR_QCU_5 0x0020
364 #define AR_QCU_6 0x0040
365 #define AR_QCU_7 0x0080
366 #define AR_QCU_8 0x0100
367 #define AR_QCU_9 0x0200
369 #define AR_Q0_TXDP 0x0800
370 #define AR_Q1_TXDP 0x0804
371 #define AR_Q2_TXDP 0x0808
372 #define AR_Q3_TXDP 0x080c
373 #define AR_Q4_TXDP 0x0810
374 #define AR_Q5_TXDP 0x0814
375 #define AR_Q6_TXDP 0x0818
376 #define AR_Q7_TXDP 0x081c
377 #define AR_Q8_TXDP 0x0820
378 #define AR_Q9_TXDP 0x0824
379 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2))
381 #define AR_Q_STATUS_RING_START 0x830
382 #define AR_Q_STATUS_RING_END 0x834
384 #define AR_Q_TXE 0x0840
385 #define AR_Q_TXE_M 0x000003FF
387 #define AR_Q_TXD 0x0880
388 #define AR_Q_TXD_M 0x000003FF
390 #define AR_Q0_CBRCFG 0x08c0
391 #define AR_Q1_CBRCFG 0x08c4
392 #define AR_Q2_CBRCFG 0x08c8
393 #define AR_Q3_CBRCFG 0x08cc
394 #define AR_Q4_CBRCFG 0x08d0
395 #define AR_Q5_CBRCFG 0x08d4
396 #define AR_Q6_CBRCFG 0x08d8
397 #define AR_Q7_CBRCFG 0x08dc
398 #define AR_Q8_CBRCFG 0x08e0
399 #define AR_Q9_CBRCFG 0x08e4
400 #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2))
401 #define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF
402 #define AR_Q_CBRCFG_INTERVAL_S 0
403 #define AR_Q_CBRCFG_OVF_THRESH 0xFF000000
404 #define AR_Q_CBRCFG_OVF_THRESH_S 24
406 #define AR_Q0_RDYTIMECFG 0x0900
407 #define AR_Q1_RDYTIMECFG 0x0904
408 #define AR_Q2_RDYTIMECFG 0x0908
409 #define AR_Q3_RDYTIMECFG 0x090c
410 #define AR_Q4_RDYTIMECFG 0x0910
411 #define AR_Q5_RDYTIMECFG 0x0914
412 #define AR_Q6_RDYTIMECFG 0x0918
413 #define AR_Q7_RDYTIMECFG 0x091c
414 #define AR_Q8_RDYTIMECFG 0x0920
415 #define AR_Q9_RDYTIMECFG 0x0924
416 #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2))
417 #define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF
418 #define AR_Q_RDYTIMECFG_DURATION_S 0
419 #define AR_Q_RDYTIMECFG_EN 0x01000000
421 #define AR_Q_ONESHOTARM_SC 0x0940
422 #define AR_Q_ONESHOTARM_SC_M 0x000003FF
423 #define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00
425 #define AR_Q_ONESHOTARM_CC 0x0980
426 #define AR_Q_ONESHOTARM_CC_M 0x000003FF
427 #define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00
429 #define AR_Q0_MISC 0x09c0
430 #define AR_Q1_MISC 0x09c4
431 #define AR_Q2_MISC 0x09c8
432 #define AR_Q3_MISC 0x09cc
433 #define AR_Q4_MISC 0x09d0
434 #define AR_Q5_MISC 0x09d4
435 #define AR_Q6_MISC 0x09d8
436 #define AR_Q7_MISC 0x09dc
437 #define AR_Q8_MISC 0x09e0
438 #define AR_Q9_MISC 0x09e4
439 #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2))
440 #define AR_Q_MISC_FSP 0x0000000F
441 #define AR_Q_MISC_FSP_ASAP 0
442 #define AR_Q_MISC_FSP_CBR 1
443 #define AR_Q_MISC_FSP_DBA_GATED 2
444 #define AR_Q_MISC_FSP_TIM_GATED 3
445 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4
446 #define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5
447 #define AR_Q_MISC_ONE_SHOT_EN 0x00000010
448 #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020
449 #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040
450 #define AR_Q_MISC_BEACON_USE 0x00000080
451 #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100
452 #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200
453 #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400
454 #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800
455 #define AR_Q_MISC_RESV0 0xFFFFF000
457 #define AR_Q0_STS 0x0a00
458 #define AR_Q1_STS 0x0a04
459 #define AR_Q2_STS 0x0a08
460 #define AR_Q3_STS 0x0a0c
461 #define AR_Q4_STS 0x0a10
462 #define AR_Q5_STS 0x0a14
463 #define AR_Q6_STS 0x0a18
464 #define AR_Q7_STS 0x0a1c
465 #define AR_Q8_STS 0x0a20
466 #define AR_Q9_STS 0x0a24
467 #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2))
468 #define AR_Q_STS_PEND_FR_CNT 0x00000003
469 #define AR_Q_STS_RESV0 0x000000FC
470 #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00
471 #define AR_Q_STS_RESV1 0xFFFF0000
473 #define AR_Q_RDYTIMESHDN 0x0a40
474 #define AR_Q_RDYTIMESHDN_M 0x000003FF
476 /* MAC Descriptor CRC check */
477 #define AR_Q_DESC_CRCCHK 0xa44
478 /* Enable CRC check on the descriptor fetched from host */
479 #define AR_Q_DESC_CRCCHK_EN 1
481 #define AR_NUM_DCU 10
482 #define AR_DCU_0 0x0001
483 #define AR_DCU_1 0x0002
484 #define AR_DCU_2 0x0004
485 #define AR_DCU_3 0x0008
486 #define AR_DCU_4 0x0010
487 #define AR_DCU_5 0x0020
488 #define AR_DCU_6 0x0040
489 #define AR_DCU_7 0x0080
490 #define AR_DCU_8 0x0100
491 #define AR_DCU_9 0x0200
493 #define AR_D0_QCUMASK 0x1000
494 #define AR_D1_QCUMASK 0x1004
495 #define AR_D2_QCUMASK 0x1008
496 #define AR_D3_QCUMASK 0x100c
497 #define AR_D4_QCUMASK 0x1010
498 #define AR_D5_QCUMASK 0x1014
499 #define AR_D6_QCUMASK 0x1018
500 #define AR_D7_QCUMASK 0x101c
501 #define AR_D8_QCUMASK 0x1020
502 #define AR_D9_QCUMASK 0x1024
503 #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2))
504 #define AR_D_QCUMASK 0x000003FF
505 #define AR_D_QCUMASK_RESV0 0xFFFFFC00
507 #define AR_D_TXBLK_CMD 0x1038
508 #define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i))
510 #define AR_D0_LCL_IFS 0x1040
511 #define AR_D1_LCL_IFS 0x1044
512 #define AR_D2_LCL_IFS 0x1048
513 #define AR_D3_LCL_IFS 0x104c
514 #define AR_D4_LCL_IFS 0x1050
515 #define AR_D5_LCL_IFS 0x1054
516 #define AR_D6_LCL_IFS 0x1058
517 #define AR_D7_LCL_IFS 0x105c
518 #define AR_D8_LCL_IFS 0x1060
519 #define AR_D9_LCL_IFS 0x1064
520 #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2))
521 #define AR_D_LCL_IFS_CWMIN 0x000003FF
522 #define AR_D_LCL_IFS_CWMIN_S 0
523 #define AR_D_LCL_IFS_CWMAX 0x000FFC00
524 #define AR_D_LCL_IFS_CWMAX_S 10
525 #define AR_D_LCL_IFS_AIFS 0x0FF00000
526 #define AR_D_LCL_IFS_AIFS_S 20
528 #define AR_D_LCL_IFS_RESV0 0xF0000000
530 #define AR_D0_RETRY_LIMIT 0x1080
531 #define AR_D1_RETRY_LIMIT 0x1084
532 #define AR_D2_RETRY_LIMIT 0x1088
533 #define AR_D3_RETRY_LIMIT 0x108c
534 #define AR_D4_RETRY_LIMIT 0x1090
535 #define AR_D5_RETRY_LIMIT 0x1094
536 #define AR_D6_RETRY_LIMIT 0x1098
537 #define AR_D7_RETRY_LIMIT 0x109c
538 #define AR_D8_RETRY_LIMIT 0x10a0
539 #define AR_D9_RETRY_LIMIT 0x10a4
540 #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2))
541 #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F
542 #define AR_D_RETRY_LIMIT_FR_SH_S 0
543 #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00
544 #define AR_D_RETRY_LIMIT_STA_SH_S 8
545 #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000
546 #define AR_D_RETRY_LIMIT_STA_LG_S 14
547 #define AR_D_RETRY_LIMIT_RESV0 0xFFF00000
549 #define AR_D0_CHNTIME 0x10c0
550 #define AR_D1_CHNTIME 0x10c4
551 #define AR_D2_CHNTIME 0x10c8
552 #define AR_D3_CHNTIME 0x10cc
553 #define AR_D4_CHNTIME 0x10d0
554 #define AR_D5_CHNTIME 0x10d4
555 #define AR_D6_CHNTIME 0x10d8
556 #define AR_D7_CHNTIME 0x10dc
557 #define AR_D8_CHNTIME 0x10e0
558 #define AR_D9_CHNTIME 0x10e4
559 #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2))
560 #define AR_D_CHNTIME_DUR 0x000FFFFF
561 #define AR_D_CHNTIME_DUR_S 0
562 #define AR_D_CHNTIME_EN 0x00100000
563 #define AR_D_CHNTIME_RESV0 0xFFE00000
565 #define AR_D0_MISC 0x1100
566 #define AR_D1_MISC 0x1104
567 #define AR_D2_MISC 0x1108
568 #define AR_D3_MISC 0x110c
569 #define AR_D4_MISC 0x1110
570 #define AR_D5_MISC 0x1114
571 #define AR_D6_MISC 0x1118
572 #define AR_D7_MISC 0x111c
573 #define AR_D8_MISC 0x1120
574 #define AR_D9_MISC 0x1124
575 #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2))
576 #define AR_D_MISC_BKOFF_THRESH 0x0000003F
577 #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040
578 #define AR_D_MISC_CW_RESET_EN 0x00000080
579 #define AR_D_MISC_FRAG_WAIT_EN 0x00000100
580 #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200
581 #define AR_D_MISC_CW_BKOFF_EN 0x00001000
582 #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000
583 #define AR_D_MISC_VIR_COL_HANDLING_S 14
584 #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0
585 #define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1
586 #define AR_D_MISC_BEACON_USE 0x00010000
587 #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000
588 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17
589 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0
590 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1
591 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2
592 #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000
593 #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000
594 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000
595 #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000
596 #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000
597 #define AR_D_MISC_RESV0 0xFF000000
599 #define AR_D_SEQNUM 0x1140
601 #define AR_D_GBL_IFS_SIFS 0x1030
602 #define AR_D_GBL_IFS_SIFS_M 0x0000FFFF
603 #define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF
605 #define AR_D_TXBLK_BASE 0x1038
606 #define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF
607 #define AR_D_TXBLK_WRITE_BITMASK_S 0
608 #define AR_D_TXBLK_WRITE_SLICE 0x000F0000
609 #define AR_D_TXBLK_WRITE_SLICE_S 16
610 #define AR_D_TXBLK_WRITE_DCU 0x00F00000
611 #define AR_D_TXBLK_WRITE_DCU_S 20
612 #define AR_D_TXBLK_WRITE_COMMAND 0x0F000000
613 #define AR_D_TXBLK_WRITE_COMMAND_S 24
615 #define AR_D_GBL_IFS_SLOT 0x1070
616 #define AR_D_GBL_IFS_SLOT_M 0x0000FFFF
617 #define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000
619 #define AR_D_GBL_IFS_EIFS 0x10b0
620 #define AR_D_GBL_IFS_EIFS_M 0x0000FFFF
621 #define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000
622 #define AR_D_GBL_IFS_EIFS_ASYNC_FIFO 363
624 #define AR_D_GBL_IFS_MISC 0x10f0
625 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007
626 #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008
627 #define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00
628 #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000
629 #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000
630 #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000
631 #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000
632 #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000
634 #define AR_D_FPCTL 0x1230
635 #define AR_D_FPCTL_DCU 0x0000000F
636 #define AR_D_FPCTL_DCU_S 0
637 #define AR_D_FPCTL_PREFETCH_EN 0x00000010
638 #define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0
639 #define AR_D_FPCTL_BURST_PREFETCH_S 5
641 #define AR_D_TXPSE 0x1270
642 #define AR_D_TXPSE_CTRL 0x000003FF
643 #define AR_D_TXPSE_RESV0 0x0000FC00
644 #define AR_D_TXPSE_STATUS 0x00010000
645 #define AR_D_TXPSE_RESV1 0xFFFE0000
647 #define AR_D_TXSLOTMASK 0x12f0
648 #define AR_D_TXSLOTMASK_NUM 0x0000000F
650 #define AR_CFG_LED 0x1f04
651 #define AR_CFG_SCLK_RATE_IND 0x00000003
652 #define AR_CFG_SCLK_RATE_IND_S 0
653 #define AR_CFG_SCLK_32MHZ 0x00000000
654 #define AR_CFG_SCLK_4MHZ 0x00000001
655 #define AR_CFG_SCLK_1MHZ 0x00000002
656 #define AR_CFG_SCLK_32KHZ 0x00000003
657 #define AR_CFG_LED_BLINK_SLOW 0x00000008
658 #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070
659 #define AR_CFG_LED_MODE_SEL 0x00000380
660 #define AR_CFG_LED_MODE_SEL_S 7
661 #define AR_CFG_LED_POWER 0x00000280
662 #define AR_CFG_LED_POWER_S 7
663 #define AR_CFG_LED_NETWORK 0x00000300
664 #define AR_CFG_LED_NETWORK_S 7
665 #define AR_CFG_LED_MODE_PROP 0x0
666 #define AR_CFG_LED_MODE_RPROP 0x1
667 #define AR_CFG_LED_MODE_SPLIT 0x2
668 #define AR_CFG_LED_MODE_RAND 0x3
669 #define AR_CFG_LED_MODE_POWER_OFF 0x4
670 #define AR_CFG_LED_MODE_POWER_ON 0x5
671 #define AR_CFG_LED_MODE_NETWORK_OFF 0x4
672 #define AR_CFG_LED_MODE_NETWORK_ON 0x6
673 #define AR_CFG_LED_ASSOC_CTL 0x00000c00
674 #define AR_CFG_LED_ASSOC_CTL_S 10
675 #define AR_CFG_LED_ASSOC_NONE 0x0
676 #define AR_CFG_LED_ASSOC_ACTIVE 0x1
677 #define AR_CFG_LED_ASSOC_PENDING 0x2
679 #define AR_CFG_LED_BLINK_SLOW 0x00000008
680 #define AR_CFG_LED_BLINK_SLOW_S 3
682 #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070
683 #define AR_CFG_LED_BLINK_THRESH_SEL_S 4
685 #define AR_MAC_SLEEP 0x1f00
686 #define AR_MAC_SLEEP_MAC_AWAKE 0x00000000
687 #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001
690 #define AR_RC_AHB 0x00000001
691 #define AR_RC_APB 0x00000002
692 #define AR_RC_HOSTIF 0x00000100
694 #define AR_WA (AR_SREV_9340(ah) ? 0x40c4 : 0x4004)
695 #define AR_WA_BIT6 (1 << 6)
696 #define AR_WA_BIT7 (1 << 7)
697 #define AR_WA_BIT23 (1 << 23)
698 #define AR_WA_D3_L1_DISABLE (1 << 14)
699 #define AR_WA_UNTIE_RESET_EN (1 << 15) /* Enable PCI Reset
700 to POR (power-on-reset) */
701 #define AR_WA_D3_TO_L1_DISABLE_REAL (1 << 16)
702 #define AR_WA_ASPM_TIMER_BASED_DISABLE (1 << 17)
703 #define AR_WA_RESET_EN (1 << 18) /* Enable PCI-Reset to
705 #define AR_WA_ANALOG_SHIFT (1 << 20)
706 #define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */
707 #define AR_WA_BIT22 (1 << 22)
708 #define AR9285_WA_DEFAULT 0x004a050b
709 #define AR9280_WA_DEFAULT 0x0040073b
710 #define AR_WA_DEFAULT 0x0000073f
713 #define AR_PM_STATE 0x4008
714 #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000
716 #define AR_HOST_TIMEOUT (AR_SREV_9340(ah) ? 0x4008 : 0x4018)
717 #define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF
718 #define AR_HOST_TIMEOUT_APB_CNTR_S 0
719 #define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000
720 #define AR_HOST_TIMEOUT_LCL_CNTR_S 16
722 #define AR_EEPROM 0x401c
723 #define AR_EEPROM_ABSENT 0x00000100
724 #define AR_EEPROM_CORRUPT 0x00000200
725 #define AR_EEPROM_PROT_MASK 0x03FFFC00
726 #define AR_EEPROM_PROT_MASK_S 10
728 #define EEPROM_PROTECT_RP_0_31 0x0001
729 #define EEPROM_PROTECT_WP_0_31 0x0002
730 #define EEPROM_PROTECT_RP_32_63 0x0004
731 #define EEPROM_PROTECT_WP_32_63 0x0008
732 #define EEPROM_PROTECT_RP_64_127 0x0010
733 #define EEPROM_PROTECT_WP_64_127 0x0020
734 #define EEPROM_PROTECT_RP_128_191 0x0040
735 #define EEPROM_PROTECT_WP_128_191 0x0080
736 #define EEPROM_PROTECT_RP_192_255 0x0100
737 #define EEPROM_PROTECT_WP_192_255 0x0200
738 #define EEPROM_PROTECT_RP_256_511 0x0400
739 #define EEPROM_PROTECT_WP_256_511 0x0800
740 #define EEPROM_PROTECT_RP_512_1023 0x1000
741 #define EEPROM_PROTECT_WP_512_1023 0x2000
742 #define EEPROM_PROTECT_RP_1024_2047 0x4000
743 #define EEPROM_PROTECT_WP_1024_2047 0x8000
746 ((AR_SREV_9100(ah)) ? 0x0600 : (AR_SREV_9340(ah) \
750 ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF)
751 #define AR_SREV_VERSION 0x000000F0
752 #define AR_SREV_VERSION_S 4
753 #define AR_SREV_REVISION 0x00000007
755 #define AR_SREV_ID2 0xFFFFFFFF
756 #define AR_SREV_VERSION2 0xFFFC0000
757 #define AR_SREV_VERSION2_S 18
758 #define AR_SREV_TYPE2 0x0003F000
759 #define AR_SREV_TYPE2_S 12
760 #define AR_SREV_TYPE2_CHAIN 0x00001000
761 #define AR_SREV_TYPE2_HOST_MODE 0x00002000
762 #define AR_SREV_REVISION2 0x00000F00
763 #define AR_SREV_REVISION2_S 8
765 #define AR_SREV_VERSION_5416_PCI 0xD
766 #define AR_SREV_VERSION_5416_PCIE 0xC
767 #define AR_SREV_REVISION_5416_10 0
768 #define AR_SREV_REVISION_5416_20 1
769 #define AR_SREV_REVISION_5416_22 2
770 #define AR_SREV_VERSION_9100 0x14
771 #define AR_SREV_VERSION_9160 0x40
772 #define AR_SREV_REVISION_9160_10 0
773 #define AR_SREV_REVISION_9160_11 1
774 #define AR_SREV_VERSION_9280 0x80
775 #define AR_SREV_REVISION_9280_10 0
776 #define AR_SREV_REVISION_9280_20 1
777 #define AR_SREV_REVISION_9280_21 2
778 #define AR_SREV_VERSION_9285 0xC0
779 #define AR_SREV_REVISION_9285_10 0
780 #define AR_SREV_REVISION_9285_11 1
781 #define AR_SREV_REVISION_9285_12 2
782 #define AR_SREV_VERSION_9287 0x180
783 #define AR_SREV_REVISION_9287_10 0
784 #define AR_SREV_REVISION_9287_11 1
785 #define AR_SREV_REVISION_9287_12 2
786 #define AR_SREV_REVISION_9287_13 3
787 #define AR_SREV_VERSION_9271 0x140
788 #define AR_SREV_REVISION_9271_10 0
789 #define AR_SREV_REVISION_9271_11 1
790 #define AR_SREV_VERSION_9300 0x1c0
791 #define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
792 #define AR_SREV_REVISION_9300_22 3
793 #define AR_SREV_VERSION_9330 0x200
794 #define AR_SREV_REVISION_9330_10 0
795 #define AR_SREV_REVISION_9330_11 1
796 #define AR_SREV_REVISION_9330_12 2
797 #define AR_SREV_VERSION_9485 0x240
798 #define AR_SREV_REVISION_9485_10 0
799 #define AR_SREV_REVISION_9485_11 1
800 #define AR_SREV_VERSION_9340 0x300
801 #define AR_SREV_REVISION_9340_10 0
802 #define AR_SREV_REVISION_9340_11 1
803 #define AR_SREV_REVISION_9340_12 2
804 #define AR_SREV_REVISION_9340_13 3
805 #define AR_SREV_VERSION_9580 0x1C0
806 #define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */
807 #define AR_SREV_VERSION_9462 0x280
808 #define AR_SREV_REVISION_9462_20 2
809 #define AR_SREV_REVISION_9462_21 3
810 #define AR_SREV_VERSION_9565 0x2C0
811 #define AR_SREV_REVISION_9565_10 0
812 #define AR_SREV_VERSION_9550 0x400
814 #define AR_SREV_5416(_ah) \
815 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
816 ((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE))
817 #define AR_SREV_5416_22_OR_LATER(_ah) \
818 (((AR_SREV_5416(_ah)) && \
819 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_22)) || \
820 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))
822 #define AR_SREV_9100(ah) \
823 ((ah->hw_version.macVersion) == AR_SREV_VERSION_9100)
824 #define AR_SREV_9100_OR_LATER(_ah) \
825 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100))
827 #define AR_SREV_9160(_ah) \
828 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160))
829 #define AR_SREV_9160_10_OR_LATER(_ah) \
830 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160))
831 #define AR_SREV_9160_11(_ah) \
832 (AR_SREV_9160(_ah) && \
833 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11))
834 #define AR_SREV_9280(_ah) \
835 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))
836 #define AR_SREV_9280_20_OR_LATER(_ah) \
837 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280))
838 #define AR_SREV_9280_20(_ah) \
839 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280))
841 #define AR_SREV_9285(_ah) \
842 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285))
843 #define AR_SREV_9285_12_OR_LATER(_ah) \
844 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285))
846 #define AR_SREV_9287(_ah) \
847 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287))
848 #define AR_SREV_9287_11_OR_LATER(_ah) \
849 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287))
850 #define AR_SREV_9287_11(_ah) \
851 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
852 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11))
853 #define AR_SREV_9287_12(_ah) \
854 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
855 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12))
856 #define AR_SREV_9287_12_OR_LATER(_ah) \
857 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
858 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
859 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_12)))
860 #define AR_SREV_9287_13_OR_LATER(_ah) \
861 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \
862 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \
863 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_13)))
865 #define AR_SREV_9271(_ah) \
866 (((_ah))->hw_version.macVersion == AR_SREV_VERSION_9271)
867 #define AR_SREV_9271_10(_ah) \
868 (AR_SREV_9271(_ah) && \
869 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_10))
870 #define AR_SREV_9271_11(_ah) \
871 (AR_SREV_9271(_ah) && \
872 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11))
874 #define AR_SREV_9300(_ah) \
875 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))
876 #define AR_SREV_9300_20_OR_LATER(_ah) \
877 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9300)
878 #define AR_SREV_9300_22(_ah) \
879 (AR_SREV_9300(ah) && \
880 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9300_22))
882 #define AR_SREV_9330(_ah) \
883 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9330))
884 #define AR_SREV_9330_10(_ah) \
885 (AR_SREV_9330((_ah)) && \
886 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_10))
887 #define AR_SREV_9330_11(_ah) \
888 (AR_SREV_9330((_ah)) && \
889 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_11))
890 #define AR_SREV_9330_12(_ah) \
891 (AR_SREV_9330((_ah)) && \
892 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_12))
894 #define AR_SREV_9485(_ah) \
895 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485))
896 #define AR_SREV_9485_11_OR_LATER(_ah) \
897 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485) && \
898 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9485_11))
899 #define AR_SREV_9485_OR_LATER(_ah) \
900 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9485))
902 #define AR_SREV_9340(_ah) \
903 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))
905 #define AR_SREV_9340_13_OR_LATER(_ah) \
906 (AR_SREV_9340((_ah)) && \
907 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9340_13))
909 #define AR_SREV_9285E_20(_ah) \
910 (AR_SREV_9285_12_OR_LATER(_ah) && \
911 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
913 #define AR_SREV_9462(_ah) \
914 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462))
915 #define AR_SREV_9462_20(_ah) \
916 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
917 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9462_20))
918 #define AR_SREV_9462_21(_ah) \
919 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
920 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9462_21))
921 #define AR_SREV_9462_20_OR_LATER(_ah) \
922 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
923 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_20))
924 #define AR_SREV_9462_21_OR_LATER(_ah) \
925 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
926 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_21))
928 #define AR_SREV_9565(_ah) \
929 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565))
931 #define AR_SREV_9565_10(_ah) \
932 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
933 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_10))
935 #define AR_SREV_9550(_ah) \
936 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550))
938 #define AR_SREV_9580(_ah) \
939 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \
940 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9580_10))
942 #define AR_SREV_9580_10(_ah) \
943 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \
944 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9580_10))
946 /* NOTE: When adding chips newer than Peacock, add chip check here */
947 #define AR_SREV_9580_10_OR_LATER(_ah) \
951 AR9280_USB
= 1, /* AR7010 + AR9280, UB94 */
952 AR9287_USB
= 2, /* AR7010 + AR9287, UB95 */
956 #define AR_DEVID_7010(_ah) \
957 (((_ah)->hw_version.usbdev == AR9280_USB) || \
958 ((_ah)->hw_version.usbdev == AR9287_USB))
960 #define AR_RADIO_SREV_MAJOR 0xf0
961 #define AR_RAD5133_SREV_MAJOR 0xc0
962 #define AR_RAD2133_SREV_MAJOR 0xd0
963 #define AR_RAD5122_SREV_MAJOR 0xe0
964 #define AR_RAD2122_SREV_MAJOR 0xf0
966 #define AR_AHB_MODE 0x4024
967 #define AR_AHB_EXACT_WR_EN 0x00000000
968 #define AR_AHB_BUF_WR_EN 0x00000001
969 #define AR_AHB_EXACT_RD_EN 0x00000000
970 #define AR_AHB_CACHELINE_RD_EN 0x00000002
971 #define AR_AHB_PREFETCH_RD_EN 0x00000004
972 #define AR_AHB_PAGE_SIZE_1K 0x00000000
973 #define AR_AHB_PAGE_SIZE_2K 0x00000008
974 #define AR_AHB_PAGE_SIZE_4K 0x00000010
975 #define AR_AHB_CUSTOM_BURST_EN 0x000000C0
976 #define AR_AHB_CUSTOM_BURST_EN_S 6
977 #define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3
979 #define AR_INTR_RTC_IRQ 0x00000001
980 #define AR_INTR_MAC_IRQ 0x00000002
981 #define AR_INTR_EEP_PROT_ACCESS 0x00000004
982 #define AR_INTR_MAC_AWAKE 0x00020000
983 #define AR_INTR_MAC_ASLEEP 0x00040000
984 #define AR_INTR_SPURIOUS 0xFFFFFFFF
987 #define AR_INTR_SYNC_CAUSE (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
988 #define AR_INTR_SYNC_CAUSE_CLR (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
991 #define AR_INTR_SYNC_ENABLE (AR_SREV_9340(ah) ? 0x4014 : 0x402c)
992 #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000
993 #define AR_INTR_SYNC_ENABLE_GPIO_S 18
996 AR_INTR_SYNC_RTC_IRQ
= 0x00000001,
997 AR_INTR_SYNC_MAC_IRQ
= 0x00000002,
998 AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS
= 0x00000004,
999 AR_INTR_SYNC_APB_TIMEOUT
= 0x00000008,
1000 AR_INTR_SYNC_PCI_MODE_CONFLICT
= 0x00000010,
1001 AR_INTR_SYNC_HOST1_FATAL
= 0x00000020,
1002 AR_INTR_SYNC_HOST1_PERR
= 0x00000040,
1003 AR_INTR_SYNC_TRCV_FIFO_PERR
= 0x00000080,
1004 AR_INTR_SYNC_RADM_CPL_EP
= 0x00000100,
1005 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT
= 0x00000200,
1006 AR_INTR_SYNC_RADM_CPL_TLP_ABORT
= 0x00000400,
1007 AR_INTR_SYNC_RADM_CPL_ECRC_ERR
= 0x00000800,
1008 AR_INTR_SYNC_RADM_CPL_TIMEOUT
= 0x00001000,
1009 AR_INTR_SYNC_LOCAL_TIMEOUT
= 0x00002000,
1010 AR_INTR_SYNC_PM_ACCESS
= 0x00004000,
1011 AR_INTR_SYNC_MAC_AWAKE
= 0x00008000,
1012 AR_INTR_SYNC_MAC_ASLEEP
= 0x00010000,
1013 AR_INTR_SYNC_MAC_SLEEP_ACCESS
= 0x00020000,
1014 AR_INTR_SYNC_ALL
= 0x0003FFFF,
1017 AR_INTR_SYNC_DEFAULT
= (AR_INTR_SYNC_HOST1_FATAL
|
1018 AR_INTR_SYNC_HOST1_PERR
|
1019 AR_INTR_SYNC_RADM_CPL_EP
|
1020 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT
|
1021 AR_INTR_SYNC_RADM_CPL_TLP_ABORT
|
1022 AR_INTR_SYNC_RADM_CPL_ECRC_ERR
|
1023 AR_INTR_SYNC_RADM_CPL_TIMEOUT
|
1024 AR_INTR_SYNC_LOCAL_TIMEOUT
|
1025 AR_INTR_SYNC_MAC_SLEEP_ACCESS
),
1027 AR9340_INTR_SYNC_LOCAL_TIMEOUT
= 0x00000010,
1029 AR_INTR_SYNC_SPURIOUS
= 0xFFFFFFFF,
1033 #define AR_INTR_ASYNC_MASK (AR_SREV_9340(ah) ? 0x4018 : 0x4030)
1034 #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000
1035 #define AR_INTR_ASYNC_MASK_GPIO_S 18
1036 #define AR_INTR_ASYNC_MASK_MCI 0x00000080
1037 #define AR_INTR_ASYNC_MASK_MCI_S 7
1039 #define AR_INTR_SYNC_MASK (AR_SREV_9340(ah) ? 0x401c : 0x4034)
1040 #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000
1041 #define AR_INTR_SYNC_MASK_GPIO_S 18
1043 #define AR_INTR_ASYNC_CAUSE_CLR (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
1044 #define AR_INTR_ASYNC_CAUSE (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
1045 #define AR_INTR_ASYNC_CAUSE_MCI 0x00000080
1046 #define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | \
1047 AR_INTR_ASYNC_CAUSE_MCI)
1049 /* Asynchronous Interrupt Enable Register */
1050 #define AR_INTR_ASYNC_ENABLE_MCI 0x00000080
1051 #define AR_INTR_ASYNC_ENABLE_MCI_S 7
1054 #define AR_INTR_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4024 : 0x403c)
1055 #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000
1056 #define AR_INTR_ASYNC_ENABLE_GPIO_S 18
1058 #define AR_PCIE_SERDES 0x4040
1059 #define AR_PCIE_SERDES2 0x4044
1060 #define AR_PCIE_PM_CTRL (AR_SREV_9340(ah) ? 0x4004 : 0x4014)
1061 #define AR_PCIE_PM_CTRL_ENA 0x00080000
1063 #define AR_PCIE_PHY_REG3 0x18c08
1065 #define AR_NUM_GPIO 14
1066 #define AR928X_NUM_GPIO 10
1067 #define AR9285_NUM_GPIO 12
1068 #define AR9287_NUM_GPIO 11
1069 #define AR9271_NUM_GPIO 16
1070 #define AR9300_NUM_GPIO 17
1071 #define AR7010_NUM_GPIO 16
1073 #define AR_GPIO_IN_OUT (AR_SREV_9340(ah) ? 0x4028 : 0x4048)
1074 #define AR_GPIO_IN_VAL 0x0FFFC000
1075 #define AR_GPIO_IN_VAL_S 14
1076 #define AR928X_GPIO_IN_VAL 0x000FFC00
1077 #define AR928X_GPIO_IN_VAL_S 10
1078 #define AR9285_GPIO_IN_VAL 0x00FFF000
1079 #define AR9285_GPIO_IN_VAL_S 12
1080 #define AR9287_GPIO_IN_VAL 0x003FF800
1081 #define AR9287_GPIO_IN_VAL_S 11
1082 #define AR9271_GPIO_IN_VAL 0xFFFF0000
1083 #define AR9271_GPIO_IN_VAL_S 16
1084 #define AR7010_GPIO_IN_VAL 0x0000FFFF
1085 #define AR7010_GPIO_IN_VAL_S 0
1087 #define AR_GPIO_IN (AR_SREV_9340(ah) ? 0x402c : 0x404c)
1088 #define AR9300_GPIO_IN_VAL 0x0001FFFF
1089 #define AR9300_GPIO_IN_VAL_S 0
1091 #define AR_GPIO_OE_OUT (AR_SREV_9340(ah) ? 0x4030 : \
1092 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c))
1093 #define AR_GPIO_OE_OUT_DRV 0x3
1094 #define AR_GPIO_OE_OUT_DRV_NO 0x0
1095 #define AR_GPIO_OE_OUT_DRV_LOW 0x1
1096 #define AR_GPIO_OE_OUT_DRV_HI 0x2
1097 #define AR_GPIO_OE_OUT_DRV_ALL 0x3
1099 #define AR7010_GPIO_OE 0x52000
1100 #define AR7010_GPIO_OE_MASK 0x1
1101 #define AR7010_GPIO_OE_AS_OUTPUT 0x0
1102 #define AR7010_GPIO_OE_AS_INPUT 0x1
1103 #define AR7010_GPIO_IN 0x52004
1104 #define AR7010_GPIO_OUT 0x52008
1105 #define AR7010_GPIO_SET 0x5200C
1106 #define AR7010_GPIO_CLEAR 0x52010
1107 #define AR7010_GPIO_INT 0x52014
1108 #define AR7010_GPIO_INT_TYPE 0x52018
1109 #define AR7010_GPIO_INT_POLARITY 0x5201C
1110 #define AR7010_GPIO_PENDING 0x52020
1111 #define AR7010_GPIO_INT_MASK 0x52024
1112 #define AR7010_GPIO_FUNCTION 0x52028
1114 #define AR_GPIO_INTR_POL (AR_SREV_9340(ah) ? 0x4038 : \
1115 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050))
1116 #define AR_GPIO_INTR_POL_VAL 0x0001FFFF
1117 #define AR_GPIO_INTR_POL_VAL_S 0
1119 #define AR_GPIO_INPUT_EN_VAL (AR_SREV_9340(ah) ? 0x403c : \
1120 (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054))
1121 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004
1122 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2
1123 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008
1124 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3
1125 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010
1126 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4
1127 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080
1128 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7
1129 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400
1130 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10
1131 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000
1132 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12
1133 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000
1134 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15
1135 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
1136 #define AR_GPIO_JTAG_DISABLE 0x00020000
1138 #define AR_GPIO_INPUT_MUX1 (AR_SREV_9340(ah) ? 0x4040 : \
1139 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058))
1140 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000
1141 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16
1142 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00
1143 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8
1145 #define AR_GPIO_INPUT_MUX2 (AR_SREV_9340(ah) ? 0x4044 : \
1146 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c))
1147 #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f
1148 #define AR_GPIO_INPUT_MUX2_CLK25_S 0
1149 #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0
1150 #define AR_GPIO_INPUT_MUX2_RFSILENT_S 4
1151 #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00
1152 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8
1154 #define AR_GPIO_OUTPUT_MUX1 (AR_SREV_9340(ah) ? 0x4048 : \
1155 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060))
1156 #define AR_GPIO_OUTPUT_MUX2 (AR_SREV_9340(ah) ? 0x404c : \
1157 (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064))
1158 #define AR_GPIO_OUTPUT_MUX3 (AR_SREV_9340(ah) ? 0x4050 : \
1159 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068))
1161 #define AR_INPUT_STATE (AR_SREV_9340(ah) ? 0x4054 : \
1162 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c))
1164 #define AR_EEPROM_STATUS_DATA (AR_SREV_9340(ah) ? 0x40c8 : \
1165 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c))
1166 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
1167 #define AR_EEPROM_STATUS_DATA_VAL_S 0
1168 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
1169 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000
1170 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
1171 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
1173 #define AR_OBS (AR_SREV_9340(ah) ? 0x405c : \
1174 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080))
1176 #define AR_GPIO_PDPU (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)
1178 #define AR_PCIE_MSI (AR_SREV_9340(ah) ? 0x40d8 : \
1179 (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094))
1180 #define AR_PCIE_MSI_ENABLE 0x00000001
1182 #define AR_INTR_PRIO_SYNC_ENABLE (AR_SREV_9340(ah) ? 0x4088 : 0x40c4)
1183 #define AR_INTR_PRIO_ASYNC_MASK (AR_SREV_9340(ah) ? 0x408c : 0x40c8)
1184 #define AR_INTR_PRIO_SYNC_MASK (AR_SREV_9340(ah) ? 0x4090 : 0x40cc)
1185 #define AR_INTR_PRIO_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4094 : 0x40d4)
1186 #define AR_ENT_OTP 0x40d8
1187 #define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
1188 #define AR_ENT_OTP_49GHZ_DISABLE 0x00100000
1189 #define AR_ENT_OTP_MIN_PKT_SIZE_DISABLE 0x00800000
1191 #define AR_CH0_BB_DPLL1 0x16180
1192 #define AR_CH0_BB_DPLL1_REFDIV 0xF8000000
1193 #define AR_CH0_BB_DPLL1_REFDIV_S 27
1194 #define AR_CH0_BB_DPLL1_NINI 0x07FC0000
1195 #define AR_CH0_BB_DPLL1_NINI_S 18
1196 #define AR_CH0_BB_DPLL1_NFRAC 0x0003FFFF
1197 #define AR_CH0_BB_DPLL1_NFRAC_S 0
1199 #define AR_CH0_BB_DPLL2 0x16184
1200 #define AR_CH0_BB_DPLL2_LOCAL_PLL 0x40000000
1201 #define AR_CH0_BB_DPLL2_LOCAL_PLL_S 30
1202 #define AR_CH0_DPLL2_KI 0x3C000000
1203 #define AR_CH0_DPLL2_KI_S 26
1204 #define AR_CH0_DPLL2_KD 0x03F80000
1205 #define AR_CH0_DPLL2_KD_S 19
1206 #define AR_CH0_BB_DPLL2_EN_NEGTRIG 0x00040000
1207 #define AR_CH0_BB_DPLL2_EN_NEGTRIG_S 18
1208 #define AR_CH0_BB_DPLL2_PLL_PWD 0x00010000
1209 #define AR_CH0_BB_DPLL2_PLL_PWD_S 16
1210 #define AR_CH0_BB_DPLL2_OUTDIV 0x0000E000
1211 #define AR_CH0_BB_DPLL2_OUTDIV_S 13
1213 #define AR_CH0_BB_DPLL3 0x16188
1214 #define AR_CH0_BB_DPLL3_PHASE_SHIFT 0x3F800000
1215 #define AR_CH0_BB_DPLL3_PHASE_SHIFT_S 23
1217 #define AR_CH0_DDR_DPLL2 0x16244
1218 #define AR_CH0_DDR_DPLL3 0x16248
1219 #define AR_CH0_DPLL3_PHASE_SHIFT 0x3F800000
1220 #define AR_CH0_DPLL3_PHASE_SHIFT_S 23
1221 #define AR_PHY_CCA_NOM_VAL_2GHZ -118
1223 #define AR_RTC_9300_PLL_DIV 0x000003ff
1224 #define AR_RTC_9300_PLL_DIV_S 0
1225 #define AR_RTC_9300_PLL_REFDIV 0x00003C00
1226 #define AR_RTC_9300_PLL_REFDIV_S 10
1227 #define AR_RTC_9300_PLL_CLKSEL 0x0000C000
1228 #define AR_RTC_9300_PLL_CLKSEL_S 14
1230 #define AR_RTC_9160_PLL_DIV 0x000003ff
1231 #define AR_RTC_9160_PLL_DIV_S 0
1232 #define AR_RTC_9160_PLL_REFDIV 0x00003C00
1233 #define AR_RTC_9160_PLL_REFDIV_S 10
1234 #define AR_RTC_9160_PLL_CLKSEL 0x0000C000
1235 #define AR_RTC_9160_PLL_CLKSEL_S 14
1237 #define AR_RTC_BASE 0x00020000
1239 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000)
1240 #define AR_RTC_RC_M 0x00000003
1241 #define AR_RTC_RC_MAC_WARM 0x00000001
1242 #define AR_RTC_RC_MAC_COLD 0x00000002
1243 #define AR_RTC_RC_COLD_RESET 0x00000004
1244 #define AR_RTC_RC_WARM_RESET 0x00000008
1246 /* Crystal Control */
1247 #define AR_RTC_XTAL_CONTROL 0x7004
1250 #define AR_RTC_REG_CONTROL0 0x7008
1253 #define AR_RTC_REG_CONTROL1 0x700c
1254 #define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001
1256 #define AR_RTC_PLL_CONTROL \
1257 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
1259 #define AR_RTC_PLL_CONTROL2 0x703c
1261 #define AR_RTC_PLL_DIV 0x0000001f
1262 #define AR_RTC_PLL_DIV_S 0
1263 #define AR_RTC_PLL_DIV2 0x00000020
1264 #define AR_RTC_PLL_REFDIV_5 0x000000c0
1265 #define AR_RTC_PLL_CLKSEL 0x00000300
1266 #define AR_RTC_PLL_CLKSEL_S 8
1267 #define AR_RTC_PLL_BYPASS 0x00010000
1268 #define AR_RTC_PLL_NOPWD 0x00040000
1269 #define AR_RTC_PLL_NOPWD_S 18
1271 #define PLL3 0x16188
1272 #define PLL3_DO_MEAS_MASK 0x40000000
1273 #define PLL4 0x1618c
1274 #define PLL4_MEAS_DONE 0x8
1275 #define SQSUM_DVC_MASK 0x007ffff8
1277 #define AR_RTC_RESET \
1278 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
1279 #define AR_RTC_RESET_EN (0x00000001)
1281 #define AR_RTC_STATUS \
1282 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044)
1284 #define AR_RTC_STATUS_M \
1285 ((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f)
1287 #define AR_RTC_PM_STATUS_M 0x0000000f
1289 #define AR_RTC_STATUS_SHUTDOWN 0x00000001
1290 #define AR_RTC_STATUS_ON 0x00000002
1291 #define AR_RTC_STATUS_SLEEP 0x00000004
1292 #define AR_RTC_STATUS_WAKEUP 0x00000008
1294 #define AR_RTC_SLEEP_CLK \
1295 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)
1296 #define AR_RTC_FORCE_DERIVED_CLK 0x2
1297 #define AR_RTC_FORCE_SWREG_PRD 0x00000004
1299 #define AR_RTC_FORCE_WAKE \
1300 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)
1301 #define AR_RTC_FORCE_WAKE_EN 0x00000001
1302 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002
1305 #define AR_RTC_INTR_CAUSE \
1306 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050)
1308 #define AR_RTC_INTR_ENABLE \
1309 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054)
1311 #define AR_RTC_INTR_MASK \
1312 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058)
1314 #define AR_RTC_KEEP_AWAKE 0x7034
1316 /* RTC_DERIVED_* - only for AR9100 */
1318 #define AR_RTC_DERIVED_CLK \
1319 (AR_SREV_9100(ah) ? (AR_RTC_BASE + 0x0038) : 0x7038)
1320 #define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe
1321 #define AR_RTC_DERIVED_CLK_PERIOD_S 1
1323 #define AR_SEQ_MASK 0x8060
1325 #define AR_AN_RF2G1_CH0 0x7810
1326 #define AR_AN_RF2G1_CH0_OB 0x03800000
1327 #define AR_AN_RF2G1_CH0_OB_S 23
1328 #define AR_AN_RF2G1_CH0_DB 0x1C000000
1329 #define AR_AN_RF2G1_CH0_DB_S 26
1331 #define AR_AN_RF5G1_CH0 0x7818
1332 #define AR_AN_RF5G1_CH0_OB5 0x00070000
1333 #define AR_AN_RF5G1_CH0_OB5_S 16
1334 #define AR_AN_RF5G1_CH0_DB5 0x00380000
1335 #define AR_AN_RF5G1_CH0_DB5_S 19
1337 #define AR_AN_RF2G1_CH1 0x7834
1338 #define AR_AN_RF2G1_CH1_OB 0x03800000
1339 #define AR_AN_RF2G1_CH1_OB_S 23
1340 #define AR_AN_RF2G1_CH1_DB 0x1C000000
1341 #define AR_AN_RF2G1_CH1_DB_S 26
1343 #define AR_AN_RF5G1_CH1 0x783C
1344 #define AR_AN_RF5G1_CH1_OB5 0x00070000
1345 #define AR_AN_RF5G1_CH1_OB5_S 16
1346 #define AR_AN_RF5G1_CH1_DB5 0x00380000
1347 #define AR_AN_RF5G1_CH1_DB5_S 19
1349 #define AR_AN_TOP1 0x7890
1350 #define AR_AN_TOP1_DACIPMODE 0x00040000
1351 #define AR_AN_TOP1_DACIPMODE_S 18
1353 #define AR_AN_TOP2 0x7894
1354 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000
1355 #define AR_AN_TOP2_XPABIAS_LVL_S 30
1356 #define AR_AN_TOP2_LOCALBIAS 0x00200000
1357 #define AR_AN_TOP2_LOCALBIAS_S 21
1358 #define AR_AN_TOP2_PWDCLKIND 0x00400000
1359 #define AR_AN_TOP2_PWDCLKIND_S 22
1361 #define AR_AN_SYNTH9 0x7868
1362 #define AR_AN_SYNTH9_REFDIVA 0xf8000000
1363 #define AR_AN_SYNTH9_REFDIVA_S 27
1365 #define AR9285_AN_RF2G1 0x7820
1366 #define AR9285_AN_RF2G1_ENPACAL 0x00000800
1367 #define AR9285_AN_RF2G1_ENPACAL_S 11
1368 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000
1369 #define AR9285_AN_RF2G1_PDPADRV1_S 25
1370 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000
1371 #define AR9285_AN_RF2G1_PDPADRV2_S 24
1372 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000
1373 #define AR9285_AN_RF2G1_PDPAOUT_S 23
1376 #define AR9285_AN_RF2G2 0x7824
1377 #define AR9285_AN_RF2G2_OFFCAL 0x00001000
1378 #define AR9285_AN_RF2G2_OFFCAL_S 12
1380 #define AR9285_AN_RF2G3 0x7828
1381 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
1382 #define AR9285_AN_RF2G3_PDVCCOMP_S 25
1383 #define AR9285_AN_RF2G3_OB_0 0x00E00000
1384 #define AR9285_AN_RF2G3_OB_0_S 21
1385 #define AR9285_AN_RF2G3_OB_1 0x001C0000
1386 #define AR9285_AN_RF2G3_OB_1_S 18
1387 #define AR9285_AN_RF2G3_OB_2 0x00038000
1388 #define AR9285_AN_RF2G3_OB_2_S 15
1389 #define AR9285_AN_RF2G3_OB_3 0x00007000
1390 #define AR9285_AN_RF2G3_OB_3_S 12
1391 #define AR9285_AN_RF2G3_OB_4 0x00000E00
1392 #define AR9285_AN_RF2G3_OB_4_S 9
1394 #define AR9285_AN_RF2G3_DB1_0 0x000001C0
1395 #define AR9285_AN_RF2G3_DB1_0_S 6
1396 #define AR9285_AN_RF2G3_DB1_1 0x00000038
1397 #define AR9285_AN_RF2G3_DB1_1_S 3
1398 #define AR9285_AN_RF2G3_DB1_2 0x00000007
1399 #define AR9285_AN_RF2G3_DB1_2_S 0
1400 #define AR9285_AN_RF2G4 0x782C
1401 #define AR9285_AN_RF2G4_DB1_3 0xE0000000
1402 #define AR9285_AN_RF2G4_DB1_3_S 29
1403 #define AR9285_AN_RF2G4_DB1_4 0x1C000000
1404 #define AR9285_AN_RF2G4_DB1_4_S 26
1406 #define AR9285_AN_RF2G4_DB2_0 0x03800000
1407 #define AR9285_AN_RF2G4_DB2_0_S 23
1408 #define AR9285_AN_RF2G4_DB2_1 0x00700000
1409 #define AR9285_AN_RF2G4_DB2_1_S 20
1410 #define AR9285_AN_RF2G4_DB2_2 0x000E0000
1411 #define AR9285_AN_RF2G4_DB2_2_S 17
1412 #define AR9285_AN_RF2G4_DB2_3 0x0001C000
1413 #define AR9285_AN_RF2G4_DB2_3_S 14
1414 #define AR9285_AN_RF2G4_DB2_4 0x00003800
1415 #define AR9285_AN_RF2G4_DB2_4_S 11
1417 #define AR9285_RF2G5 0x7830
1418 #define AR9285_RF2G5_IC50TX 0xfffff8ff
1419 #define AR9285_RF2G5_IC50TX_SET 0x00000400
1420 #define AR9285_RF2G5_IC50TX_XE_SET 0x00000500
1421 #define AR9285_RF2G5_IC50TX_CLEAR 0x00000700
1422 #define AR9285_RF2G5_IC50TX_CLEAR_S 8
1424 /* AR9271 : 0x7828, 0x782c different setting from AR9285 */
1425 #define AR9271_AN_RF2G3_OB_cck 0x001C0000
1426 #define AR9271_AN_RF2G3_OB_cck_S 18
1427 #define AR9271_AN_RF2G3_OB_psk 0x00038000
1428 #define AR9271_AN_RF2G3_OB_psk_S 15
1429 #define AR9271_AN_RF2G3_OB_qam 0x00007000
1430 #define AR9271_AN_RF2G3_OB_qam_S 12
1432 #define AR9271_AN_RF2G3_DB_1 0x00E00000
1433 #define AR9271_AN_RF2G3_DB_1_S 21
1435 #define AR9271_AN_RF2G3_CCOMP 0xFFF
1436 #define AR9271_AN_RF2G3_CCOMP_S 0
1438 #define AR9271_AN_RF2G4_DB_2 0xE0000000
1439 #define AR9271_AN_RF2G4_DB_2_S 29
1441 #define AR9285_AN_RF2G6 0x7834
1442 #define AR9285_AN_RF2G6_CCOMP 0x00007800
1443 #define AR9285_AN_RF2G6_CCOMP_S 11
1444 #define AR9285_AN_RF2G6_OFFS 0x03f00000
1445 #define AR9285_AN_RF2G6_OFFS_S 20
1447 #define AR9271_AN_RF2G6_OFFS 0x07f00000
1448 #define AR9271_AN_RF2G6_OFFS_S 20
1450 #define AR9285_AN_RF2G7 0x7838
1451 #define AR9285_AN_RF2G7_PWDDB 0x00000002
1452 #define AR9285_AN_RF2G7_PWDDB_S 1
1453 #define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000
1454 #define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29
1456 #define AR9285_AN_RF2G8 0x783C
1457 #define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000
1458 #define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14
1461 #define AR9285_AN_RF2G9 0x7840
1462 #define AR9285_AN_RXTXBB1 0x7854
1463 #define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020
1464 #define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5
1465 #define AR9285_AN_RXTXBB1_PDV2I 0x00000080
1466 #define AR9285_AN_RXTXBB1_PDV2I_S 7
1467 #define AR9285_AN_RXTXBB1_PDDACIF 0x00000100
1468 #define AR9285_AN_RXTXBB1_PDDACIF_S 8
1469 #define AR9285_AN_RXTXBB1_SPARE9 0x00000001
1470 #define AR9285_AN_RXTXBB1_SPARE9_S 0
1472 #define AR9285_AN_TOP2 0x7868
1474 #define AR9285_AN_TOP3 0x786c
1475 #define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C
1476 #define AR9285_AN_TOP3_XPABIAS_LVL_S 2
1477 #define AR9285_AN_TOP3_PWDDAC 0x00800000
1478 #define AR9285_AN_TOP3_PWDDAC_S 23
1480 #define AR9285_AN_TOP4 0x7870
1481 #define AR9285_AN_TOP4_DEFAULT 0x10142c00
1483 #define AR9287_AN_RF2G3_CH0 0x7808
1484 #define AR9287_AN_RF2G3_CH1 0x785c
1485 #define AR9287_AN_RF2G3_DB1 0xE0000000
1486 #define AR9287_AN_RF2G3_DB1_S 29
1487 #define AR9287_AN_RF2G3_DB2 0x1C000000
1488 #define AR9287_AN_RF2G3_DB2_S 26
1489 #define AR9287_AN_RF2G3_OB_CCK 0x03800000
1490 #define AR9287_AN_RF2G3_OB_CCK_S 23
1491 #define AR9287_AN_RF2G3_OB_PSK 0x00700000
1492 #define AR9287_AN_RF2G3_OB_PSK_S 20
1493 #define AR9287_AN_RF2G3_OB_QAM 0x000E0000
1494 #define AR9287_AN_RF2G3_OB_QAM_S 17
1495 #define AR9287_AN_RF2G3_OB_PAL_OFF 0x0001C000
1496 #define AR9287_AN_RF2G3_OB_PAL_OFF_S 14
1498 #define AR9287_AN_TXPC0 0x7898
1499 #define AR9287_AN_TXPC0_TXPCMODE 0x0000C000
1500 #define AR9287_AN_TXPC0_TXPCMODE_S 14
1501 #define AR9287_AN_TXPC0_TXPCMODE_NORMAL 0
1502 #define AR9287_AN_TXPC0_TXPCMODE_TEST 1
1503 #define AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE 2
1504 #define AR9287_AN_TXPC0_TXPCMODE_ATBTEST 3
1506 #define AR9287_AN_TOP2 0x78b4
1507 #define AR9287_AN_TOP2_XPABIAS_LVL 0xC0000000
1508 #define AR9287_AN_TOP2_XPABIAS_LVL_S 30
1510 /* AR9271 specific stuff */
1511 #define AR9271_RESET_POWER_DOWN_CONTROL 0x50044
1512 #define AR9271_RADIO_RF_RST 0x20
1513 #define AR9271_GATE_MAC_CTL 0x4000
1515 #define AR_STA_ID1_STA_AP 0x00010000
1516 #define AR_STA_ID1_ADHOC 0x00020000
1517 #define AR_STA_ID1_PWR_SAV 0x00040000
1518 #define AR_STA_ID1_KSRCHDIS 0x00080000
1519 #define AR_STA_ID1_PCF 0x00100000
1520 #define AR_STA_ID1_USE_DEFANT 0x00200000
1521 #define AR_STA_ID1_DEFANT_UPDATE 0x00400000
1522 #define AR_STA_ID1_AR9100_BA_FIX 0x00400000
1523 #define AR_STA_ID1_RTS_USE_DEF 0x00800000
1524 #define AR_STA_ID1_ACKCTS_6MB 0x01000000
1525 #define AR_STA_ID1_BASE_RATE_11B 0x02000000
1526 #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000
1527 #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000
1528 #define AR_STA_ID1_KSRCH_MODE 0x10000000
1529 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000
1530 #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000
1531 #define AR_STA_ID1_MCAST_KSRCH 0x80000000
1533 #define AR_BSS_ID0 0x8008
1534 #define AR_BSS_ID1 0x800C
1535 #define AR_BSS_ID1_U16 0x0000FFFF
1536 #define AR_BSS_ID1_AID 0x07FF0000
1537 #define AR_BSS_ID1_AID_S 16
1539 #define AR_BCN_RSSI_AVE 0x8010
1540 #define AR_BCN_RSSI_AVE_MASK 0x00000FFF
1542 #define AR_TIME_OUT 0x8014
1543 #define AR_TIME_OUT_ACK 0x00003FFF
1544 #define AR_TIME_OUT_ACK_S 0
1545 #define AR_TIME_OUT_CTS 0x3FFF0000
1546 #define AR_TIME_OUT_CTS_S 16
1548 #define AR_RSSI_THR 0x8018
1549 #define AR_RSSI_THR_MASK 0x000000FF
1550 #define AR_RSSI_THR_BM_THR 0x0000FF00
1551 #define AR_RSSI_THR_BM_THR_S 8
1552 #define AR_RSSI_BCN_WEIGHT 0x1F000000
1553 #define AR_RSSI_BCN_WEIGHT_S 24
1554 #define AR_RSSI_BCN_RSSI_RST 0x20000000
1556 #define AR_USEC 0x801c
1557 #define AR_USEC_USEC 0x0000007F
1558 #define AR_USEC_TX_LAT 0x007FC000
1559 #define AR_USEC_TX_LAT_S 14
1560 #define AR_USEC_RX_LAT 0x1F800000
1561 #define AR_USEC_RX_LAT_S 23
1562 #define AR_USEC_ASYNC_FIFO 0x12E00074
1564 #define AR_RESET_TSF 0x8020
1565 #define AR_RESET_TSF_ONCE 0x01000000
1567 #define AR_MAX_CFP_DUR 0x8038
1568 #define AR_CFP_VAL 0x0000FFFF
1570 #define AR_RX_FILTER 0x803C
1572 #define AR_MCAST_FIL0 0x8040
1573 #define AR_MCAST_FIL1 0x8044
1576 * AR_DIAG_SW - Register which can be used for diagnostics and testing purposes.
1578 * The force RX abort (AR_DIAG_RX_ABORT, bit 25) can be used in conjunction with
1579 * RX block (AR_DIAG_RX_DIS, bit 5) to help fast channel change to shut down
1580 * receive. The force RX abort bit will kill any frame which is currently being
1581 * transferred between the MAC and baseband. The RX block bit (AR_DIAG_RX_DIS)
1582 * will prevent any new frames from getting started.
1584 #define AR_DIAG_SW 0x8048
1585 #define AR_DIAG_CACHE_ACK 0x00000001
1586 #define AR_DIAG_ACK_DIS 0x00000002
1587 #define AR_DIAG_CTS_DIS 0x00000004
1588 #define AR_DIAG_ENCRYPT_DIS 0x00000008
1589 #define AR_DIAG_DECRYPT_DIS 0x00000010
1590 #define AR_DIAG_RX_DIS 0x00000020 /* RX block */
1591 #define AR_DIAG_LOOP_BACK 0x00000040
1592 #define AR_DIAG_CORR_FCS 0x00000080
1593 #define AR_DIAG_CHAN_INFO 0x00000100
1594 #define AR_DIAG_SCRAM_SEED 0x0001FE00
1595 #define AR_DIAG_SCRAM_SEED_S 8
1596 #define AR_DIAG_FRAME_NV0 0x00020000
1597 #define AR_DIAG_OBS_PT_SEL1 0x000C0000
1598 #define AR_DIAG_OBS_PT_SEL1_S 18
1599 #define AR_DIAG_OBS_PT_SEL2 0x08000000
1600 #define AR_DIAG_OBS_PT_SEL2_S 27
1601 #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 /* force rx_clear high */
1602 #define AR_DIAG_IGNORE_VIRT_CS 0x00200000
1603 #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000
1604 #define AR_DIAG_EIFS_CTRL_ENA 0x00800000
1605 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000
1606 #define AR_DIAG_RX_ABORT 0x02000000 /* Force RX abort */
1607 #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000
1608 #define AR_DIAG_OBS_PT_SEL2 0x08000000
1609 #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000
1610 #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000
1612 #define AR_TSF_L32 0x804c
1613 #define AR_TSF_U32 0x8050
1615 #define AR_TST_ADDAC 0x8054
1616 #define AR_DEF_ANTENNA 0x8058
1618 #define AR_AES_MUTE_MASK0 0x805c
1619 #define AR_AES_MUTE_MASK0_FC 0x0000FFFF
1620 #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000
1621 #define AR_AES_MUTE_MASK0_QOS_S 16
1623 #define AR_AES_MUTE_MASK1 0x8060
1624 #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF
1625 #define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000
1626 #define AR_AES_MUTE_MASK1_FC_MGMT_S 16
1628 #define AR_GATED_CLKS 0x8064
1629 #define AR_GATED_CLKS_TX 0x00000002
1630 #define AR_GATED_CLKS_RX 0x00000004
1631 #define AR_GATED_CLKS_REG 0x00000008
1633 #define AR_OBS_BUS_CTRL 0x8068
1634 #define AR_OBS_BUS_SEL_1 0x00040000
1635 #define AR_OBS_BUS_SEL_2 0x00080000
1636 #define AR_OBS_BUS_SEL_3 0x000C0000
1637 #define AR_OBS_BUS_SEL_4 0x08040000
1638 #define AR_OBS_BUS_SEL_5 0x08080000
1640 #define AR_OBS_BUS_1 0x806c
1641 #define AR_OBS_BUS_1_PCU 0x00000001
1642 #define AR_OBS_BUS_1_RX_END 0x00000002
1643 #define AR_OBS_BUS_1_RX_WEP 0x00000004
1644 #define AR_OBS_BUS_1_RX_BEACON 0x00000008
1645 #define AR_OBS_BUS_1_RX_FILTER 0x00000010
1646 #define AR_OBS_BUS_1_TX_HCF 0x00000020
1647 #define AR_OBS_BUS_1_QUIET_TIME 0x00000040
1648 #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080
1649 #define AR_OBS_BUS_1_TX_HOLD 0x00000100
1650 #define AR_OBS_BUS_1_TX_FRAME 0x00000200
1651 #define AR_OBS_BUS_1_RX_FRAME 0x00000400
1652 #define AR_OBS_BUS_1_RX_CLEAR 0x00000800
1653 #define AR_OBS_BUS_1_WEP_STATE 0x0003F000
1654 #define AR_OBS_BUS_1_WEP_STATE_S 12
1655 #define AR_OBS_BUS_1_RX_STATE 0x01F00000
1656 #define AR_OBS_BUS_1_RX_STATE_S 20
1657 #define AR_OBS_BUS_1_TX_STATE 0x7E000000
1658 #define AR_OBS_BUS_1_TX_STATE_S 25
1660 #define AR_LAST_TSTP 0x8080
1661 #define AR_NAV 0x8084
1662 #define AR_RTS_OK 0x8088
1663 #define AR_RTS_FAIL 0x808c
1664 #define AR_ACK_FAIL 0x8090
1665 #define AR_FCS_FAIL 0x8094
1666 #define AR_BEACON_CNT 0x8098
1668 #define AR_SLEEP1 0x80d4
1669 #define AR_SLEEP1_ASSUME_DTIM 0x00080000
1670 #define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000
1671 #define AR_SLEEP1_CAB_TIMEOUT_S 21
1673 #define AR_SLEEP2 0x80d8
1674 #define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000
1675 #define AR_SLEEP2_BEACON_TIMEOUT_S 21
1677 #define AR_TPC 0x80e8
1678 #define AR_TPC_ACK 0x0000003f
1679 #define AR_TPC_ACK_S 0
1680 #define AR_TPC_CTS 0x00003f00
1681 #define AR_TPC_CTS_S 8
1682 #define AR_TPC_CHIRP 0x003f0000
1683 #define AR_TPC_CHIRP_S 16
1685 #define AR_QUIET1 0x80fc
1686 #define AR_QUIET1_NEXT_QUIET_S 0
1687 #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff
1688 #define AR_QUIET1_QUIET_ENABLE 0x00010000
1689 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000
1690 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17
1691 #define AR_QUIET2 0x8100
1692 #define AR_QUIET2_QUIET_PERIOD_S 0
1693 #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff
1694 #define AR_QUIET2_QUIET_DUR_S 16
1695 #define AR_QUIET2_QUIET_DUR 0xffff0000
1697 #define AR_TSF_PARM 0x8104
1698 #define AR_TSF_INCREMENT_M 0x000000ff
1699 #define AR_TSF_INCREMENT_S 0x00
1701 #define AR_QOS_NO_ACK 0x8108
1702 #define AR_QOS_NO_ACK_TWO_BIT 0x0000000f
1703 #define AR_QOS_NO_ACK_TWO_BIT_S 0
1704 #define AR_QOS_NO_ACK_BIT_OFF 0x00000070
1705 #define AR_QOS_NO_ACK_BIT_OFF_S 4
1706 #define AR_QOS_NO_ACK_BYTE_OFF 0x00000180
1707 #define AR_QOS_NO_ACK_BYTE_OFF_S 7
1709 #define AR_PHY_ERR 0x810c
1711 #define AR_PHY_ERR_DCHIRP 0x00000008
1712 #define AR_PHY_ERR_RADAR 0x00000020
1713 #define AR_PHY_ERR_OFDM_TIMING 0x00020000
1714 #define AR_PHY_ERR_CCK_TIMING 0x02000000
1716 #define AR_RXFIFO_CFG 0x8114
1719 #define AR_MIC_QOS_CONTROL 0x8118
1720 #define AR_MIC_QOS_SELECT 0x811c
1722 #define AR_PCU_MISC 0x8120
1723 #define AR_PCU_FORCE_BSSID_MATCH 0x00000001
1724 #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004
1725 #define AR_PCU_TX_ADD_TSF 0x00000008
1726 #define AR_PCU_CCK_SIFS_MODE 0x00000010
1727 #define AR_PCU_RX_ANT_UPDT 0x00000800
1728 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000
1729 #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000
1730 #define AR_PCU_BUG_12306_FIX_ENA 0x00020000
1731 #define AR_PCU_FORCE_QUIET_COLL 0x00040000
1732 #define AR_PCU_TBTT_PROTECT 0x00200000
1733 #define AR_PCU_CLEAR_VMF 0x01000000
1734 #define AR_PCU_CLEAR_BA_VALID 0x04000000
1735 #define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000
1737 #define AR_PCU_BT_ANT_PREVENT_RX 0x00100000
1738 #define AR_PCU_BT_ANT_PREVENT_RX_S 20
1740 #define AR_FILT_OFDM 0x8124
1741 #define AR_FILT_OFDM_COUNT 0x00FFFFFF
1743 #define AR_FILT_CCK 0x8128
1744 #define AR_FILT_CCK_COUNT 0x00FFFFFF
1746 #define AR_PHY_ERR_1 0x812c
1747 #define AR_PHY_ERR_1_COUNT 0x00FFFFFF
1748 #define AR_PHY_ERR_MASK_1 0x8130
1750 #define AR_PHY_ERR_2 0x8134
1751 #define AR_PHY_ERR_2_COUNT 0x00FFFFFF
1752 #define AR_PHY_ERR_MASK_2 0x8138
1754 #define AR_PHY_COUNTMAX (3 << 22)
1755 #define AR_MIBCNT_INTRMASK (3 << 22)
1757 #define AR_TSFOOR_THRESHOLD 0x813c
1758 #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF
1760 #define AR_PHY_ERR_EIFS_MASK 0x8144
1762 #define AR_PHY_ERR_3 0x8168
1763 #define AR_PHY_ERR_3_COUNT 0x00FFFFFF
1764 #define AR_PHY_ERR_MASK_3 0x816c
1766 #define AR_BT_COEX_MODE 0x8170
1767 #define AR_BT_TIME_EXTEND 0x000000ff
1768 #define AR_BT_TIME_EXTEND_S 0
1769 #define AR_BT_TXSTATE_EXTEND 0x00000100
1770 #define AR_BT_TXSTATE_EXTEND_S 8
1771 #define AR_BT_TX_FRAME_EXTEND 0x00000200
1772 #define AR_BT_TX_FRAME_EXTEND_S 9
1773 #define AR_BT_MODE 0x00000c00
1774 #define AR_BT_MODE_S 10
1775 #define AR_BT_QUIET 0x00001000
1776 #define AR_BT_QUIET_S 12
1777 #define AR_BT_QCU_THRESH 0x0001e000
1778 #define AR_BT_QCU_THRESH_S 13
1779 #define AR_BT_RX_CLEAR_POLARITY 0x00020000
1780 #define AR_BT_RX_CLEAR_POLARITY_S 17
1781 #define AR_BT_PRIORITY_TIME 0x00fc0000
1782 #define AR_BT_PRIORITY_TIME_S 18
1783 #define AR_BT_FIRST_SLOT_TIME 0xff000000
1784 #define AR_BT_FIRST_SLOT_TIME_S 24
1786 #define AR_BT_COEX_WEIGHT 0x8174
1787 #define AR_BT_COEX_WGHT 0xff55
1788 #define AR_STOMP_ALL_WLAN_WGHT 0xfcfc
1789 #define AR_STOMP_LOW_WLAN_WGHT 0xa8a8
1790 #define AR_STOMP_NONE_WLAN_WGHT 0x0000
1791 #define AR_BTCOEX_BT_WGHT 0x0000ffff
1792 #define AR_BTCOEX_BT_WGHT_S 0
1793 #define AR_BTCOEX_WL_WGHT 0xffff0000
1794 #define AR_BTCOEX_WL_WGHT_S 16
1796 #define AR_BT_COEX_WL_WEIGHTS0 0x8174
1797 #define AR_BT_COEX_WL_WEIGHTS1 0x81c4
1798 #define AR_MCI_COEX_WL_WEIGHTS(_i) (0x18b0 + (_i << 2))
1799 #define AR_BT_COEX_BT_WEIGHTS(_i) (0x83ac + (_i << 2))
1801 #define AR9300_BT_WGHT 0xcccc4444
1803 #define AR_BT_COEX_MODE2 0x817c
1804 #define AR_BT_BCN_MISS_THRESH 0x000000ff
1805 #define AR_BT_BCN_MISS_THRESH_S 0
1806 #define AR_BT_BCN_MISS_CNT 0x0000ff00
1807 #define AR_BT_BCN_MISS_CNT_S 8
1808 #define AR_BT_HOLD_RX_CLEAR 0x00010000
1809 #define AR_BT_HOLD_RX_CLEAR_S 16
1810 #define AR_BT_DISABLE_BT_ANT 0x00100000
1811 #define AR_BT_DISABLE_BT_ANT_S 20
1813 #define AR_TXSIFS 0x81d0
1814 #define AR_TXSIFS_TIME 0x000000FF
1815 #define AR_TXSIFS_TX_LATENCY 0x00000F00
1816 #define AR_TXSIFS_TX_LATENCY_S 8
1817 #define AR_TXSIFS_ACK_SHIFT 0x00007000
1818 #define AR_TXSIFS_ACK_SHIFT_S 12
1820 #define AR_TXOP_X 0x81ec
1821 #define AR_TXOP_X_VAL 0x000000FF
1824 #define AR_TXOP_0_3 0x81f0
1825 #define AR_TXOP_4_7 0x81f4
1826 #define AR_TXOP_8_11 0x81f8
1827 #define AR_TXOP_12_15 0x81fc
1829 #define AR_NEXT_NDP2_TIMER 0x8180
1830 #define AR_GEN_TIMER_BANK_1_LEN 8
1831 #define AR_FIRST_NDP_TIMER 7
1832 #define AR_NDP2_PERIOD 0x81a0
1833 #define AR_NDP2_TIMER_MODE 0x81c0
1835 #define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2))
1836 #define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0)
1837 #define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1)
1838 #define AR_NEXT_SWBA AR_GEN_TIMERS(2)
1839 #define AR_NEXT_CFP AR_GEN_TIMERS(2)
1840 #define AR_NEXT_HCF AR_GEN_TIMERS(3)
1841 #define AR_NEXT_TIM AR_GEN_TIMERS(4)
1842 #define AR_NEXT_DTIM AR_GEN_TIMERS(5)
1843 #define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6)
1844 #define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7)
1846 #define AR_BEACON_PERIOD AR_GEN_TIMERS(8)
1847 #define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9)
1848 #define AR_SWBA_PERIOD AR_GEN_TIMERS(10)
1849 #define AR_HCF_PERIOD AR_GEN_TIMERS(11)
1850 #define AR_TIM_PERIOD AR_GEN_TIMERS(12)
1851 #define AR_DTIM_PERIOD AR_GEN_TIMERS(13)
1852 #define AR_QUIET_PERIOD AR_GEN_TIMERS(14)
1853 #define AR_NDP_PERIOD AR_GEN_TIMERS(15)
1855 #define AR_TIMER_MODE 0x8240
1856 #define AR_TBTT_TIMER_EN 0x00000001
1857 #define AR_DBA_TIMER_EN 0x00000002
1858 #define AR_SWBA_TIMER_EN 0x00000004
1859 #define AR_HCF_TIMER_EN 0x00000008
1860 #define AR_TIM_TIMER_EN 0x00000010
1861 #define AR_DTIM_TIMER_EN 0x00000020
1862 #define AR_QUIET_TIMER_EN 0x00000040
1863 #define AR_NDP_TIMER_EN 0x00000080
1864 #define AR_TIMER_OVERFLOW_INDEX 0x00000700
1865 #define AR_TIMER_OVERFLOW_INDEX_S 8
1866 #define AR_TIMER_THRESH 0xFFFFF000
1867 #define AR_TIMER_THRESH_S 12
1869 #define AR_SLP32_MODE 0x8244
1870 #define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF
1871 #define AR_SLP32_ENA 0x00100000
1872 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000
1874 #define AR_SLP32_WAKE 0x8248
1875 #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF
1877 #define AR_SLP32_INC 0x824c
1878 #define AR_SLP32_TST_INC 0x000FFFFF
1880 #define AR_SLP_CNT 0x8250
1881 #define AR_SLP_CYCLE_CNT 0x8254
1883 #define AR_SLP_MIB_CTRL 0x8258
1884 #define AR_SLP_MIB_CLEAR 0x00000001
1885 #define AR_SLP_MIB_PENDING 0x00000002
1887 #define AR_MAC_PCU_LOGIC_ANALYZER 0x8264
1888 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000
1891 #define AR_2040_MODE 0x8318
1892 #define AR_2040_JOINED_RX_CLEAR 0x00000001
1895 #define AR_EXTRCCNT 0x8328
1897 #define AR_SELFGEN_MASK 0x832c
1899 #define AR_PCU_TXBUF_CTRL 0x8340
1900 #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF
1901 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700
1902 #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380
1903 #define AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE 0x500
1905 #define AR_PCU_MISC_MODE2 0x8344
1906 #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002
1907 #define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004
1909 #define AR_PCU_MISC_MODE2_RESERVED 0x00000038
1910 #define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040
1911 #define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080
1912 #define AR_PCU_MISC_MODE2_MGMT_QOS 0x0000FF00
1913 #define AR_PCU_MISC_MODE2_MGMT_QOS_S 8
1914 #define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000
1915 #define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000
1916 #define AR_PCU_MISC_MODE2_HWWAR1 0x00100000
1917 #define AR_PCU_MISC_MODE2_HWWAR2 0x02000000
1918 #define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000
1920 #define AR_PCU_MISC_MODE3 0x83d0
1922 #define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358
1923 #define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400
1924 #define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000
1925 #define AR_MAC_PCU_GEN_TIMER_TSF_SEL 0x83d8
1928 #define AR_AES_MUTE_MASK0 0x805c
1929 #define AR_AES_MUTE_MASK0_FC 0x0000FFFF
1930 #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000
1931 #define AR_AES_MUTE_MASK0_QOS_S 16
1933 #define AR_AES_MUTE_MASK1 0x8060
1934 #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF
1935 #define AR_AES_MUTE_MASK1_SEQ_S 0
1936 #define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000
1937 #define AR_AES_MUTE_MASK1_FC_MGMT_S 16
1939 #define AR_RATE_DURATION_0 0x8700
1940 #define AR_RATE_DURATION_31 0x87CC
1941 #define AR_RATE_DURATION_32 0x8780
1942 #define AR_RATE_DURATION(_n) (AR_RATE_DURATION_0 + ((_n)<<2))
1944 /* WoW - Wake On Wireless */
1946 #define AR_PMCTRL_AUX_PWR_DET 0x10000000 /* Puts Chip in L2 state */
1947 #define AR_PMCTRL_D3COLD_VAUX 0x00800000
1948 #define AR_PMCTRL_HOST_PME_EN 0x00400000 /* Send OOB WAKE_L on WoW
1950 #define AR_PMCTRL_WOW_PME_CLR 0x00200000 /* Clear WoW event */
1951 #define AR_PMCTRL_PWR_STATE_MASK 0x0f000000 /* Power State Mask */
1952 #define AR_PMCTRL_PWR_STATE_D1D3 0x0f000000 /* Activate D1 and D3 */
1953 #define AR_PMCTRL_PWR_STATE_D1D3_REAL 0x0f000000 /* Activate D1 and D3 */
1954 #define AR_PMCTRL_PWR_STATE_D0 0x08000000 /* Activate D0 */
1955 #define AR_PMCTRL_PWR_PM_CTRL_ENA 0x00008000 /* Enable power mgmt */
1957 #define AR_WOW_BEACON_TIMO_MAX 0xffffffff
1963 #define AR_WOW_PATTERN 0x825C
1964 #define AR_WOW_COUNT 0x8260
1965 #define AR_WOW_BCN_EN 0x8270
1966 #define AR_WOW_BCN_TIMO 0x8274
1967 #define AR_WOW_KEEP_ALIVE_TIMO 0x8278
1968 #define AR_WOW_KEEP_ALIVE 0x827c
1969 #define AR_WOW_US_SCALAR 0x8284
1970 #define AR_WOW_KEEP_ALIVE_DELAY 0x8288
1971 #define AR_WOW_PATTERN_MATCH 0x828c
1972 #define AR_WOW_PATTERN_OFF1 0x8290 /* pattern bytes 0 -> 3 */
1973 #define AR_WOW_PATTERN_OFF2 0x8294 /* pattern bytes 4 -> 7 */
1975 /* for AR9285 or later version of chips */
1976 #define AR_WOW_EXACT 0x829c
1977 #define AR_WOW_LENGTH1 0x8360
1978 #define AR_WOW_LENGTH2 0X8364
1979 /* register to enable match for less than 256 bytes packets */
1980 #define AR_WOW_PATTERN_MATCH_LT_256B 0x8368
1982 #define AR_SW_WOW_CONTROL 0x20018
1983 #define AR_SW_WOW_ENABLE 0x1
1984 #define AR_SWITCH_TO_REFCLK 0x2
1985 #define AR_RESET_CONTROL 0x4
1986 #define AR_RESET_VALUE_MASK 0x8
1987 #define AR_HW_WOW_DISABLE 0x10
1988 #define AR_CLR_MAC_INTERRUPT 0x20
1989 #define AR_CLR_KA_INTERRUPT 0x40
1991 /* AR_WOW_PATTERN register values */
1992 #define AR_WOW_BACK_OFF_SHIFT(x) ((x & 0xf) << 28) /* in usecs */
1993 #define AR_WOW_MAC_INTR_EN 0x00040000
1994 #define AR_WOW_MAGIC_EN 0x00010000
1995 #define AR_WOW_PATTERN_EN(x) (x & 0xff)
1996 #define AR_WOW_PAT_FOUND_SHIFT 8
1997 #define AR_WOW_PATTERN_FOUND(x) (x & (0xff << AR_WOW_PAT_FOUND_SHIFT))
1998 #define AR_WOW_PATTERN_FOUND_MASK ((0xff) << AR_WOW_PAT_FOUND_SHIFT)
1999 #define AR_WOW_MAGIC_PAT_FOUND 0x00020000
2000 #define AR_WOW_MAC_INTR 0x00080000
2001 #define AR_WOW_KEEP_ALIVE_FAIL 0x00100000
2002 #define AR_WOW_BEACON_FAIL 0x00200000
2004 #define AR_WOW_STATUS(x) (x & (AR_WOW_PATTERN_FOUND_MASK | \
2005 AR_WOW_MAGIC_PAT_FOUND | \
2006 AR_WOW_KEEP_ALIVE_FAIL | \
2007 AR_WOW_BEACON_FAIL))
2008 #define AR_WOW_CLEAR_EVENTS(x) (x & ~(AR_WOW_PATTERN_EN(0xff) | \
2010 AR_WOW_MAC_INTR_EN | \
2011 AR_WOW_BEACON_FAIL | \
2012 AR_WOW_KEEP_ALIVE_FAIL))
2014 /* AR_WOW_COUNT register values */
2015 #define AR_WOW_AIFS_CNT(x) (x & 0xff)
2016 #define AR_WOW_SLOT_CNT(x) ((x & 0xff) << 8)
2017 #define AR_WOW_KEEP_ALIVE_CNT(x) ((x & 0xff) << 16)
2019 /* AR_WOW_BCN_EN register */
2020 #define AR_WOW_BEACON_FAIL_EN 0x00000001
2022 /* AR_WOW_BCN_TIMO rgister */
2023 #define AR_WOW_BEACON_TIMO 0x40000000 /* valid if BCN_EN is set */
2025 /* AR_WOW_KEEP_ALIVE_TIMO register */
2026 #define AR_WOW_KEEP_ALIVE_TIMO_VALUE
2027 #define AR_WOW_KEEP_ALIVE_NEVER 0xffffffff
2029 /* AR_WOW_KEEP_ALIVE register */
2030 #define AR_WOW_KEEP_ALIVE_AUTO_DIS 0x00000001
2031 #define AR_WOW_KEEP_ALIVE_FAIL_DIS 0x00000002
2033 /* AR_WOW_KEEP_ALIVE_DELAY register */
2034 #define AR_WOW_KEEP_ALIVE_DELAY_VALUE 0x000003e8 /* 1 msec */
2038 * keep it long for beacon workaround - ensure no false alarm
2040 #define AR_WOW_BMISSTHRESHOLD 0x20
2042 /* AR_WOW_PATTERN_MATCH register */
2043 #define AR_WOW_PAT_END_OF_PKT(x) (x & 0xf)
2044 #define AR_WOW_PAT_OFF_MATCH(x) ((x & 0xf) << 8)
2047 * default values for Wow Configuration for backoff, aifs, slot, keep-alive
2048 * to be programmed into various registers.
2050 #define AR_WOW_PAT_BACKOFF 0x00000004 /* AR_WOW_PATTERN_REG */
2051 #define AR_WOW_CNT_AIFS_CNT 0x00000022 /* AR_WOW_COUNT_REG */
2052 #define AR_WOW_CNT_SLOT_CNT 0x00000009 /* AR_WOW_COUNT_REG */
2054 * Keepalive count applicable for AR9280 2.0 and above.
2056 #define AR_WOW_CNT_KA_CNT 0x00000008 /* AR_WOW_COUNT register */
2058 /* WoW - Transmit buffer for keep alive frames */
2059 #define AR_WOW_TRANSMIT_BUFFER 0xe000 /* E000 - EFFC */
2061 #define AR_WOW_TXBUF(i) (AR_WOW_TRANSMIT_BUFFER + ((i) << 2))
2063 #define AR_WOW_KA_DESC_WORD2 0xe000
2065 #define AR_WOW_KA_DATA_WORD0 0xe030
2067 /* WoW Transmit Buffer for patterns */
2068 #define AR_WOW_TB_PATTERN(i) (0xe100 + (i << 8))
2069 #define AR_WOW_TB_MASK(i) (0xec00 + (i << 5))
2071 /* Currently Pattern 0-7 are supported - so bit 0-7 are set */
2072 #define AR_WOW_PATTERN_SUPPORTED 0xff
2073 #define AR_WOW_LENGTH_MAX 0xff
2074 #define AR_WOW_LEN1_SHIFT(_i) ((0x3 - ((_i) & 0x3)) << 0x3)
2075 #define AR_WOW_LENGTH1_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN1_SHIFT(_i))
2076 #define AR_WOW_LEN2_SHIFT(_i) ((0x7 - ((_i) & 0x7)) << 0x3)
2077 #define AR_WOW_LENGTH2_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN2_SHIFT(_i))
2079 #define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */
2080 #define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
2082 #define AR_AGG_WEP_ENABLE_FIX 0x00000008 /* This allows the use of AR_AGG_WEP_ENABLE */
2083 #define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search
2084 * based on both MAC Address and Key ID.
2085 * If bit is 0, then Multicast search is
2086 * based on MAC address only.
2087 * For Merlin and above only.
2089 #define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature,
2090 * when it is enable, AGG_WEP would takes
2091 * charge of the encryption interface of
2095 #define AR9300_SM_BASE 0xa200
2096 #define AR9002_PHY_AGC_CONTROL 0x9860
2097 #define AR9003_PHY_AGC_CONTROL AR9300_SM_BASE + 0xc4
2098 #define AR_PHY_AGC_CONTROL (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL)
2099 #define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */
2100 #define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */
2101 #define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */
2102 #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */
2103 #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */
2104 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */
2105 #define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */
2106 #define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */
2107 #define AR_PHY_AGC_CONTROL_PKDET_CAL 0x00100000
2108 #define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0
2109 #define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6
2113 #define AR_MCI_COMMAND0 0x1800
2114 #define AR_MCI_COMMAND0_HEADER 0xFF
2115 #define AR_MCI_COMMAND0_HEADER_S 0
2116 #define AR_MCI_COMMAND0_LEN 0x1f00
2117 #define AR_MCI_COMMAND0_LEN_S 8
2118 #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000
2119 #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S 13
2121 #define AR_MCI_COMMAND1 0x1804
2123 #define AR_MCI_COMMAND2 0x1808
2124 #define AR_MCI_COMMAND2_RESET_TX 0x01
2125 #define AR_MCI_COMMAND2_RESET_TX_S 0
2126 #define AR_MCI_COMMAND2_RESET_RX 0x02
2127 #define AR_MCI_COMMAND2_RESET_RX_S 1
2128 #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES 0x3FC
2129 #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S 2
2130 #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP 0x400
2131 #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S 10
2133 #define AR_MCI_RX_CTRL 0x180c
2135 #define AR_MCI_TX_CTRL 0x1810
2136 /* 0 = no division, 1 = divide by 2, 2 = divide by 4, 3 = divide by 8 */
2137 #define AR_MCI_TX_CTRL_CLK_DIV 0x03
2138 #define AR_MCI_TX_CTRL_CLK_DIV_S 0
2139 #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE 0x04
2140 #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S 2
2141 #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ 0xFFFFF8
2142 #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S 3
2143 #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM 0xF000000
2144 #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S 24
2146 #define AR_MCI_MSG_ATTRIBUTES_TABLE 0x1814
2147 #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM 0xFFFF
2148 #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S 0
2149 #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR 0xFFFF0000
2150 #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S 16
2152 #define AR_MCI_SCHD_TABLE_0 0x1818
2153 #define AR_MCI_SCHD_TABLE_1 0x181c
2154 #define AR_MCI_GPM_0 0x1820
2155 #define AR_MCI_GPM_1 0x1824
2156 #define AR_MCI_GPM_WRITE_PTR 0xFFFF0000
2157 #define AR_MCI_GPM_WRITE_PTR_S 16
2158 #define AR_MCI_GPM_BUF_LEN 0x0000FFFF
2159 #define AR_MCI_GPM_BUF_LEN_S 0
2161 #define AR_MCI_INTERRUPT_RAW 0x1828
2162 #define AR_MCI_INTERRUPT_EN 0x182c
2163 #define AR_MCI_INTERRUPT_SW_MSG_DONE 0x00000001
2164 #define AR_MCI_INTERRUPT_SW_MSG_DONE_S 0
2165 #define AR_MCI_INTERRUPT_CPU_INT_MSG 0x00000002
2166 #define AR_MCI_INTERRUPT_CPU_INT_MSG_S 1
2167 #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL 0x00000004
2168 #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S 2
2169 #define AR_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008
2170 #define AR_MCI_INTERRUPT_RX_INVALID_HDR_S 3
2171 #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010
2172 #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S 4
2173 #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020
2174 #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S 5
2175 #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080
2176 #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S 7
2177 #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100
2178 #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S 8
2179 #define AR_MCI_INTERRUPT_RX_MSG 0x00000200
2180 #define AR_MCI_INTERRUPT_RX_MSG_S 9
2181 #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400
2182 #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S 10
2183 #define AR_MCI_INTERRUPT_BT_PRI 0x07fff800
2184 #define AR_MCI_INTERRUPT_BT_PRI_S 11
2185 #define AR_MCI_INTERRUPT_BT_PRI_THRESH 0x08000000
2186 #define AR_MCI_INTERRUPT_BT_PRI_THRESH_S 27
2187 #define AR_MCI_INTERRUPT_BT_FREQ 0x10000000
2188 #define AR_MCI_INTERRUPT_BT_FREQ_S 28
2189 #define AR_MCI_INTERRUPT_BT_STOMP 0x20000000
2190 #define AR_MCI_INTERRUPT_BT_STOMP_S 29
2191 #define AR_MCI_INTERRUPT_BB_AIC_IRQ 0x40000000
2192 #define AR_MCI_INTERRUPT_BB_AIC_IRQ_S 30
2193 #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000
2194 #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S 31
2196 #define AR_MCI_INTERRUPT_DEFAULT (AR_MCI_INTERRUPT_SW_MSG_DONE | \
2197 AR_MCI_INTERRUPT_RX_INVALID_HDR | \
2198 AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \
2199 AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \
2200 AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \
2201 AR_MCI_INTERRUPT_TX_SW_MSG_FAIL | \
2202 AR_MCI_INTERRUPT_RX_MSG | \
2203 AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE | \
2204 AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)
2206 #define AR_MCI_INTERRUPT_MSG_FAIL_MASK (AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \
2207 AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \
2208 AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \
2209 AR_MCI_INTERRUPT_TX_SW_MSG_FAIL)
2211 #define AR_MCI_REMOTE_CPU_INT 0x1830
2212 #define AR_MCI_REMOTE_CPU_INT_EN 0x1834
2213 #define AR_MCI_INTERRUPT_RX_MSG_RAW 0x1838
2214 #define AR_MCI_INTERRUPT_RX_MSG_EN 0x183c
2215 #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001
2216 #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0
2217 #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002
2218 #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1
2219 #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004
2220 #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2
2221 #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008
2222 #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3
2223 #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010
2224 #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4
2225 #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020
2226 #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5
2227 #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040
2228 #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6
2229 #define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100
2230 #define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8
2231 #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200
2232 #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9
2233 #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400
2234 #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10
2235 #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800
2236 #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11
2237 #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000
2238 #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12
2239 #define AR_MCI_INTERRUPT_RX_HW_MSG_MASK (AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \
2240 AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL| \
2241 AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \
2242 AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \
2243 AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \
2244 AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
2246 #define AR_MCI_INTERRUPT_RX_MSG_DEFAULT (AR_MCI_INTERRUPT_RX_MSG_GPM | \
2247 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET| \
2248 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \
2249 AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING| \
2250 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)
2252 #define AR_MCI_CPU_INT 0x1840
2254 #define AR_MCI_RX_STATUS 0x1844
2255 #define AR_MCI_RX_LAST_SCHD_MSG_INDEX 0x00000F00
2256 #define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S 8
2257 #define AR_MCI_RX_REMOTE_SLEEP 0x00001000
2258 #define AR_MCI_RX_REMOTE_SLEEP_S 12
2259 #define AR_MCI_RX_MCI_CLK_REQ 0x00002000
2260 #define AR_MCI_RX_MCI_CLK_REQ_S 13
2262 #define AR_MCI_CONT_STATUS 0x1848
2263 #define AR_MCI_CONT_RSSI_POWER 0x000000FF
2264 #define AR_MCI_CONT_RSSI_POWER_S 0
2265 #define AR_MCI_CONT_PRIORITY 0x0000FF00
2266 #define AR_MCI_CONT_PRIORITY_S 8
2267 #define AR_MCI_CONT_TXRX 0x00010000
2268 #define AR_MCI_CONT_TXRX_S 16
2270 #define AR_MCI_BT_PRI0 0x184c
2271 #define AR_MCI_BT_PRI1 0x1850
2272 #define AR_MCI_BT_PRI2 0x1854
2273 #define AR_MCI_BT_PRI3 0x1858
2274 #define AR_MCI_BT_PRI 0x185c
2275 #define AR_MCI_WL_FREQ0 0x1860
2276 #define AR_MCI_WL_FREQ1 0x1864
2277 #define AR_MCI_WL_FREQ2 0x1868
2278 #define AR_MCI_GAIN 0x186c
2279 #define AR_MCI_WBTIMER1 0x1870
2280 #define AR_MCI_WBTIMER2 0x1874
2281 #define AR_MCI_WBTIMER3 0x1878
2282 #define AR_MCI_WBTIMER4 0x187c
2283 #define AR_MCI_MAXGAIN 0x1880
2284 #define AR_MCI_HW_SCHD_TBL_CTL 0x1884
2285 #define AR_MCI_HW_SCHD_TBL_D0 0x1888
2286 #define AR_MCI_HW_SCHD_TBL_D1 0x188c
2287 #define AR_MCI_HW_SCHD_TBL_D2 0x1890
2288 #define AR_MCI_HW_SCHD_TBL_D3 0x1894
2289 #define AR_MCI_TX_PAYLOAD0 0x1898
2290 #define AR_MCI_TX_PAYLOAD1 0x189c
2291 #define AR_MCI_TX_PAYLOAD2 0x18a0
2292 #define AR_MCI_TX_PAYLOAD3 0x18a4
2293 #define AR_BTCOEX_WBTIMER 0x18a8
2295 #define AR_BTCOEX_CTRL 0x18ac
2296 #define AR_BTCOEX_CTRL_AR9462_MODE 0x00000001
2297 #define AR_BTCOEX_CTRL_AR9462_MODE_S 0
2298 #define AR_BTCOEX_CTRL_WBTIMER_EN 0x00000002
2299 #define AR_BTCOEX_CTRL_WBTIMER_EN_S 1
2300 #define AR_BTCOEX_CTRL_MCI_MODE_EN 0x00000004
2301 #define AR_BTCOEX_CTRL_MCI_MODE_EN_S 2
2302 #define AR_BTCOEX_CTRL_LNA_SHARED 0x00000008
2303 #define AR_BTCOEX_CTRL_LNA_SHARED_S 3
2304 #define AR_BTCOEX_CTRL_PA_SHARED 0x00000010
2305 #define AR_BTCOEX_CTRL_PA_SHARED_S 4
2306 #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN 0x00000020
2307 #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S 5
2308 #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN 0x00000040
2309 #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S 6
2310 #define AR_BTCOEX_CTRL_NUM_ANTENNAS 0x00000180
2311 #define AR_BTCOEX_CTRL_NUM_ANTENNAS_S 7
2312 #define AR_BTCOEX_CTRL_RX_CHAIN_MASK 0x00000E00
2313 #define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S 9
2314 #define AR_BTCOEX_CTRL_AGGR_THRESH 0x00007000
2315 #define AR_BTCOEX_CTRL_AGGR_THRESH_S 12
2316 #define AR_BTCOEX_CTRL_1_CHAIN_BCN 0x00080000
2317 #define AR_BTCOEX_CTRL_1_CHAIN_BCN_S 19
2318 #define AR_BTCOEX_CTRL_1_CHAIN_ACK 0x00100000
2319 #define AR_BTCOEX_CTRL_1_CHAIN_ACK_S 20
2320 #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN 0x1FE00000
2321 #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S 28
2322 #define AR_BTCOEX_CTRL_REDUCE_TXPWR 0x20000000
2323 #define AR_BTCOEX_CTRL_REDUCE_TXPWR_S 29
2324 #define AR_BTCOEX_CTRL_SPDT_ENABLE_10 0x40000000
2325 #define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S 30
2326 #define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000
2327 #define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31
2329 #define AR_BTCOEX_MAX_TXPWR(_x) (0x18c0 + ((_x) << 2))
2330 #define AR_BTCOEX_WL_LNA 0x1940
2331 #define AR_BTCOEX_RFGAIN_CTRL 0x1944
2332 #define AR_BTCOEX_WL_LNA_TIMEOUT 0x003FFFFF
2333 #define AR_BTCOEX_WL_LNA_TIMEOUT_S 0
2335 #define AR_BTCOEX_CTRL2 0x1948
2336 #define AR_BTCOEX_CTRL2_TXPWR_THRESH 0x0007F800
2337 #define AR_BTCOEX_CTRL2_TXPWR_THRESH_S 11
2338 #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK 0x00380000
2339 #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S 19
2340 #define AR_BTCOEX_CTRL2_RX_DEWEIGHT 0x00400000
2341 #define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S 22
2342 #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL 0x00800000
2343 #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S 23
2344 #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL 0x01000000
2345 #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S 24
2346 #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE 0x02000000
2347 #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S 25
2349 #define AR_BTCOEX_CTRL_SPDT_ENABLE 0x00000001
2350 #define AR_BTCOEX_CTRL_SPDT_ENABLE_S 0
2351 #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL 0x00000002
2352 #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S 1
2353 #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT 0x00000004
2354 #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S 2
2355 #define AR_GLB_WLAN_UART_INTF_EN 0x00020000
2356 #define AR_GLB_WLAN_UART_INTF_EN_S 17
2357 #define AR_GLB_DS_JTAG_DISABLE 0x00040000
2358 #define AR_GLB_DS_JTAG_DISABLE_S 18
2360 #define AR_BTCOEX_RC 0x194c
2361 #define AR_BTCOEX_MAX_RFGAIN(_x) (0x1950 + ((_x) << 2))
2362 #define AR_BTCOEX_DBG 0x1a50
2363 #define AR_MCI_LAST_HW_MSG_HDR 0x1a54
2364 #define AR_MCI_LAST_HW_MSG_BDY 0x1a58
2366 #define AR_MCI_SCHD_TABLE_2 0x1a5c
2367 #define AR_MCI_SCHD_TABLE_2_MEM_BASED 0x00000001
2368 #define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0
2369 #define AR_MCI_SCHD_TABLE_2_HW_BASED 0x00000002
2370 #define AR_MCI_SCHD_TABLE_2_HW_BASED_S 1
2372 #define AR_BTCOEX_CTRL3 0x1a60
2373 #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000fff
2374 #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0
2376 #define AR_GLB_SWREG_DISCONT_MODE 0x2002c
2377 #define AR_GLB_SWREG_DISCONT_EN_BT_WLAN 0x3
2379 #define AR_MCI_MISC 0x1a74
2380 #define AR_MCI_MISC_HW_FIX_EN 0x00000001
2381 #define AR_MCI_MISC_HW_FIX_EN_S 0
2382 #define AR_MCI_DBG_CNT_CTRL 0x1a78
2383 #define AR_MCI_DBG_CNT_CTRL_ENABLE 0x00000001
2384 #define AR_MCI_DBG_CNT_CTRL_ENABLE_S 0