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ARM: mm: Recreate kernel mappings in early_paging_init()
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / xmit.c
blob35b515fe3ffa41e00dc614b6590cc2eabead9de4
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF 8
25 #define L_LTF 8
26 #define L_SIG 4
27 #define HT_SIG 8
28 #define HT_STF 4
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36
37
38 static u16 bits_per_symbol[][2] = {
39 /* 20MHz 40MHz */
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 };
49
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
51
52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 struct ath_atx_tid *tid, struct sk_buff *skb);
54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 struct ath_txq *txq, struct list_head *bf_q,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
63 int txok);
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 int seqno);
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
67 struct ath_txq *txq,
68 struct ath_atx_tid *tid,
69 struct sk_buff *skb);
70
71 enum {
72 MCS_HT20,
73 MCS_HT20_SGI,
74 MCS_HT40,
75 MCS_HT40_SGI,
76 };
77
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
81
82 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 __acquires(&txq->axq_lock)
84 {
85 spin_lock_bh(&txq->axq_lock);
86 }
87
88 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 __releases(&txq->axq_lock)
90 {
91 spin_unlock_bh(&txq->axq_lock);
92 }
93
94 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 __releases(&txq->axq_lock)
96 {
97 struct sk_buff_head q;
98 struct sk_buff *skb;
99
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
103
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
106 }
107
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
109 {
110 struct ath_atx_ac *ac = tid->ac;
111
112 if (tid->paused)
113 return;
114
115 if (tid->sched)
116 return;
117
118 tid->sched = true;
119 list_add_tail(&tid->list, &ac->tid_q);
120
121 if (ac->sched)
122 return;
123
124 ac->sched = true;
125 list_add_tail(&ac->list, &txq->axq_acq);
126 }
127
128 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
129 {
130 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
131 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 sizeof(tx_info->rate_driver_data));
133 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
134 }
135
136 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
137 {
138 if (!tid->an->sta)
139 return;
140
141 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
142 seqno << IEEE80211_SEQ_SEQ_SHIFT);
143 }
144
145 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
146 struct ath_buf *bf)
147 {
148 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
149 ARRAY_SIZE(bf->rates));
150 }
151
152 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
153 struct sk_buff *skb)
154 {
155 int q;
156
157 q = skb_get_queue_mapping(skb);
158 if (txq == sc->tx.uapsdq)
159 txq = sc->tx.txq_map[q];
160
161 if (txq != sc->tx.txq_map[q])
162 return;
163
164 if (WARN_ON(--txq->pending_frames < 0))
165 txq->pending_frames = 0;
166
167 if (txq->stopped &&
168 txq->pending_frames < sc->tx.txq_max_pending[q]) {
169 ieee80211_wake_queue(sc->hw, q);
170 txq->stopped = false;
171 }
172 }
173
174 static struct ath_atx_tid *
175 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
176 {
177 struct ieee80211_hdr *hdr;
178 u8 tidno = 0;
179
180 hdr = (struct ieee80211_hdr *) skb->data;
181 if (ieee80211_is_data_qos(hdr->frame_control))
182 tidno = ieee80211_get_qos_ctl(hdr)[0];
183
184 tidno &= IEEE80211_QOS_CTL_TID_MASK;
185 return ATH_AN_2_TID(an, tidno);
186 }
187
188 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
189 {
190 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
191 }
192
193 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
194 {
195 struct sk_buff *skb;
196
197 skb = __skb_dequeue(&tid->retry_q);
198 if (!skb)
199 skb = __skb_dequeue(&tid->buf_q);
200
201 return skb;
202 }
203
204 /*
205 * ath_tx_tid_change_state:
206 * - clears a-mpdu flag of previous session
207 * - force sequence number allocation to fix next BlockAck Window
208 */
209 static void
210 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
211 {
212 struct ath_txq *txq = tid->ac->txq;
213 struct ieee80211_tx_info *tx_info;
214 struct sk_buff *skb, *tskb;
215 struct ath_buf *bf;
216 struct ath_frame_info *fi;
217
218 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
219 fi = get_frame_info(skb);
220 bf = fi->bf;
221
222 tx_info = IEEE80211_SKB_CB(skb);
223 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
224
225 if (bf)
226 continue;
227
228 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
229 if (!bf) {
230 __skb_unlink(skb, &tid->buf_q);
231 ath_txq_skb_done(sc, txq, skb);
232 ieee80211_free_txskb(sc->hw, skb);
233 continue;
234 }
235 }
236
237 }
238
239 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
240 {
241 struct ath_txq *txq = tid->ac->txq;
242 struct sk_buff *skb;
243 struct ath_buf *bf;
244 struct list_head bf_head;
245 struct ath_tx_status ts;
246 struct ath_frame_info *fi;
247 bool sendbar = false;
248
249 INIT_LIST_HEAD(&bf_head);
250
251 memset(&ts, 0, sizeof(ts));
252
253 while ((skb = __skb_dequeue(&tid->retry_q))) {
254 fi = get_frame_info(skb);
255 bf = fi->bf;
256 if (!bf) {
257 ath_txq_skb_done(sc, txq, skb);
258 ieee80211_free_txskb(sc->hw, skb);
259 continue;
260 }
261
262 if (fi->baw_tracked) {
263 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
264 sendbar = true;
265 }
266
267 list_add_tail(&bf->list, &bf_head);
268 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
269 }
270
271 if (sendbar) {
272 ath_txq_unlock(sc, txq);
273 ath_send_bar(tid, tid->seq_start);
274 ath_txq_lock(sc, txq);
275 }
276 }
277
278 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
279 int seqno)
280 {
281 int index, cindex;
282
283 index = ATH_BA_INDEX(tid->seq_start, seqno);
284 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
285
286 __clear_bit(cindex, tid->tx_buf);
287
288 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
289 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
290 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
291 if (tid->bar_index >= 0)
292 tid->bar_index--;
293 }
294 }
295
296 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
297 struct ath_buf *bf)
298 {
299 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
300 u16 seqno = bf->bf_state.seqno;
301 int index, cindex;
302
303 index = ATH_BA_INDEX(tid->seq_start, seqno);
304 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
305 __set_bit(cindex, tid->tx_buf);
306 fi->baw_tracked = 1;
307
308 if (index >= ((tid->baw_tail - tid->baw_head) &
309 (ATH_TID_MAX_BUFS - 1))) {
310 tid->baw_tail = cindex;
311 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
312 }
313 }
314
315 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
316 struct ath_atx_tid *tid)
317
318 {
319 struct sk_buff *skb;
320 struct ath_buf *bf;
321 struct list_head bf_head;
322 struct ath_tx_status ts;
323 struct ath_frame_info *fi;
324
325 memset(&ts, 0, sizeof(ts));
326 INIT_LIST_HEAD(&bf_head);
327
328 while ((skb = ath_tid_dequeue(tid))) {
329 fi = get_frame_info(skb);
330 bf = fi->bf;
331
332 if (!bf) {
333 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
334 continue;
335 }
336
337 list_add_tail(&bf->list, &bf_head);
338 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
339 }
340 }
341
342 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
343 struct sk_buff *skb, int count)
344 {
345 struct ath_frame_info *fi = get_frame_info(skb);
346 struct ath_buf *bf = fi->bf;
347 struct ieee80211_hdr *hdr;
348 int prev = fi->retries;
349
350 TX_STAT_INC(txq->axq_qnum, a_retries);
351 fi->retries += count;
352
353 if (prev > 0)
354 return;
355
356 hdr = (struct ieee80211_hdr *)skb->data;
357 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
358 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
359 sizeof(*hdr), DMA_TO_DEVICE);
360 }
361
362 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
363 {
364 struct ath_buf *bf = NULL;
365
366 spin_lock_bh(&sc->tx.txbuflock);
367
368 if (unlikely(list_empty(&sc->tx.txbuf))) {
369 spin_unlock_bh(&sc->tx.txbuflock);
370 return NULL;
371 }
372
373 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
374 list_del(&bf->list);
375
376 spin_unlock_bh(&sc->tx.txbuflock);
377
378 return bf;
379 }
380
381 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
382 {
383 spin_lock_bh(&sc->tx.txbuflock);
384 list_add_tail(&bf->list, &sc->tx.txbuf);
385 spin_unlock_bh(&sc->tx.txbuflock);
386 }
387
388 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
389 {
390 struct ath_buf *tbf;
391
392 tbf = ath_tx_get_buffer(sc);
393 if (WARN_ON(!tbf))
394 return NULL;
395
396 ATH_TXBUF_RESET(tbf);
397
398 tbf->bf_mpdu = bf->bf_mpdu;
399 tbf->bf_buf_addr = bf->bf_buf_addr;
400 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
401 tbf->bf_state = bf->bf_state;
402
403 return tbf;
404 }
405
406 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
407 struct ath_tx_status *ts, int txok,
408 int *nframes, int *nbad)
409 {
410 struct ath_frame_info *fi;
411 u16 seq_st = 0;
412 u32 ba[WME_BA_BMP_SIZE >> 5];
413 int ba_index;
414 int isaggr = 0;
415
416 *nbad = 0;
417 *nframes = 0;
418
419 isaggr = bf_isaggr(bf);
420 if (isaggr) {
421 seq_st = ts->ts_seqnum;
422 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
423 }
424
425 while (bf) {
426 fi = get_frame_info(bf->bf_mpdu);
427 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
428
429 (*nframes)++;
430 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
431 (*nbad)++;
432
433 bf = bf->bf_next;
434 }
435 }
436
437
438 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
439 struct ath_buf *bf, struct list_head *bf_q,
440 struct ath_tx_status *ts, int txok)
441 {
442 struct ath_node *an = NULL;
443 struct sk_buff *skb;
444 struct ieee80211_sta *sta;
445 struct ieee80211_hw *hw = sc->hw;
446 struct ieee80211_hdr *hdr;
447 struct ieee80211_tx_info *tx_info;
448 struct ath_atx_tid *tid = NULL;
449 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
450 struct list_head bf_head;
451 struct sk_buff_head bf_pending;
452 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
453 u32 ba[WME_BA_BMP_SIZE >> 5];
454 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
455 bool rc_update = true, isba;
456 struct ieee80211_tx_rate rates[4];
457 struct ath_frame_info *fi;
458 int nframes;
459 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
460 int i, retries;
461 int bar_index = -1;
462
463 skb = bf->bf_mpdu;
464 hdr = (struct ieee80211_hdr *)skb->data;
465
466 tx_info = IEEE80211_SKB_CB(skb);
467
468 memcpy(rates, bf->rates, sizeof(rates));
469
470 retries = ts->ts_longretry + 1;
471 for (i = 0; i < ts->ts_rateindex; i++)
472 retries += rates[i].count;
473
474 rcu_read_lock();
475
476 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
477 if (!sta) {
478 rcu_read_unlock();
479
480 INIT_LIST_HEAD(&bf_head);
481 while (bf) {
482 bf_next = bf->bf_next;
483
484 if (!bf->bf_state.stale || bf_next != NULL)
485 list_move_tail(&bf->list, &bf_head);
486
487 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
488
489 bf = bf_next;
490 }
491 return;
492 }
493
494 an = (struct ath_node *)sta->drv_priv;
495 tid = ath_get_skb_tid(sc, an, skb);
496 seq_first = tid->seq_start;
497 isba = ts->ts_flags & ATH9K_TX_BA;
498
499 /*
500 * The hardware occasionally sends a tx status for the wrong TID.
501 * In this case, the BA status cannot be considered valid and all
502 * subframes need to be retransmitted
503 *
504 * Only BlockAcks have a TID and therefore normal Acks cannot be
505 * checked
506 */
507 if (isba && tid->tidno != ts->tid)
508 txok = false;
509
510 isaggr = bf_isaggr(bf);
511 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
512
513 if (isaggr && txok) {
514 if (ts->ts_flags & ATH9K_TX_BA) {
515 seq_st = ts->ts_seqnum;
516 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
517 } else {
518 /*
519 * AR5416 can become deaf/mute when BA
520 * issue happens. Chip needs to be reset.
521 * But AP code may have sychronization issues
522 * when perform internal reset in this routine.
523 * Only enable reset in STA mode for now.
524 */
525 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
526 needreset = 1;
527 }
528 }
529
530 __skb_queue_head_init(&bf_pending);
531
532 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
533 while (bf) {
534 u16 seqno = bf->bf_state.seqno;
535
536 txfail = txpending = sendbar = 0;
537 bf_next = bf->bf_next;
538
539 skb = bf->bf_mpdu;
540 tx_info = IEEE80211_SKB_CB(skb);
541 fi = get_frame_info(skb);
542
543 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
544 !tid->active) {
545 /*
546 * Outside of the current BlockAck window,
547 * maybe part of a previous session
548 */
549 txfail = 1;
550 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
551 /* transmit completion, subframe is
552 * acked by block ack */
553 acked_cnt++;
554 } else if (!isaggr && txok) {
555 /* transmit completion */
556 acked_cnt++;
557 } else if (flush) {
558 txpending = 1;
559 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
560 if (txok || !an->sleeping)
561 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
562 retries);
563
564 txpending = 1;
565 } else {
566 txfail = 1;
567 txfail_cnt++;
568 bar_index = max_t(int, bar_index,
569 ATH_BA_INDEX(seq_first, seqno));
570 }
571
572 /*
573 * Make sure the last desc is reclaimed if it
574 * not a holding desc.
575 */
576 INIT_LIST_HEAD(&bf_head);
577 if (bf_next != NULL || !bf_last->bf_state.stale)
578 list_move_tail(&bf->list, &bf_head);
579
580 if (!txpending) {
581 /*
582 * complete the acked-ones/xretried ones; update
583 * block-ack window
584 */
585 ath_tx_update_baw(sc, tid, seqno);
586
587 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
588 memcpy(tx_info->control.rates, rates, sizeof(rates));
589 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
590 rc_update = false;
591 }
592
593 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
594 !txfail);
595 } else {
596 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
597 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
598 ieee80211_sta_eosp(sta);
599 }
600 /* retry the un-acked ones */
601 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
602 struct ath_buf *tbf;
603
604 tbf = ath_clone_txbuf(sc, bf_last);
605 /*
606 * Update tx baw and complete the
607 * frame with failed status if we
608 * run out of tx buf.
609 */
610 if (!tbf) {
611 ath_tx_update_baw(sc, tid, seqno);
612
613 ath_tx_complete_buf(sc, bf, txq,
614 &bf_head, ts, 0);
615 bar_index = max_t(int, bar_index,
616 ATH_BA_INDEX(seq_first, seqno));
617 break;
618 }
619
620 fi->bf = tbf;
621 }
622
623 /*
624 * Put this buffer to the temporary pending
625 * queue to retain ordering
626 */
627 __skb_queue_tail(&bf_pending, skb);
628 }
629
630 bf = bf_next;
631 }
632
633 /* prepend un-acked frames to the beginning of the pending frame queue */
634 if (!skb_queue_empty(&bf_pending)) {
635 if (an->sleeping)
636 ieee80211_sta_set_buffered(sta, tid->tidno, true);
637
638 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
639 if (!an->sleeping) {
640 ath_tx_queue_tid(txq, tid);
641
642 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
643 tid->ac->clear_ps_filter = true;
644 }
645 }
646
647 if (bar_index >= 0) {
648 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
649
650 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
651 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
652
653 ath_txq_unlock(sc, txq);
654 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
655 ath_txq_lock(sc, txq);
656 }
657
658 rcu_read_unlock();
659
660 if (needreset)
661 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
662 }
663
664 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
665 {
666 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
667 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
668 }
669
670 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
671 struct ath_tx_status *ts, struct ath_buf *bf,
672 struct list_head *bf_head)
673 {
674 struct ieee80211_tx_info *info;
675 bool txok, flush;
676
677 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
678 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
679 txq->axq_tx_inprogress = false;
680
681 txq->axq_depth--;
682 if (bf_is_ampdu_not_probing(bf))
683 txq->axq_ampdu_depth--;
684
685 if (!bf_isampdu(bf)) {
686 if (!flush) {
687 info = IEEE80211_SKB_CB(bf->bf_mpdu);
688 memcpy(info->control.rates, bf->rates,
689 sizeof(info->control.rates));
690 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
691 }
692 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
693 } else
694 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
695
696 if (!flush)
697 ath_txq_schedule(sc, txq);
698 }
699
700 static bool ath_lookup_legacy(struct ath_buf *bf)
701 {
702 struct sk_buff *skb;
703 struct ieee80211_tx_info *tx_info;
704 struct ieee80211_tx_rate *rates;
705 int i;
706
707 skb = bf->bf_mpdu;
708 tx_info = IEEE80211_SKB_CB(skb);
709 rates = tx_info->control.rates;
710
711 for (i = 0; i < 4; i++) {
712 if (!rates[i].count || rates[i].idx < 0)
713 break;
714
715 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
716 return true;
717 }
718
719 return false;
720 }
721
722 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
723 struct ath_atx_tid *tid)
724 {
725 struct sk_buff *skb;
726 struct ieee80211_tx_info *tx_info;
727 struct ieee80211_tx_rate *rates;
728 u32 max_4ms_framelen, frmlen;
729 u16 aggr_limit, bt_aggr_limit, legacy = 0;
730 int q = tid->ac->txq->mac80211_qnum;
731 int i;
732
733 skb = bf->bf_mpdu;
734 tx_info = IEEE80211_SKB_CB(skb);
735 rates = bf->rates;
736
737 /*
738 * Find the lowest frame length among the rate series that will have a
739 * 4ms (or TXOP limited) transmit duration.
740 */
741 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
742
743 for (i = 0; i < 4; i++) {
744 int modeidx;
745
746 if (!rates[i].count)
747 continue;
748
749 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
750 legacy = 1;
751 break;
752 }
753
754 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
755 modeidx = MCS_HT40;
756 else
757 modeidx = MCS_HT20;
758
759 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
760 modeidx++;
761
762 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
763 max_4ms_framelen = min(max_4ms_framelen, frmlen);
764 }
765
766 /*
767 * limit aggregate size by the minimum rate if rate selected is
768 * not a probe rate, if rate selected is a probe rate then
769 * avoid aggregation of this packet.
770 */
771 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
772 return 0;
773
774 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
775
776 /*
777 * Override the default aggregation limit for BTCOEX.
778 */
779 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
780 if (bt_aggr_limit)
781 aggr_limit = bt_aggr_limit;
782
783 /*
784 * h/w can accept aggregates up to 16 bit lengths (65535).
785 * The IE, however can hold up to 65536, which shows up here
786 * as zero. Ignore 65536 since we are constrained by hw.
787 */
788 if (tid->an->maxampdu)
789 aggr_limit = min(aggr_limit, tid->an->maxampdu);
790
791 return aggr_limit;
792 }
793
794 /*
795 * Returns the number of delimiters to be added to
796 * meet the minimum required mpdudensity.
797 */
798 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
799 struct ath_buf *bf, u16 frmlen,
800 bool first_subfrm)
801 {
802 #define FIRST_DESC_NDELIMS 60
803 u32 nsymbits, nsymbols;
804 u16 minlen;
805 u8 flags, rix;
806 int width, streams, half_gi, ndelim, mindelim;
807 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
808
809 /* Select standard number of delimiters based on frame length alone */
810 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
811
812 /*
813 * If encryption enabled, hardware requires some more padding between
814 * subframes.
815 * TODO - this could be improved to be dependent on the rate.
816 * The hardware can keep up at lower rates, but not higher rates
817 */
818 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
819 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
820 ndelim += ATH_AGGR_ENCRYPTDELIM;
821
822 /*
823 * Add delimiter when using RTS/CTS with aggregation
824 * and non enterprise AR9003 card
825 */
826 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
827 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
828 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
829
830 /*
831 * Convert desired mpdu density from microeconds to bytes based
832 * on highest rate in rate series (i.e. first rate) to determine
833 * required minimum length for subframe. Take into account
834 * whether high rate is 20 or 40Mhz and half or full GI.
835 *
836 * If there is no mpdu density restriction, no further calculation
837 * is needed.
838 */
839
840 if (tid->an->mpdudensity == 0)
841 return ndelim;
842
843 rix = bf->rates[0].idx;
844 flags = bf->rates[0].flags;
845 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
846 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
847
848 if (half_gi)
849 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
850 else
851 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
852
853 if (nsymbols == 0)
854 nsymbols = 1;
855
856 streams = HT_RC_2_STREAMS(rix);
857 nsymbits = bits_per_symbol[rix % 8][width] * streams;
858 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
859
860 if (frmlen < minlen) {
861 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
862 ndelim = max(mindelim, ndelim);
863 }
864
865 return ndelim;
866 }
867
868 static struct ath_buf *
869 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
870 struct ath_atx_tid *tid, struct sk_buff_head **q)
871 {
872 struct ieee80211_tx_info *tx_info;
873 struct ath_frame_info *fi;
874 struct sk_buff *skb;
875 struct ath_buf *bf;
876 u16 seqno;
877
878 while (1) {
879 *q = &tid->retry_q;
880 if (skb_queue_empty(*q))
881 *q = &tid->buf_q;
882
883 skb = skb_peek(*q);
884 if (!skb)
885 break;
886
887 fi = get_frame_info(skb);
888 bf = fi->bf;
889 if (!fi->bf)
890 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
891 else
892 bf->bf_state.stale = false;
893
894 if (!bf) {
895 __skb_unlink(skb, *q);
896 ath_txq_skb_done(sc, txq, skb);
897 ieee80211_free_txskb(sc->hw, skb);
898 continue;
899 }
900
901 bf->bf_next = NULL;
902 bf->bf_lastbf = bf;
903
904 tx_info = IEEE80211_SKB_CB(skb);
905 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
906 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
907 bf->bf_state.bf_type = 0;
908 return bf;
909 }
910
911 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
912 seqno = bf->bf_state.seqno;
913
914 /* do not step over block-ack window */
915 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
916 break;
917
918 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
919 struct ath_tx_status ts = {};
920 struct list_head bf_head;
921
922 INIT_LIST_HEAD(&bf_head);
923 list_add(&bf->list, &bf_head);
924 __skb_unlink(skb, *q);
925 ath_tx_update_baw(sc, tid, seqno);
926 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
927 continue;
928 }
929
930 return bf;
931 }
932
933 return NULL;
934 }
935
936 static bool
937 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
938 struct ath_atx_tid *tid, struct list_head *bf_q,
939 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
940 int *aggr_len)
941 {
942 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
943 struct ath_buf *bf = bf_first, *bf_prev = NULL;
944 int nframes = 0, ndelim;
945 u16 aggr_limit = 0, al = 0, bpad = 0,
946 al_delta, h_baw = tid->baw_size / 2;
947 struct ieee80211_tx_info *tx_info;
948 struct ath_frame_info *fi;
949 struct sk_buff *skb;
950 bool closed = false;
951
952 bf = bf_first;
953 aggr_limit = ath_lookup_rate(sc, bf, tid);
954
955 do {
956 skb = bf->bf_mpdu;
957 fi = get_frame_info(skb);
958
959 /* do not exceed aggregation limit */
960 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
961 if (nframes) {
962 if (aggr_limit < al + bpad + al_delta ||
963 ath_lookup_legacy(bf) || nframes >= h_baw)
964 break;
965
966 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
967 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
968 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
969 break;
970 }
971
972 /* add padding for previous frame to aggregation length */
973 al += bpad + al_delta;
974
975 /*
976 * Get the delimiters needed to meet the MPDU
977 * density for this node.
978 */
979 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
980 !nframes);
981 bpad = PADBYTES(al_delta) + (ndelim << 2);
982
983 nframes++;
984 bf->bf_next = NULL;
985
986 /* link buffers of this frame to the aggregate */
987 if (!fi->baw_tracked)
988 ath_tx_addto_baw(sc, tid, bf);
989 bf->bf_state.ndelim = ndelim;
990
991 __skb_unlink(skb, tid_q);
992 list_add_tail(&bf->list, bf_q);
993 if (bf_prev)
994 bf_prev->bf_next = bf;
995
996 bf_prev = bf;
997
998 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
999 if (!bf) {
1000 closed = true;
1001 break;
1002 }
1003 } while (ath_tid_has_buffered(tid));
1004
1005 bf = bf_first;
1006 bf->bf_lastbf = bf_prev;
1007
1008 if (bf == bf_prev) {
1009 al = get_frame_info(bf->bf_mpdu)->framelen;
1010 bf->bf_state.bf_type = BUF_AMPDU;
1011 } else {
1012 TX_STAT_INC(txq->axq_qnum, a_aggr);
1013 }
1014
1015 *aggr_len = al;
1016
1017 return closed;
1018 #undef PADBYTES
1019 }
1020
1021 /*
1022 * rix - rate index
1023 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1024 * width - 0 for 20 MHz, 1 for 40 MHz
1025 * half_gi - to use 4us v/s 3.6 us for symbol time
1026 */
1027 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1028 int width, int half_gi, bool shortPreamble)
1029 {
1030 u32 nbits, nsymbits, duration, nsymbols;
1031 int streams;
1032
1033 /* find number of symbols: PLCP + data */
1034 streams = HT_RC_2_STREAMS(rix);
1035 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1036 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1037 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1038
1039 if (!half_gi)
1040 duration = SYMBOL_TIME(nsymbols);
1041 else
1042 duration = SYMBOL_TIME_HALFGI(nsymbols);
1043
1044 /* addup duration for legacy/ht training and signal fields */
1045 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1046
1047 return duration;
1048 }
1049
1050 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1051 {
1052 int streams = HT_RC_2_STREAMS(mcs);
1053 int symbols, bits;
1054 int bytes = 0;
1055
1056 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1057 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1058 bits -= OFDM_PLCP_BITS;
1059 bytes = bits / 8;
1060 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1061 if (bytes > 65532)
1062 bytes = 65532;
1063
1064 return bytes;
1065 }
1066
1067 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1068 {
1069 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1070 int mcs;
1071
1072 /* 4ms is the default (and maximum) duration */
1073 if (!txop || txop > 4096)
1074 txop = 4096;
1075
1076 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1077 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1078 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1079 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1080 for (mcs = 0; mcs < 32; mcs++) {
1081 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1082 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1083 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1084 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1085 }
1086 }
1087
1088 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1089 struct ath_tx_info *info, int len, bool rts)
1090 {
1091 struct ath_hw *ah = sc->sc_ah;
1092 struct sk_buff *skb;
1093 struct ieee80211_tx_info *tx_info;
1094 struct ieee80211_tx_rate *rates;
1095 const struct ieee80211_rate *rate;
1096 struct ieee80211_hdr *hdr;
1097 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1098 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1099 int i;
1100 u8 rix = 0;
1101
1102 skb = bf->bf_mpdu;
1103 tx_info = IEEE80211_SKB_CB(skb);
1104 rates = bf->rates;
1105 hdr = (struct ieee80211_hdr *)skb->data;
1106
1107 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1108 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1109 info->rtscts_rate = fi->rtscts_rate;
1110
1111 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1112 bool is_40, is_sgi, is_sp;
1113 int phy;
1114
1115 if (!rates[i].count || (rates[i].idx < 0))
1116 continue;
1117
1118 rix = rates[i].idx;
1119 info->rates[i].Tries = rates[i].count;
1120
1121 /*
1122 * Handle RTS threshold for unaggregated HT frames.
1123 */
1124 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1125 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1126 unlikely(rts_thresh != (u32) -1)) {
1127 if (!rts_thresh || (len > rts_thresh))
1128 rts = true;
1129 }
1130
1131 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1132 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1133 info->flags |= ATH9K_TXDESC_RTSENA;
1134 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1135 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1136 info->flags |= ATH9K_TXDESC_CTSENA;
1137 }
1138
1139 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1140 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1141 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1142 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1143
1144 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1145 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1146 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1147
1148 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1149 /* MCS rates */
1150 info->rates[i].Rate = rix | 0x80;
1151 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1152 ah->txchainmask, info->rates[i].Rate);
1153 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1154 is_40, is_sgi, is_sp);
1155 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1156 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1157 continue;
1158 }
1159
1160 /* legacy rates */
1161 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1162 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1163 !(rate->flags & IEEE80211_RATE_ERP_G))
1164 phy = WLAN_RC_PHY_CCK;
1165 else
1166 phy = WLAN_RC_PHY_OFDM;
1167
1168 info->rates[i].Rate = rate->hw_value;
1169 if (rate->hw_value_short) {
1170 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1171 info->rates[i].Rate |= rate->hw_value_short;
1172 } else {
1173 is_sp = false;
1174 }
1175
1176 if (bf->bf_state.bfs_paprd)
1177 info->rates[i].ChSel = ah->txchainmask;
1178 else
1179 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1180 ah->txchainmask, info->rates[i].Rate);
1181
1182 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1183 phy, rate->bitrate * 100, len, rix, is_sp);
1184 }
1185
1186 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1187 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1188 info->flags &= ~ATH9K_TXDESC_RTSENA;
1189
1190 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1191 if (info->flags & ATH9K_TXDESC_RTSENA)
1192 info->flags &= ~ATH9K_TXDESC_CTSENA;
1193 }
1194
1195 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1196 {
1197 struct ieee80211_hdr *hdr;
1198 enum ath9k_pkt_type htype;
1199 __le16 fc;
1200
1201 hdr = (struct ieee80211_hdr *)skb->data;
1202 fc = hdr->frame_control;
1203
1204 if (ieee80211_is_beacon(fc))
1205 htype = ATH9K_PKT_TYPE_BEACON;
1206 else if (ieee80211_is_probe_resp(fc))
1207 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1208 else if (ieee80211_is_atim(fc))
1209 htype = ATH9K_PKT_TYPE_ATIM;
1210 else if (ieee80211_is_pspoll(fc))
1211 htype = ATH9K_PKT_TYPE_PSPOLL;
1212 else
1213 htype = ATH9K_PKT_TYPE_NORMAL;
1214
1215 return htype;
1216 }
1217
1218 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1219 struct ath_txq *txq, int len)
1220 {
1221 struct ath_hw *ah = sc->sc_ah;
1222 struct ath_buf *bf_first = NULL;
1223 struct ath_tx_info info;
1224 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1225 bool rts = false;
1226
1227 memset(&info, 0, sizeof(info));
1228 info.is_first = true;
1229 info.is_last = true;
1230 info.txpower = MAX_RATE_POWER;
1231 info.qcu = txq->axq_qnum;
1232
1233 while (bf) {
1234 struct sk_buff *skb = bf->bf_mpdu;
1235 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1236 struct ath_frame_info *fi = get_frame_info(skb);
1237 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1238
1239 info.type = get_hw_packet_type(skb);
1240 if (bf->bf_next)
1241 info.link = bf->bf_next->bf_daddr;
1242 else
1243 info.link = 0;
1244
1245 if (!bf_first) {
1246 bf_first = bf;
1247
1248 info.flags = ATH9K_TXDESC_INTREQ;
1249 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1250 txq == sc->tx.uapsdq)
1251 info.flags |= ATH9K_TXDESC_CLRDMASK;
1252
1253 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1254 info.flags |= ATH9K_TXDESC_NOACK;
1255 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1256 info.flags |= ATH9K_TXDESC_LDPC;
1257
1258 if (bf->bf_state.bfs_paprd)
1259 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1260 ATH9K_TXDESC_PAPRD_S;
1261
1262 /*
1263 * mac80211 doesn't handle RTS threshold for HT because
1264 * the decision has to be taken based on AMPDU length
1265 * and aggregation is done entirely inside ath9k.
1266 * Set the RTS/CTS flag for the first subframe based
1267 * on the threshold.
1268 */
1269 if (aggr && (bf == bf_first) &&
1270 unlikely(rts_thresh != (u32) -1)) {
1271 /*
1272 * "len" is the size of the entire AMPDU.
1273 */
1274 if (!rts_thresh || (len > rts_thresh))
1275 rts = true;
1276 }
1277 ath_buf_set_rate(sc, bf, &info, len, rts);
1278 }
1279
1280 info.buf_addr[0] = bf->bf_buf_addr;
1281 info.buf_len[0] = skb->len;
1282 info.pkt_len = fi->framelen;
1283 info.keyix = fi->keyix;
1284 info.keytype = fi->keytype;
1285
1286 if (aggr) {
1287 if (bf == bf_first)
1288 info.aggr = AGGR_BUF_FIRST;
1289 else if (bf == bf_first->bf_lastbf)
1290 info.aggr = AGGR_BUF_LAST;
1291 else
1292 info.aggr = AGGR_BUF_MIDDLE;
1293
1294 info.ndelim = bf->bf_state.ndelim;
1295 info.aggr_len = len;
1296 }
1297
1298 if (bf == bf_first->bf_lastbf)
1299 bf_first = NULL;
1300
1301 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1302 bf = bf->bf_next;
1303 }
1304 }
1305
1306 static void
1307 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1308 struct ath_atx_tid *tid, struct list_head *bf_q,
1309 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1310 {
1311 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1312 struct sk_buff *skb;
1313 int nframes = 0;
1314
1315 do {
1316 struct ieee80211_tx_info *tx_info;
1317 skb = bf->bf_mpdu;
1318
1319 nframes++;
1320 __skb_unlink(skb, tid_q);
1321 list_add_tail(&bf->list, bf_q);
1322 if (bf_prev)
1323 bf_prev->bf_next = bf;
1324 bf_prev = bf;
1325
1326 if (nframes >= 2)
1327 break;
1328
1329 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1330 if (!bf)
1331 break;
1332
1333 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1334 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1335 break;
1336
1337 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1338 } while (1);
1339 }
1340
1341 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1342 struct ath_atx_tid *tid, bool *stop)
1343 {
1344 struct ath_buf *bf;
1345 struct ieee80211_tx_info *tx_info;
1346 struct sk_buff_head *tid_q;
1347 struct list_head bf_q;
1348 int aggr_len = 0;
1349 bool aggr, last = true;
1350
1351 if (!ath_tid_has_buffered(tid))
1352 return false;
1353
1354 INIT_LIST_HEAD(&bf_q);
1355
1356 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1357 if (!bf)
1358 return false;
1359
1360 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1361 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1362 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1363 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1364 *stop = true;
1365 return false;
1366 }
1367
1368 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1369 if (aggr)
1370 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1371 tid_q, &aggr_len);
1372 else
1373 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1374
1375 if (list_empty(&bf_q))
1376 return false;
1377
1378 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
1379 tid->ac->clear_ps_filter = false;
1380 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1381 }
1382
1383 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1384 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1385 return true;
1386 }
1387
1388 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1389 u16 tid, u16 *ssn)
1390 {
1391 struct ath_atx_tid *txtid;
1392 struct ath_node *an;
1393 u8 density;
1394
1395 an = (struct ath_node *)sta->drv_priv;
1396 txtid = ATH_AN_2_TID(an, tid);
1397
1398 /* update ampdu factor/density, they may have changed. This may happen
1399 * in HT IBSS when a beacon with HT-info is received after the station
1400 * has already been added.
1401 */
1402 if (sta->ht_cap.ht_supported) {
1403 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1404 sta->ht_cap.ampdu_factor);
1405 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1406 an->mpdudensity = density;
1407 }
1408
1409 /* force sequence number allocation for pending frames */
1410 ath_tx_tid_change_state(sc, txtid);
1411
1412 txtid->active = true;
1413 txtid->paused = true;
1414 *ssn = txtid->seq_start = txtid->seq_next;
1415 txtid->bar_index = -1;
1416
1417 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1418 txtid->baw_head = txtid->baw_tail = 0;
1419
1420 return 0;
1421 }
1422
1423 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1424 {
1425 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1426 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1427 struct ath_txq *txq = txtid->ac->txq;
1428
1429 ath_txq_lock(sc, txq);
1430 txtid->active = false;
1431 txtid->paused = false;
1432 ath_tx_flush_tid(sc, txtid);
1433 ath_tx_tid_change_state(sc, txtid);
1434 ath_txq_unlock_complete(sc, txq);
1435 }
1436
1437 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1438 struct ath_node *an)
1439 {
1440 struct ath_atx_tid *tid;
1441 struct ath_atx_ac *ac;
1442 struct ath_txq *txq;
1443 bool buffered;
1444 int tidno;
1445
1446 for (tidno = 0, tid = &an->tid[tidno];
1447 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1448
1449 if (!tid->sched)
1450 continue;
1451
1452 ac = tid->ac;
1453 txq = ac->txq;
1454
1455 ath_txq_lock(sc, txq);
1456
1457 buffered = ath_tid_has_buffered(tid);
1458
1459 tid->sched = false;
1460 list_del(&tid->list);
1461
1462 if (ac->sched) {
1463 ac->sched = false;
1464 list_del(&ac->list);
1465 }
1466
1467 ath_txq_unlock(sc, txq);
1468
1469 ieee80211_sta_set_buffered(sta, tidno, buffered);
1470 }
1471 }
1472
1473 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1474 {
1475 struct ath_atx_tid *tid;
1476 struct ath_atx_ac *ac;
1477 struct ath_txq *txq;
1478 int tidno;
1479
1480 for (tidno = 0, tid = &an->tid[tidno];
1481 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1482
1483 ac = tid->ac;
1484 txq = ac->txq;
1485
1486 ath_txq_lock(sc, txq);
1487 ac->clear_ps_filter = true;
1488
1489 if (!tid->paused && ath_tid_has_buffered(tid)) {
1490 ath_tx_queue_tid(txq, tid);
1491 ath_txq_schedule(sc, txq);
1492 }
1493
1494 ath_txq_unlock_complete(sc, txq);
1495 }
1496 }
1497
1498 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1499 u16 tidno)
1500 {
1501 struct ath_atx_tid *tid;
1502 struct ath_node *an;
1503 struct ath_txq *txq;
1504
1505 an = (struct ath_node *)sta->drv_priv;
1506 tid = ATH_AN_2_TID(an, tidno);
1507 txq = tid->ac->txq;
1508
1509 ath_txq_lock(sc, txq);
1510
1511 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1512 tid->paused = false;
1513
1514 if (ath_tid_has_buffered(tid)) {
1515 ath_tx_queue_tid(txq, tid);
1516 ath_txq_schedule(sc, txq);
1517 }
1518
1519 ath_txq_unlock_complete(sc, txq);
1520 }
1521
1522 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1523 struct ieee80211_sta *sta,
1524 u16 tids, int nframes,
1525 enum ieee80211_frame_release_type reason,
1526 bool more_data)
1527 {
1528 struct ath_softc *sc = hw->priv;
1529 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1530 struct ath_txq *txq = sc->tx.uapsdq;
1531 struct ieee80211_tx_info *info;
1532 struct list_head bf_q;
1533 struct ath_buf *bf_tail = NULL, *bf;
1534 struct sk_buff_head *tid_q;
1535 int sent = 0;
1536 int i;
1537
1538 INIT_LIST_HEAD(&bf_q);
1539 for (i = 0; tids && nframes; i++, tids >>= 1) {
1540 struct ath_atx_tid *tid;
1541
1542 if (!(tids & 1))
1543 continue;
1544
1545 tid = ATH_AN_2_TID(an, i);
1546 if (tid->paused)
1547 continue;
1548
1549 ath_txq_lock(sc, tid->ac->txq);
1550 while (nframes > 0) {
1551 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1552 if (!bf)
1553 break;
1554
1555 __skb_unlink(bf->bf_mpdu, tid_q);
1556 list_add_tail(&bf->list, &bf_q);
1557 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1558 ath_tx_addto_baw(sc, tid, bf);
1559 bf->bf_state.bf_type &= ~BUF_AGGR;
1560 if (bf_tail)
1561 bf_tail->bf_next = bf;
1562
1563 bf_tail = bf;
1564 nframes--;
1565 sent++;
1566 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1567
1568 if (an->sta && !ath_tid_has_buffered(tid))
1569 ieee80211_sta_set_buffered(an->sta, i, false);
1570 }
1571 ath_txq_unlock_complete(sc, tid->ac->txq);
1572 }
1573
1574 if (list_empty(&bf_q))
1575 return;
1576
1577 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1578 info->flags |= IEEE80211_TX_STATUS_EOSP;
1579
1580 bf = list_first_entry(&bf_q, struct ath_buf, list);
1581 ath_txq_lock(sc, txq);
1582 ath_tx_fill_desc(sc, bf, txq, 0);
1583 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1584 ath_txq_unlock(sc, txq);
1585 }
1586
1587 /********************/
1588 /* Queue Management */
1589 /********************/
1590
1591 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1592 {
1593 struct ath_hw *ah = sc->sc_ah;
1594 struct ath9k_tx_queue_info qi;
1595 static const int subtype_txq_to_hwq[] = {
1596 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1597 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1598 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1599 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1600 };
1601 int axq_qnum, i;
1602
1603 memset(&qi, 0, sizeof(qi));
1604 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1605 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1606 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1607 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1608 qi.tqi_physCompBuf = 0;
1609
1610 /*
1611 * Enable interrupts only for EOL and DESC conditions.
1612 * We mark tx descriptors to receive a DESC interrupt
1613 * when a tx queue gets deep; otherwise waiting for the
1614 * EOL to reap descriptors. Note that this is done to
1615 * reduce interrupt load and this only defers reaping
1616 * descriptors, never transmitting frames. Aside from
1617 * reducing interrupts this also permits more concurrency.
1618 * The only potential downside is if the tx queue backs
1619 * up in which case the top half of the kernel may backup
1620 * due to a lack of tx descriptors.
1621 *
1622 * The UAPSD queue is an exception, since we take a desc-
1623 * based intr on the EOSP frames.
1624 */
1625 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1626 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1627 } else {
1628 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1629 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1630 else
1631 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1632 TXQ_FLAG_TXDESCINT_ENABLE;
1633 }
1634 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1635 if (axq_qnum == -1) {
1636 /*
1637 * NB: don't print a message, this happens
1638 * normally on parts with too few tx queues
1639 */
1640 return NULL;
1641 }
1642 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1643 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1644
1645 txq->axq_qnum = axq_qnum;
1646 txq->mac80211_qnum = -1;
1647 txq->axq_link = NULL;
1648 __skb_queue_head_init(&txq->complete_q);
1649 INIT_LIST_HEAD(&txq->axq_q);
1650 INIT_LIST_HEAD(&txq->axq_acq);
1651 spin_lock_init(&txq->axq_lock);
1652 txq->axq_depth = 0;
1653 txq->axq_ampdu_depth = 0;
1654 txq->axq_tx_inprogress = false;
1655 sc->tx.txqsetup |= 1<<axq_qnum;
1656
1657 txq->txq_headidx = txq->txq_tailidx = 0;
1658 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1659 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1660 }
1661 return &sc->tx.txq[axq_qnum];
1662 }
1663
1664 int ath_txq_update(struct ath_softc *sc, int qnum,
1665 struct ath9k_tx_queue_info *qinfo)
1666 {
1667 struct ath_hw *ah = sc->sc_ah;
1668 int error = 0;
1669 struct ath9k_tx_queue_info qi;
1670
1671 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1672
1673 ath9k_hw_get_txq_props(ah, qnum, &qi);
1674 qi.tqi_aifs = qinfo->tqi_aifs;
1675 qi.tqi_cwmin = qinfo->tqi_cwmin;
1676 qi.tqi_cwmax = qinfo->tqi_cwmax;
1677 qi.tqi_burstTime = qinfo->tqi_burstTime;
1678 qi.tqi_readyTime = qinfo->tqi_readyTime;
1679
1680 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1681 ath_err(ath9k_hw_common(sc->sc_ah),
1682 "Unable to update hardware queue %u!\n", qnum);
1683 error = -EIO;
1684 } else {
1685 ath9k_hw_resettxqueue(ah, qnum);
1686 }
1687
1688 return error;
1689 }
1690
1691 int ath_cabq_update(struct ath_softc *sc)
1692 {
1693 struct ath9k_tx_queue_info qi;
1694 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1695 int qnum = sc->beacon.cabq->axq_qnum;
1696
1697 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1698 /*
1699 * Ensure the readytime % is within the bounds.
1700 */
1701 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1702 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1703 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1704 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1705
1706 qi.tqi_readyTime = (cur_conf->beacon_interval *
1707 sc->config.cabqReadytime) / 100;
1708 ath_txq_update(sc, qnum, &qi);
1709
1710 return 0;
1711 }
1712
1713 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1714 struct list_head *list)
1715 {
1716 struct ath_buf *bf, *lastbf;
1717 struct list_head bf_head;
1718 struct ath_tx_status ts;
1719
1720 memset(&ts, 0, sizeof(ts));
1721 ts.ts_status = ATH9K_TX_FLUSH;
1722 INIT_LIST_HEAD(&bf_head);
1723
1724 while (!list_empty(list)) {
1725 bf = list_first_entry(list, struct ath_buf, list);
1726
1727 if (bf->bf_state.stale) {
1728 list_del(&bf->list);
1729
1730 ath_tx_return_buffer(sc, bf);
1731 continue;
1732 }
1733
1734 lastbf = bf->bf_lastbf;
1735 list_cut_position(&bf_head, list, &lastbf->list);
1736 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1737 }
1738 }
1739
1740 /*
1741 * Drain a given TX queue (could be Beacon or Data)
1742 *
1743 * This assumes output has been stopped and
1744 * we do not need to block ath_tx_tasklet.
1745 */
1746 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1747 {
1748 ath_txq_lock(sc, txq);
1749
1750 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1751 int idx = txq->txq_tailidx;
1752
1753 while (!list_empty(&txq->txq_fifo[idx])) {
1754 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1755
1756 INCR(idx, ATH_TXFIFO_DEPTH);
1757 }
1758 txq->txq_tailidx = idx;
1759 }
1760
1761 txq->axq_link = NULL;
1762 txq->axq_tx_inprogress = false;
1763 ath_drain_txq_list(sc, txq, &txq->axq_q);
1764
1765 ath_txq_unlock_complete(sc, txq);
1766 }
1767
1768 bool ath_drain_all_txq(struct ath_softc *sc)
1769 {
1770 struct ath_hw *ah = sc->sc_ah;
1771 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1772 struct ath_txq *txq;
1773 int i;
1774 u32 npend = 0;
1775
1776 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1777 return true;
1778
1779 ath9k_hw_abort_tx_dma(ah);
1780
1781 /* Check if any queue remains active */
1782 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1783 if (!ATH_TXQ_SETUP(sc, i))
1784 continue;
1785
1786 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1787 npend |= BIT(i);
1788 }
1789
1790 if (npend)
1791 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1792
1793 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1794 if (!ATH_TXQ_SETUP(sc, i))
1795 continue;
1796
1797 /*
1798 * The caller will resume queues with ieee80211_wake_queues.
1799 * Mark the queue as not stopped to prevent ath_tx_complete
1800 * from waking the queue too early.
1801 */
1802 txq = &sc->tx.txq[i];
1803 txq->stopped = false;
1804 ath_draintxq(sc, txq);
1805 }
1806
1807 return !npend;
1808 }
1809
1810 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1811 {
1812 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1813 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1814 }
1815
1816 /* For each axq_acq entry, for each tid, try to schedule packets
1817 * for transmit until ampdu_depth has reached min Q depth.
1818 */
1819 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1820 {
1821 struct ath_atx_ac *ac, *last_ac;
1822 struct ath_atx_tid *tid, *last_tid;
1823 bool sent = false;
1824
1825 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1826 list_empty(&txq->axq_acq))
1827 return;
1828
1829 rcu_read_lock();
1830
1831 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1832 while (!list_empty(&txq->axq_acq)) {
1833 bool stop = false;
1834
1835 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1836 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1837 list_del(&ac->list);
1838 ac->sched = false;
1839
1840 while (!list_empty(&ac->tid_q)) {
1841
1842 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1843 list);
1844 list_del(&tid->list);
1845 tid->sched = false;
1846
1847 if (tid->paused)
1848 continue;
1849
1850 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1851 sent = true;
1852
1853 /*
1854 * add tid to round-robin queue if more frames
1855 * are pending for the tid
1856 */
1857 if (ath_tid_has_buffered(tid))
1858 ath_tx_queue_tid(txq, tid);
1859
1860 if (stop || tid == last_tid)
1861 break;
1862 }
1863
1864 if (!list_empty(&ac->tid_q) && !ac->sched) {
1865 ac->sched = true;
1866 list_add_tail(&ac->list, &txq->axq_acq);
1867 }
1868
1869 if (stop)
1870 break;
1871
1872 if (ac == last_ac) {
1873 if (!sent)
1874 break;
1875
1876 sent = false;
1877 last_ac = list_entry(txq->axq_acq.prev,
1878 struct ath_atx_ac, list);
1879 }
1880 }
1881
1882 rcu_read_unlock();
1883 }
1884
1885 /***********/
1886 /* TX, DMA */
1887 /***********/
1888
1889 /*
1890 * Insert a chain of ath_buf (descriptors) on a txq and
1891 * assume the descriptors are already chained together by caller.
1892 */
1893 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1894 struct list_head *head, bool internal)
1895 {
1896 struct ath_hw *ah = sc->sc_ah;
1897 struct ath_common *common = ath9k_hw_common(ah);
1898 struct ath_buf *bf, *bf_last;
1899 bool puttxbuf = false;
1900 bool edma;
1901
1902 /*
1903 * Insert the frame on the outbound list and
1904 * pass it on to the hardware.
1905 */
1906
1907 if (list_empty(head))
1908 return;
1909
1910 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1911 bf = list_first_entry(head, struct ath_buf, list);
1912 bf_last = list_entry(head->prev, struct ath_buf, list);
1913
1914 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1915 txq->axq_qnum, txq->axq_depth);
1916
1917 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1918 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1919 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1920 puttxbuf = true;
1921 } else {
1922 list_splice_tail_init(head, &txq->axq_q);
1923
1924 if (txq->axq_link) {
1925 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1926 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1927 txq->axq_qnum, txq->axq_link,
1928 ito64(bf->bf_daddr), bf->bf_desc);
1929 } else if (!edma)
1930 puttxbuf = true;
1931
1932 txq->axq_link = bf_last->bf_desc;
1933 }
1934
1935 if (puttxbuf) {
1936 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1937 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1938 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1939 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1940 }
1941
1942 if (!edma) {
1943 TX_STAT_INC(txq->axq_qnum, txstart);
1944 ath9k_hw_txstart(ah, txq->axq_qnum);
1945 }
1946
1947 if (!internal) {
1948 while (bf) {
1949 txq->axq_depth++;
1950 if (bf_is_ampdu_not_probing(bf))
1951 txq->axq_ampdu_depth++;
1952
1953 bf = bf->bf_lastbf->bf_next;
1954 }
1955 }
1956 }
1957
1958 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1959 struct ath_atx_tid *tid, struct sk_buff *skb)
1960 {
1961 struct ath_frame_info *fi = get_frame_info(skb);
1962 struct list_head bf_head;
1963 struct ath_buf *bf;
1964
1965 bf = fi->bf;
1966
1967 INIT_LIST_HEAD(&bf_head);
1968 list_add_tail(&bf->list, &bf_head);
1969 bf->bf_state.bf_type = 0;
1970
1971 bf->bf_next = NULL;
1972 bf->bf_lastbf = bf;
1973 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1974 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1975 TX_STAT_INC(txq->axq_qnum, queued);
1976 }
1977
1978 static void setup_frame_info(struct ieee80211_hw *hw,
1979 struct ieee80211_sta *sta,
1980 struct sk_buff *skb,
1981 int framelen)
1982 {
1983 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1984 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1985 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1986 const struct ieee80211_rate *rate;
1987 struct ath_frame_info *fi = get_frame_info(skb);
1988 struct ath_node *an = NULL;
1989 enum ath9k_key_type keytype;
1990 bool short_preamble = false;
1991
1992 /*
1993 * We check if Short Preamble is needed for the CTS rate by
1994 * checking the BSS's global flag.
1995 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1996 */
1997 if (tx_info->control.vif &&
1998 tx_info->control.vif->bss_conf.use_short_preamble)
1999 short_preamble = true;
2000
2001 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2002 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2003
2004 if (sta)
2005 an = (struct ath_node *) sta->drv_priv;
2006
2007 memset(fi, 0, sizeof(*fi));
2008 if (hw_key)
2009 fi->keyix = hw_key->hw_key_idx;
2010 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2011 fi->keyix = an->ps_key;
2012 else
2013 fi->keyix = ATH9K_TXKEYIX_INVALID;
2014 fi->keytype = keytype;
2015 fi->framelen = framelen;
2016 fi->rtscts_rate = rate->hw_value;
2017 if (short_preamble)
2018 fi->rtscts_rate |= rate->hw_value_short;
2019 }
2020
2021 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2022 {
2023 struct ath_hw *ah = sc->sc_ah;
2024 struct ath9k_channel *curchan = ah->curchan;
2025
2026 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
2027 (curchan->channelFlags & CHANNEL_5GHZ) &&
2028 (chainmask == 0x7) && (rate < 0x90))
2029 return 0x3;
2030 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2031 IS_CCK_RATE(rate))
2032 return 0x2;
2033 else
2034 return chainmask;
2035 }
2036
2037 /*
2038 * Assign a descriptor (and sequence number if necessary,
2039 * and map buffer for DMA. Frees skb on error
2040 */
2041 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2042 struct ath_txq *txq,
2043 struct ath_atx_tid *tid,
2044 struct sk_buff *skb)
2045 {
2046 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2047 struct ath_frame_info *fi = get_frame_info(skb);
2048 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2049 struct ath_buf *bf;
2050 int fragno;
2051 u16 seqno;
2052
2053 bf = ath_tx_get_buffer(sc);
2054 if (!bf) {
2055 ath_dbg(common, XMIT, "TX buffers are full\n");
2056 return NULL;
2057 }
2058
2059 ATH_TXBUF_RESET(bf);
2060
2061 if (tid) {
2062 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2063 seqno = tid->seq_next;
2064 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2065
2066 if (fragno)
2067 hdr->seq_ctrl |= cpu_to_le16(fragno);
2068
2069 if (!ieee80211_has_morefrags(hdr->frame_control))
2070 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2071
2072 bf->bf_state.seqno = seqno;
2073 }
2074
2075 bf->bf_mpdu = skb;
2076
2077 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2078 skb->len, DMA_TO_DEVICE);
2079 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2080 bf->bf_mpdu = NULL;
2081 bf->bf_buf_addr = 0;
2082 ath_err(ath9k_hw_common(sc->sc_ah),
2083 "dma_mapping_error() on TX\n");
2084 ath_tx_return_buffer(sc, bf);
2085 return NULL;
2086 }
2087
2088 fi->bf = bf;
2089
2090 return bf;
2091 }
2092
2093 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2094 struct ath_tx_control *txctl)
2095 {
2096 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2097 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2098 struct ieee80211_sta *sta = txctl->sta;
2099 struct ieee80211_vif *vif = info->control.vif;
2100 struct ath_vif *avp;
2101 struct ath_softc *sc = hw->priv;
2102 int frmlen = skb->len + FCS_LEN;
2103 int padpos, padsize;
2104
2105 /* NOTE: sta can be NULL according to net/mac80211.h */
2106 if (sta)
2107 txctl->an = (struct ath_node *)sta->drv_priv;
2108 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2109 avp = (void *)vif->drv_priv;
2110 txctl->an = &avp->mcast_node;
2111 }
2112
2113 if (info->control.hw_key)
2114 frmlen += info->control.hw_key->icv_len;
2115
2116 /*
2117 * As a temporary workaround, assign seq# here; this will likely need
2118 * to be cleaned up to work better with Beacon transmission and virtual
2119 * BSSes.
2120 */
2121 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2122 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2123 sc->tx.seq_no += 0x10;
2124 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2125 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2126 }
2127
2128 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2129 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2130 !ieee80211_is_data(hdr->frame_control))
2131 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2132
2133 /* Add the padding after the header if this is not already done */
2134 padpos = ieee80211_hdrlen(hdr->frame_control);
2135 padsize = padpos & 3;
2136 if (padsize && skb->len > padpos) {
2137 if (skb_headroom(skb) < padsize)
2138 return -ENOMEM;
2139
2140 skb_push(skb, padsize);
2141 memmove(skb->data, skb->data + padsize, padpos);
2142 }
2143
2144 setup_frame_info(hw, sta, skb, frmlen);
2145 return 0;
2146 }
2147
2148
2149 /* Upon failure caller should free skb */
2150 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2151 struct ath_tx_control *txctl)
2152 {
2153 struct ieee80211_hdr *hdr;
2154 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2155 struct ieee80211_sta *sta = txctl->sta;
2156 struct ieee80211_vif *vif = info->control.vif;
2157 struct ath_softc *sc = hw->priv;
2158 struct ath_txq *txq = txctl->txq;
2159 struct ath_atx_tid *tid = NULL;
2160 struct ath_buf *bf;
2161 int q;
2162 int ret;
2163
2164 ret = ath_tx_prepare(hw, skb, txctl);
2165 if (ret)
2166 return ret;
2167
2168 hdr = (struct ieee80211_hdr *) skb->data;
2169 /*
2170 * At this point, the vif, hw_key and sta pointers in the tx control
2171 * info are no longer valid (overwritten by the ath_frame_info data.
2172 */
2173
2174 q = skb_get_queue_mapping(skb);
2175
2176 ath_txq_lock(sc, txq);
2177 if (txq == sc->tx.txq_map[q] &&
2178 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2179 !txq->stopped) {
2180 ieee80211_stop_queue(sc->hw, q);
2181 txq->stopped = true;
2182 }
2183
2184 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2185 ath_txq_unlock(sc, txq);
2186 txq = sc->tx.uapsdq;
2187 ath_txq_lock(sc, txq);
2188 } else if (txctl->an &&
2189 ieee80211_is_data_present(hdr->frame_control)) {
2190 tid = ath_get_skb_tid(sc, txctl->an, skb);
2191
2192 WARN_ON(tid->ac->txq != txctl->txq);
2193
2194 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2195 tid->ac->clear_ps_filter = true;
2196
2197 /*
2198 * Add this frame to software queue for scheduling later
2199 * for aggregation.
2200 */
2201 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2202 __skb_queue_tail(&tid->buf_q, skb);
2203 if (!txctl->an->sleeping)
2204 ath_tx_queue_tid(txq, tid);
2205
2206 ath_txq_schedule(sc, txq);
2207 goto out;
2208 }
2209
2210 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2211 if (!bf) {
2212 ath_txq_skb_done(sc, txq, skb);
2213 if (txctl->paprd)
2214 dev_kfree_skb_any(skb);
2215 else
2216 ieee80211_free_txskb(sc->hw, skb);
2217 goto out;
2218 }
2219
2220 bf->bf_state.bfs_paprd = txctl->paprd;
2221
2222 if (txctl->paprd)
2223 bf->bf_state.bfs_paprd_timestamp = jiffies;
2224
2225 ath_set_rates(vif, sta, bf);
2226 ath_tx_send_normal(sc, txq, tid, skb);
2227
2228 out:
2229 ath_txq_unlock(sc, txq);
2230
2231 return 0;
2232 }
2233
2234 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2235 struct sk_buff *skb)
2236 {
2237 struct ath_softc *sc = hw->priv;
2238 struct ath_tx_control txctl = {
2239 .txq = sc->beacon.cabq
2240 };
2241 struct ath_tx_info info = {};
2242 struct ieee80211_hdr *hdr;
2243 struct ath_buf *bf_tail = NULL;
2244 struct ath_buf *bf;
2245 LIST_HEAD(bf_q);
2246 int duration = 0;
2247 int max_duration;
2248
2249 max_duration =
2250 sc->cur_beacon_conf.beacon_interval * 1000 *
2251 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2252
2253 do {
2254 struct ath_frame_info *fi = get_frame_info(skb);
2255
2256 if (ath_tx_prepare(hw, skb, &txctl))
2257 break;
2258
2259 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2260 if (!bf)
2261 break;
2262
2263 bf->bf_lastbf = bf;
2264 ath_set_rates(vif, NULL, bf);
2265 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2266 duration += info.rates[0].PktDuration;
2267 if (bf_tail)
2268 bf_tail->bf_next = bf;
2269
2270 list_add_tail(&bf->list, &bf_q);
2271 bf_tail = bf;
2272 skb = NULL;
2273
2274 if (duration > max_duration)
2275 break;
2276
2277 skb = ieee80211_get_buffered_bc(hw, vif);
2278 } while(skb);
2279
2280 if (skb)
2281 ieee80211_free_txskb(hw, skb);
2282
2283 if (list_empty(&bf_q))
2284 return;
2285
2286 bf = list_first_entry(&bf_q, struct ath_buf, list);
2287 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2288
2289 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2290 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2291 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2292 sizeof(*hdr), DMA_TO_DEVICE);
2293 }
2294
2295 ath_txq_lock(sc, txctl.txq);
2296 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2297 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2298 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2299 ath_txq_unlock(sc, txctl.txq);
2300 }
2301
2302 /*****************/
2303 /* TX Completion */
2304 /*****************/
2305
2306 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2307 int tx_flags, struct ath_txq *txq)
2308 {
2309 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2310 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2311 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2312 int padpos, padsize;
2313 unsigned long flags;
2314
2315 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2316
2317 if (sc->sc_ah->caldata)
2318 sc->sc_ah->caldata->paprd_packet_sent = true;
2319
2320 if (!(tx_flags & ATH_TX_ERROR))
2321 /* Frame was ACKed */
2322 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2323
2324 padpos = ieee80211_hdrlen(hdr->frame_control);
2325 padsize = padpos & 3;
2326 if (padsize && skb->len>padpos+padsize) {
2327 /*
2328 * Remove MAC header padding before giving the frame back to
2329 * mac80211.
2330 */
2331 memmove(skb->data + padsize, skb->data, padpos);
2332 skb_pull(skb, padsize);
2333 }
2334
2335 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2336 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2337 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2338 ath_dbg(common, PS,
2339 "Going back to sleep after having received TX status (0x%lx)\n",
2340 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2341 PS_WAIT_FOR_CAB |
2342 PS_WAIT_FOR_PSPOLL_DATA |
2343 PS_WAIT_FOR_TX_ACK));
2344 }
2345 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2346
2347 __skb_queue_tail(&txq->complete_q, skb);
2348 ath_txq_skb_done(sc, txq, skb);
2349 }
2350
2351 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2352 struct ath_txq *txq, struct list_head *bf_q,
2353 struct ath_tx_status *ts, int txok)
2354 {
2355 struct sk_buff *skb = bf->bf_mpdu;
2356 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2357 unsigned long flags;
2358 int tx_flags = 0;
2359
2360 if (!txok)
2361 tx_flags |= ATH_TX_ERROR;
2362
2363 if (ts->ts_status & ATH9K_TXERR_FILT)
2364 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2365
2366 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2367 bf->bf_buf_addr = 0;
2368
2369 if (bf->bf_state.bfs_paprd) {
2370 if (time_after(jiffies,
2371 bf->bf_state.bfs_paprd_timestamp +
2372 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2373 dev_kfree_skb_any(skb);
2374 else
2375 complete(&sc->paprd_complete);
2376 } else {
2377 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2378 ath_tx_complete(sc, skb, tx_flags, txq);
2379 }
2380 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2381 * accidentally reference it later.
2382 */
2383 bf->bf_mpdu = NULL;
2384
2385 /*
2386 * Return the list of ath_buf of this mpdu to free queue
2387 */
2388 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2389 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2390 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2391 }
2392
2393 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2394 struct ath_tx_status *ts, int nframes, int nbad,
2395 int txok)
2396 {
2397 struct sk_buff *skb = bf->bf_mpdu;
2398 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2399 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2400 struct ieee80211_hw *hw = sc->hw;
2401 struct ath_hw *ah = sc->sc_ah;
2402 u8 i, tx_rateindex;
2403
2404 if (txok)
2405 tx_info->status.ack_signal = ts->ts_rssi;
2406
2407 tx_rateindex = ts->ts_rateindex;
2408 WARN_ON(tx_rateindex >= hw->max_rates);
2409
2410 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2411 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2412
2413 BUG_ON(nbad > nframes);
2414 }
2415 tx_info->status.ampdu_len = nframes;
2416 tx_info->status.ampdu_ack_len = nframes - nbad;
2417
2418 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2419 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2420 /*
2421 * If an underrun error is seen assume it as an excessive
2422 * retry only if max frame trigger level has been reached
2423 * (2 KB for single stream, and 4 KB for dual stream).
2424 * Adjust the long retry as if the frame was tried
2425 * hw->max_rate_tries times to affect how rate control updates
2426 * PER for the failed rate.
2427 * In case of congestion on the bus penalizing this type of
2428 * underruns should help hardware actually transmit new frames
2429 * successfully by eventually preferring slower rates.
2430 * This itself should also alleviate congestion on the bus.
2431 */
2432 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2433 ATH9K_TX_DELIM_UNDERRUN)) &&
2434 ieee80211_is_data(hdr->frame_control) &&
2435 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2436 tx_info->status.rates[tx_rateindex].count =
2437 hw->max_rate_tries;
2438 }
2439
2440 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2441 tx_info->status.rates[i].count = 0;
2442 tx_info->status.rates[i].idx = -1;
2443 }
2444
2445 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2446 }
2447
2448 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2449 {
2450 struct ath_hw *ah = sc->sc_ah;
2451 struct ath_common *common = ath9k_hw_common(ah);
2452 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2453 struct list_head bf_head;
2454 struct ath_desc *ds;
2455 struct ath_tx_status ts;
2456 int status;
2457
2458 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2459 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2460 txq->axq_link);
2461
2462 ath_txq_lock(sc, txq);
2463 for (;;) {
2464 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2465 break;
2466
2467 if (list_empty(&txq->axq_q)) {
2468 txq->axq_link = NULL;
2469 ath_txq_schedule(sc, txq);
2470 break;
2471 }
2472 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2473
2474 /*
2475 * There is a race condition that a BH gets scheduled
2476 * after sw writes TxE and before hw re-load the last
2477 * descriptor to get the newly chained one.
2478 * Software must keep the last DONE descriptor as a
2479 * holding descriptor - software does so by marking
2480 * it with the STALE flag.
2481 */
2482 bf_held = NULL;
2483 if (bf->bf_state.stale) {
2484 bf_held = bf;
2485 if (list_is_last(&bf_held->list, &txq->axq_q))
2486 break;
2487
2488 bf = list_entry(bf_held->list.next, struct ath_buf,
2489 list);
2490 }
2491
2492 lastbf = bf->bf_lastbf;
2493 ds = lastbf->bf_desc;
2494
2495 memset(&ts, 0, sizeof(ts));
2496 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2497 if (status == -EINPROGRESS)
2498 break;
2499
2500 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2501
2502 /*
2503 * Remove ath_buf's of the same transmit unit from txq,
2504 * however leave the last descriptor back as the holding
2505 * descriptor for hw.
2506 */
2507 lastbf->bf_state.stale = true;
2508 INIT_LIST_HEAD(&bf_head);
2509 if (!list_is_singular(&lastbf->list))
2510 list_cut_position(&bf_head,
2511 &txq->axq_q, lastbf->list.prev);
2512
2513 if (bf_held) {
2514 list_del(&bf_held->list);
2515 ath_tx_return_buffer(sc, bf_held);
2516 }
2517
2518 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2519 }
2520 ath_txq_unlock_complete(sc, txq);
2521 }
2522
2523 void ath_tx_tasklet(struct ath_softc *sc)
2524 {
2525 struct ath_hw *ah = sc->sc_ah;
2526 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2527 int i;
2528
2529 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2530 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2531 ath_tx_processq(sc, &sc->tx.txq[i]);
2532 }
2533 }
2534
2535 void ath_tx_edma_tasklet(struct ath_softc *sc)
2536 {
2537 struct ath_tx_status ts;
2538 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2539 struct ath_hw *ah = sc->sc_ah;
2540 struct ath_txq *txq;
2541 struct ath_buf *bf, *lastbf;
2542 struct list_head bf_head;
2543 struct list_head *fifo_list;
2544 int status;
2545
2546 for (;;) {
2547 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2548 break;
2549
2550 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2551 if (status == -EINPROGRESS)
2552 break;
2553 if (status == -EIO) {
2554 ath_dbg(common, XMIT, "Error processing tx status\n");
2555 break;
2556 }
2557
2558 /* Process beacon completions separately */
2559 if (ts.qid == sc->beacon.beaconq) {
2560 sc->beacon.tx_processed = true;
2561 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2562
2563 ath9k_csa_is_finished(sc);
2564 continue;
2565 }
2566
2567 txq = &sc->tx.txq[ts.qid];
2568
2569 ath_txq_lock(sc, txq);
2570
2571 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2572
2573 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2574 if (list_empty(fifo_list)) {
2575 ath_txq_unlock(sc, txq);
2576 return;
2577 }
2578
2579 bf = list_first_entry(fifo_list, struct ath_buf, list);
2580 if (bf->bf_state.stale) {
2581 list_del(&bf->list);
2582 ath_tx_return_buffer(sc, bf);
2583 bf = list_first_entry(fifo_list, struct ath_buf, list);
2584 }
2585
2586 lastbf = bf->bf_lastbf;
2587
2588 INIT_LIST_HEAD(&bf_head);
2589 if (list_is_last(&lastbf->list, fifo_list)) {
2590 list_splice_tail_init(fifo_list, &bf_head);
2591 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2592
2593 if (!list_empty(&txq->axq_q)) {
2594 struct list_head bf_q;
2595
2596 INIT_LIST_HEAD(&bf_q);
2597 txq->axq_link = NULL;
2598 list_splice_tail_init(&txq->axq_q, &bf_q);
2599 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2600 }
2601 } else {
2602 lastbf->bf_state.stale = true;
2603 if (bf != lastbf)
2604 list_cut_position(&bf_head, fifo_list,
2605 lastbf->list.prev);
2606 }
2607
2608 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2609 ath_txq_unlock_complete(sc, txq);
2610 }
2611 }
2612
2613 /*****************/
2614 /* Init, Cleanup */
2615 /*****************/
2616
2617 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2618 {
2619 struct ath_descdma *dd = &sc->txsdma;
2620 u8 txs_len = sc->sc_ah->caps.txs_len;
2621
2622 dd->dd_desc_len = size * txs_len;
2623 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2624 &dd->dd_desc_paddr, GFP_KERNEL);
2625 if (!dd->dd_desc)
2626 return -ENOMEM;
2627
2628 return 0;
2629 }
2630
2631 static int ath_tx_edma_init(struct ath_softc *sc)
2632 {
2633 int err;
2634
2635 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2636 if (!err)
2637 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2638 sc->txsdma.dd_desc_paddr,
2639 ATH_TXSTATUS_RING_SIZE);
2640
2641 return err;
2642 }
2643
2644 int ath_tx_init(struct ath_softc *sc, int nbufs)
2645 {
2646 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2647 int error = 0;
2648
2649 spin_lock_init(&sc->tx.txbuflock);
2650
2651 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2652 "tx", nbufs, 1, 1);
2653 if (error != 0) {
2654 ath_err(common,
2655 "Failed to allocate tx descriptors: %d\n", error);
2656 return error;
2657 }
2658
2659 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2660 "beacon", ATH_BCBUF, 1, 1);
2661 if (error != 0) {
2662 ath_err(common,
2663 "Failed to allocate beacon descriptors: %d\n", error);
2664 return error;
2665 }
2666
2667 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2668
2669 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2670 error = ath_tx_edma_init(sc);
2671
2672 return error;
2673 }
2674
2675 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2676 {
2677 struct ath_atx_tid *tid;
2678 struct ath_atx_ac *ac;
2679 int tidno, acno;
2680
2681 for (tidno = 0, tid = &an->tid[tidno];
2682 tidno < IEEE80211_NUM_TIDS;
2683 tidno++, tid++) {
2684 tid->an = an;
2685 tid->tidno = tidno;
2686 tid->seq_start = tid->seq_next = 0;
2687 tid->baw_size = WME_MAX_BA;
2688 tid->baw_head = tid->baw_tail = 0;
2689 tid->sched = false;
2690 tid->paused = false;
2691 tid->active = false;
2692 __skb_queue_head_init(&tid->buf_q);
2693 __skb_queue_head_init(&tid->retry_q);
2694 acno = TID_TO_WME_AC(tidno);
2695 tid->ac = &an->ac[acno];
2696 }
2697
2698 for (acno = 0, ac = &an->ac[acno];
2699 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2700 ac->sched = false;
2701 ac->clear_ps_filter = true;
2702 ac->txq = sc->tx.txq_map[acno];
2703 INIT_LIST_HEAD(&ac->tid_q);
2704 }
2705 }
2706
2707 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2708 {
2709 struct ath_atx_ac *ac;
2710 struct ath_atx_tid *tid;
2711 struct ath_txq *txq;
2712 int tidno;
2713
2714 for (tidno = 0, tid = &an->tid[tidno];
2715 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2716
2717 ac = tid->ac;
2718 txq = ac->txq;
2719
2720 ath_txq_lock(sc, txq);
2721
2722 if (tid->sched) {
2723 list_del(&tid->list);
2724 tid->sched = false;
2725 }
2726
2727 if (ac->sched) {
2728 list_del(&ac->list);
2729 tid->ac->sched = false;
2730 }
2731
2732 ath_tid_drain(sc, txq, tid);
2733 tid->active = false;
2734
2735 ath_txq_unlock(sc, txq);
2736 }
2737 }
Linux with added FPC-III support