drivers/net/wireless/b43legacy/dma.h

   1 #ifndef B43legacy_DMA_H_
   2 #define B43legacy_DMA_H_
   3
   4 #include <linux/list.h>
   5 #include <linux/spinlock.h>
   6 #include <linux/workqueue.h>
   7 #include <linux/linkage.h>
   8 #include <linux/atomic.h>
   9
  10 #include "b43legacy.h"
  11
  12
  13 /* DMA-Interrupt reasons. */
  14 #define B43legacy_DMAIRQ_FATALMASK      ((1 << 10) | (1 << 11) | (1 << 12) \
  15                                          | (1 << 14) | (1 << 15))
  16 #define B43legacy_DMAIRQ_NONFATALMASK   (1 << 13)
  17 #define B43legacy_DMAIRQ_RX_DONE                (1 << 16)
  18
  19
  20 /*** 32-bit DMA Engine. ***/
  21
  22 /* 32-bit DMA controller registers. */
  23 #define B43legacy_DMA32_TXCTL                           0x00
  24 #define         B43legacy_DMA32_TXENABLE                0x00000001
  25 #define         B43legacy_DMA32_TXSUSPEND               0x00000002
  26 #define         B43legacy_DMA32_TXLOOPBACK              0x00000004
  27 #define         B43legacy_DMA32_TXFLUSH                 0x00000010
  28 #define         B43legacy_DMA32_TXADDREXT_MASK          0x00030000
  29 #define         B43legacy_DMA32_TXADDREXT_SHIFT         16
  30 #define B43legacy_DMA32_TXRING                          0x04
  31 #define B43legacy_DMA32_TXINDEX                         0x08
  32 #define B43legacy_DMA32_TXSTATUS                        0x0C
  33 #define         B43legacy_DMA32_TXDPTR                  0x00000FFF
  34 #define         B43legacy_DMA32_TXSTATE                 0x0000F000
  35 #define                 B43legacy_DMA32_TXSTAT_DISABLED 0x00000000
  36 #define                 B43legacy_DMA32_TXSTAT_ACTIVE   0x00001000
  37 #define                 B43legacy_DMA32_TXSTAT_IDLEWAIT 0x00002000
  38 #define                 B43legacy_DMA32_TXSTAT_STOPPED  0x00003000
  39 #define                 B43legacy_DMA32_TXSTAT_SUSP     0x00004000
  40 #define         B43legacy_DMA32_TXERROR                 0x000F0000
  41 #define                 B43legacy_DMA32_TXERR_NOERR     0x00000000
  42 #define                 B43legacy_DMA32_TXERR_PROT      0x00010000
  43 #define                 B43legacy_DMA32_TXERR_UNDERRUN  0x00020000
  44 #define                 B43legacy_DMA32_TXERR_BUFREAD   0x00030000
  45 #define                 B43legacy_DMA32_TXERR_DESCREAD  0x00040000
  46 #define         B43legacy_DMA32_TXACTIVE                0xFFF00000
  47 #define B43legacy_DMA32_RXCTL                           0x10
  48 #define         B43legacy_DMA32_RXENABLE                0x00000001
  49 #define         B43legacy_DMA32_RXFROFF_MASK            0x000000FE
  50 #define         B43legacy_DMA32_RXFROFF_SHIFT           1
  51 #define         B43legacy_DMA32_RXDIRECTFIFO            0x00000100
  52 #define         B43legacy_DMA32_RXADDREXT_MASK          0x00030000
  53 #define         B43legacy_DMA32_RXADDREXT_SHIFT         16
  54 #define B43legacy_DMA32_RXRING                          0x14
  55 #define B43legacy_DMA32_RXINDEX                         0x18
  56 #define B43legacy_DMA32_RXSTATUS                        0x1C
  57 #define         B43legacy_DMA32_RXDPTR                  0x00000FFF
  58 #define         B43legacy_DMA32_RXSTATE                 0x0000F000
  59 #define                 B43legacy_DMA32_RXSTAT_DISABLED 0x00000000
  60 #define                 B43legacy_DMA32_RXSTAT_ACTIVE   0x00001000
  61 #define                 B43legacy_DMA32_RXSTAT_IDLEWAIT 0x00002000
  62 #define                 B43legacy_DMA32_RXSTAT_STOPPED  0x00003000
  63 #define         B43legacy_DMA32_RXERROR                 0x000F0000
  64 #define                 B43legacy_DMA32_RXERR_NOERR     0x00000000
  65 #define                 B43legacy_DMA32_RXERR_PROT      0x00010000
  66 #define                 B43legacy_DMA32_RXERR_OVERFLOW  0x00020000
  67 #define                 B43legacy_DMA32_RXERR_BUFWRITE  0x00030000
  68 #define                 B43legacy_DMA32_RXERR_DESCREAD  0x00040000
  69 #define         B43legacy_DMA32_RXACTIVE                0xFFF00000
  70
  71 /* 32-bit DMA descriptor. */
  72 struct b43legacy_dmadesc32 {
  73         __le32 control;
  74         __le32 address;
  75 } __packed;
  76 #define B43legacy_DMA32_DCTL_BYTECNT            0x00001FFF
  77 #define B43legacy_DMA32_DCTL_ADDREXT_MASK       0x00030000
  78 #define B43legacy_DMA32_DCTL_ADDREXT_SHIFT      16
  79 #define B43legacy_DMA32_DCTL_DTABLEEND          0x10000000
  80 #define B43legacy_DMA32_DCTL_IRQ                0x20000000
  81 #define B43legacy_DMA32_DCTL_FRAMEEND           0x40000000
  82 #define B43legacy_DMA32_DCTL_FRAMESTART         0x80000000
  83
  84
  85 /* Misc DMA constants */
  86 #define B43legacy_DMA_RINGMEMSIZE       PAGE_SIZE
  87 #define B43legacy_DMA0_RX_FRAMEOFFSET   30
  88 #define B43legacy_DMA3_RX_FRAMEOFFSET   0
  89
  90
  91 /* DMA engine tuning knobs */
  92 #define B43legacy_TXRING_SLOTS          128
  93 #define B43legacy_RXRING_SLOTS          64
  94 #define B43legacy_DMA0_RX_BUFFERSIZE    (2304 + 100)
  95 #define B43legacy_DMA3_RX_BUFFERSIZE    16
  96
  97
  98
  99 #ifdef CONFIG_B43LEGACY_DMA
 100
 101
 102 struct sk_buff;
 103 struct b43legacy_private;
 104 struct b43legacy_txstatus;
 105
 106
 107 struct b43legacy_dmadesc_meta {
 108         /* The kernel DMA-able buffer. */
 109         struct sk_buff *skb;
 110         /* DMA base bus-address of the descriptor buffer. */
 111         dma_addr_t dmaaddr;
 112         /* ieee80211 TX status. Only used once per 802.11 frag. */
 113         bool is_last_fragment;
 114 };
 115
 116 enum b43legacy_dmatype {
 117         B43legacy_DMA_30BIT = 30,
 118         B43legacy_DMA_32BIT = 32,
 119 };
 120
 121 struct b43legacy_dmaring {
 122         /* Kernel virtual base address of the ring memory. */
 123         void *descbase;
 124         /* Meta data about all descriptors. */
 125         struct b43legacy_dmadesc_meta *meta;
 126         /* Cache of TX headers for each slot.
 127          * This is to avoid an allocation on each TX.
 128          * This is NULL for an RX ring.
 129          */
 130         u8 *txhdr_cache;
 131         /* (Unadjusted) DMA base bus-address of the ring memory. */
 132         dma_addr_t dmabase;
 133         /* Number of descriptor slots in the ring. */
 134         int nr_slots;
 135         /* Number of used descriptor slots. */
 136         int used_slots;
 137         /* Currently used slot in the ring. */
 138         int current_slot;
 139         /* Frameoffset in octets. */
 140         u32 frameoffset;
 141         /* Descriptor buffer size. */
 142         u16 rx_buffersize;
 143         /* The MMIO base register of the DMA controller. */
 144         u16 mmio_base;
 145         /* DMA controller index number (0-5). */
 146         int index;
 147         /* Boolean. Is this a TX ring? */
 148         bool tx;
 149         /* The type of DMA engine used. */
 150         enum b43legacy_dmatype type;
 151         /* Boolean. Is this ring stopped at ieee80211 level? */
 152         bool stopped;
 153         /* The QOS priority assigned to this ring. Only used for TX rings.
 154          * This is the mac80211 "queue" value. */
 155         u8 queue_prio;
 156         struct b43legacy_wldev *dev;
 157 #ifdef CONFIG_B43LEGACY_DEBUG
 158         /* Maximum number of used slots. */
 159         int max_used_slots;
 160         /* Last time we injected a ring overflow. */
 161         unsigned long last_injected_overflow;
 162 #endif /* CONFIG_B43LEGACY_DEBUG*/
 163 };
 164
 165
 166 static inline
 167 u32 b43legacy_dma_read(struct b43legacy_dmaring *ring,
 168                        u16 offset)
 169 {
 170         return b43legacy_read32(ring->dev, ring->mmio_base + offset);
 171 }
 172
 173 static inline
 174 void b43legacy_dma_write(struct b43legacy_dmaring *ring,
 175                          u16 offset, u32 value)
 176 {
 177         b43legacy_write32(ring->dev, ring->mmio_base + offset, value);
 178 }
 179
 180
 181 int b43legacy_dma_init(struct b43legacy_wldev *dev);
 182 void b43legacy_dma_free(struct b43legacy_wldev *dev);
 183
 184 void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev);
 185 void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev);
 186
 187 int b43legacy_dma_tx(struct b43legacy_wldev *dev,
 188                      struct sk_buff *skb);
 189 void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
 190                                    const struct b43legacy_txstatus *status);
 191
 192 void b43legacy_dma_rx(struct b43legacy_dmaring *ring);
 193
 194 #else /* CONFIG_B43LEGACY_DMA */
 195
 196
 197 static inline
 198 int b43legacy_dma_init(struct b43legacy_wldev *dev)
 199 {
 200         return 0;
 201 }
 202 static inline
 203 void b43legacy_dma_free(struct b43legacy_wldev *dev)
 204 {
 205 }
 206 static inline
 207 int b43legacy_dma_tx(struct b43legacy_wldev *dev,
 208                      struct sk_buff *skb)
 209 {
 210         return 0;
 211 }
 212 static inline
 213 void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
 214                                    const struct b43legacy_txstatus *status)
 215 {
 216 }
 217 static inline
 218 void b43legacy_dma_rx(struct b43legacy_dmaring *ring)
 219 {
 220 }
 221 static inline
 222 void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev)
 223 {
 224 }
 225 static inline
 226 void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev)
 227 {
 228 }
 229
 230 #endif /* CONFIG_B43LEGACY_DMA */
 231 #endif /* B43legacy_DMA_H_ */