drivers/net/wireless/iwlegacy/4965.h

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __il_4965_h__
  31 #define __il_4965_h__
  32
  33 struct il_rx_queue;
  34 struct il_rx_buf;
  35 struct il_rx_pkt;
  36 struct il_tx_queue;
  37 struct il_rxon_context;
  38
  39 /* configuration for the _4965 devices */
  40 extern struct il_cfg il4965_cfg;
  41 extern const struct il_ops il4965_ops;
  42
  43 extern struct il_mod_params il4965_mod_params;
  44
  45 /* tx queue */
  46 void il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid,
  47                                int freed);
  48
  49 /* RXON */
  50 void il4965_set_rxon_chain(struct il_priv *il);
  51
  52 /* uCode */
  53 int il4965_verify_ucode(struct il_priv *il);
  54
  55 /* lib */
  56 void il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status);
  57
  58 void il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq);
  59 int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq);
  60 int il4965_hw_nic_init(struct il_priv *il);
  61 int il4965_dump_fh(struct il_priv *il, char **buf, bool display);
  62
  63 void il4965_nic_config(struct il_priv *il);
  64
  65 /* rx */
  66 void il4965_rx_queue_restock(struct il_priv *il);
  67 void il4965_rx_replenish(struct il_priv *il);
  68 void il4965_rx_replenish_now(struct il_priv *il);
  69 void il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq);
  70 int il4965_rxq_stop(struct il_priv *il);
  71 int il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band);
  72 void il4965_rx_handle(struct il_priv *il);
  73
  74 /* tx */
  75 void il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq);
  76 int il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
  77                                     dma_addr_t addr, u16 len, u8 reset, u8 pad);
  78 int il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq);
  79 void il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
  80                                  struct ieee80211_tx_info *info);
  81 int il4965_tx_skb(struct il_priv *il,
  82                   struct ieee80211_sta *sta,
  83                   struct sk_buff *skb);
  84 int il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
  85                         struct ieee80211_sta *sta, u16 tid, u16 * ssn);
  86 int il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
  87                        struct ieee80211_sta *sta, u16 tid);
  88 int il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id);
  89 int il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx);
  90 void il4965_hw_txq_ctx_free(struct il_priv *il);
  91 int il4965_txq_ctx_alloc(struct il_priv *il);
  92 void il4965_txq_ctx_reset(struct il_priv *il);
  93 void il4965_txq_ctx_stop(struct il_priv *il);
  94 void il4965_txq_set_sched(struct il_priv *il, u32 mask);
  95
  96 /*
  97  * Acquire il->lock before calling this function !
  98  */
  99 void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx);
 100 /**
 101  * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
 102  * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
 103  * @scd_retry: (1) Indicates queue will be used in aggregation mode
 104  *
 105  * NOTE:  Acquire il->lock before calling this function !
 106  */
 107 void il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
 108                                 int tx_fifo_id, int scd_retry);
 109
 110 /* scan */
 111 int il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif);
 112
 113 /* station mgmt */
 114 int il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
 115                                bool add);
 116
 117 /* hcmd */
 118 int il4965_send_beacon_cmd(struct il_priv *il);
 119
 120 #ifdef CONFIG_IWLEGACY_DEBUG
 121 const char *il4965_get_tx_fail_reason(u32 status);
 122 #else
 123 static inline const char *
 124 il4965_get_tx_fail_reason(u32 status)
 125 {
 126         return "";
 127 }
 128 #endif
 129
 130 /* station management */
 131 int il4965_alloc_bcast_station(struct il_priv *il);
 132 int il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r);
 133 int il4965_remove_default_wep_key(struct il_priv *il,
 134                                   struct ieee80211_key_conf *key);
 135 int il4965_set_default_wep_key(struct il_priv *il,
 136                                struct ieee80211_key_conf *key);
 137 int il4965_restore_default_wep_keys(struct il_priv *il);
 138 int il4965_set_dynamic_key(struct il_priv *il,
 139                            struct ieee80211_key_conf *key, u8 sta_id);
 140 int il4965_remove_dynamic_key(struct il_priv *il,
 141                               struct ieee80211_key_conf *key, u8 sta_id);
 142 void il4965_update_tkip_key(struct il_priv *il,
 143                             struct ieee80211_key_conf *keyconf,
 144                             struct ieee80211_sta *sta, u32 iv32,
 145                             u16 *phase1key);
 146 int il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid);
 147 int il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta,
 148                             int tid, u16 ssn);
 149 int il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta,
 150                            int tid);
 151 void il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt);
 152 int il4965_update_bcast_stations(struct il_priv *il);
 153
 154 /* rate */
 155 static inline u8
 156 il4965_hw_get_rate(__le32 rate_n_flags)
 157 {
 158         return le32_to_cpu(rate_n_flags) & 0xFF;
 159 }
 160
 161 /* eeprom */
 162 void il4965_eeprom_get_mac(const struct il_priv *il, u8 * mac);
 163 int il4965_eeprom_acquire_semaphore(struct il_priv *il);
 164 void il4965_eeprom_release_semaphore(struct il_priv *il);
 165 int il4965_eeprom_check_version(struct il_priv *il);
 166
 167 /* mac80211 handlers (for 4965) */
 168 void il4965_mac_tx(struct ieee80211_hw *hw,
 169                    struct ieee80211_tx_control *control,
 170                    struct sk_buff *skb);
 171 int il4965_mac_start(struct ieee80211_hw *hw);
 172 void il4965_mac_stop(struct ieee80211_hw *hw);
 173 void il4965_configure_filter(struct ieee80211_hw *hw,
 174                              unsigned int changed_flags,
 175                              unsigned int *total_flags, u64 multicast);
 176 int il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
 177                        struct ieee80211_vif *vif, struct ieee80211_sta *sta,
 178                        struct ieee80211_key_conf *key);
 179 void il4965_mac_update_tkip_key(struct ieee80211_hw *hw,
 180                                 struct ieee80211_vif *vif,
 181                                 struct ieee80211_key_conf *keyconf,
 182                                 struct ieee80211_sta *sta, u32 iv32,
 183                                 u16 *phase1key);
 184 int il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 185                             enum ieee80211_ampdu_mlme_action action,
 186                             struct ieee80211_sta *sta, u16 tid, u16 * ssn,
 187                             u8 buf_size);
 188 int il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 189                        struct ieee80211_sta *sta);
 190 void il4965_mac_channel_switch(struct ieee80211_hw *hw,
 191                                struct ieee80211_channel_switch *ch_switch);
 192
 193 void il4965_led_enable(struct il_priv *il);
 194
 195 /* EEPROM */
 196 #define IL4965_EEPROM_IMG_SIZE                  1024
 197
 198 /*
 199  * uCode queue management definitions ...
 200  * The first queue used for block-ack aggregation is #7 (4965 only).
 201  * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
 202  */
 203 #define IL49_FIRST_AMPDU_QUEUE  7
 204
 205 /* Sizes and addresses for instruction and data memory (SRAM) in
 206  * 4965's embedded processor.  Driver access is via HBUS_TARG_MEM_* regs. */
 207 #define IL49_RTC_INST_LOWER_BOUND               (0x000000)
 208 #define IL49_RTC_INST_UPPER_BOUND               (0x018000)
 209
 210 #define IL49_RTC_DATA_LOWER_BOUND               (0x800000)
 211 #define IL49_RTC_DATA_UPPER_BOUND               (0x80A000)
 212
 213 #define IL49_RTC_INST_SIZE  (IL49_RTC_INST_UPPER_BOUND - \
 214                                 IL49_RTC_INST_LOWER_BOUND)
 215 #define IL49_RTC_DATA_SIZE  (IL49_RTC_DATA_UPPER_BOUND - \
 216                                 IL49_RTC_DATA_LOWER_BOUND)
 217
 218 #define IL49_MAX_INST_SIZE IL49_RTC_INST_SIZE
 219 #define IL49_MAX_DATA_SIZE IL49_RTC_DATA_SIZE
 220
 221 /* Size of uCode instruction memory in bootstrap state machine */
 222 #define IL49_MAX_BSM_SIZE BSM_SRAM_SIZE
 223
 224 static inline int
 225 il4965_hw_valid_rtc_data_addr(u32 addr)
 226 {
 227         return (addr >= IL49_RTC_DATA_LOWER_BOUND &&
 228                 addr < IL49_RTC_DATA_UPPER_BOUND);
 229 }
 230
 231 /********************* START TEMPERATURE *************************************/
 232
 233 /**
 234  * 4965 temperature calculation.
 235  *
 236  * The driver must calculate the device temperature before calculating
 237  * a txpower setting (amplifier gain is temperature dependent).  The
 238  * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration
 239  * values used for the life of the driver, and one of which (R4) is the
 240  * real-time temperature indicator.
 241  *
 242  * uCode provides all 4 values to the driver via the "initialize alive"
 243  * notification (see struct il4965_init_alive_resp).  After the runtime uCode
 244  * image loads, uCode updates the R4 value via stats notifications
 245  * (see N_STATS), which occur after each received beacon
 246  * when associated, or can be requested via C_STATS.
 247  *
 248  * NOTE:  uCode provides the R4 value as a 23-bit signed value.  Driver
 249  *        must sign-extend to 32 bits before applying formula below.
 250  *
 251  * Formula:
 252  *
 253  * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
 254  *
 255  * NOTE:  The basic formula is 259 * (R4-R2) / (R3-R1).  The 97/100 is
 256  * an additional correction, which should be centered around 0 degrees
 257  * Celsius (273 degrees Kelvin).  The 8 (3 percent of 273) compensates for
 258  * centering the 97/100 correction around 0 degrees K.
 259  *
 260  * Add 273 to Kelvin value to find degrees Celsius, for comparing current
 261  * temperature with factory-measured temperatures when calculating txpower
 262  * settings.
 263  */
 264 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8
 265 #define TEMPERATURE_CALIB_A_VAL 259
 266
 267 /* Limit range of calculated temperature to be between these Kelvin values */
 268 #define IL_TX_POWER_TEMPERATURE_MIN  (263)
 269 #define IL_TX_POWER_TEMPERATURE_MAX  (410)
 270
 271 #define IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
 272         ((t) < IL_TX_POWER_TEMPERATURE_MIN || \
 273          (t) > IL_TX_POWER_TEMPERATURE_MAX)
 274
 275 extern void il4965_temperature_calib(struct il_priv *il);
 276 /********************* END TEMPERATURE ***************************************/
 277
 278 /********************* START TXPOWER *****************************************/
 279
 280 /**
 281  * 4965 txpower calculations rely on information from three sources:
 282  *
 283  *     1) EEPROM
 284  *     2) "initialize" alive notification
 285  *     3) stats notifications
 286  *
 287  * EEPROM data consists of:
 288  *
 289  * 1)  Regulatory information (max txpower and channel usage flags) is provided
 290  *     separately for each channel that can possibly supported by 4965.
 291  *     40 MHz wide (.11n HT40) channels are listed separately from 20 MHz
 292  *     (legacy) channels.
 293  *
 294  *     See struct il4965_eeprom_channel for format, and struct il4965_eeprom
 295  *     for locations in EEPROM.
 296  *
 297  * 2)  Factory txpower calibration information is provided separately for
 298  *     sub-bands of contiguous channels.  2.4GHz has just one sub-band,
 299  *     but 5 GHz has several sub-bands.
 300  *
 301  *     In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
 302  *
 303  *     See struct il4965_eeprom_calib_info (and the tree of structures
 304  *     contained within it) for format, and struct il4965_eeprom for
 305  *     locations in EEPROM.
 306  *
 307  * "Initialization alive" notification (see struct il4965_init_alive_resp)
 308  * consists of:
 309  *
 310  * 1)  Temperature calculation parameters.
 311  *
 312  * 2)  Power supply voltage measurement.
 313  *
 314  * 3)  Tx gain compensation to balance 2 transmitters for MIMO use.
 315  *
 316  * Statistics notifications deliver:
 317  *
 318  * 1)  Current values for temperature param R4.
 319  */
 320
 321 /**
 322  * To calculate a txpower setting for a given desired target txpower, channel,
 323  * modulation bit rate, and transmitter chain (4965 has 2 transmitters to
 324  * support MIMO and transmit diversity), driver must do the following:
 325  *
 326  * 1)  Compare desired txpower vs. (EEPROM) regulatory limit for this channel.
 327  *     Do not exceed regulatory limit; reduce target txpower if necessary.
 328  *
 329  *     If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
 330  *     2 transmitters will be used simultaneously; driver must reduce the
 331  *     regulatory limit by 3 dB (half-power) for each transmitter, so the
 332  *     combined total output of the 2 transmitters is within regulatory limits.
 333  *
 334  *
 335  * 2)  Compare target txpower vs. (EEPROM) saturation txpower *reduced by
 336  *     backoff for this bit rate*.  Do not exceed (saturation - backoff[rate]);
 337  *     reduce target txpower if necessary.
 338  *
 339  *     Backoff values below are in 1/2 dB units (equivalent to steps in
 340  *     txpower gain tables):
 341  *
 342  *     OFDM 6 - 36 MBit:  10 steps (5 dB)
 343  *     OFDM 48 MBit:      15 steps (7.5 dB)
 344  *     OFDM 54 MBit:      17 steps (8.5 dB)
 345  *     OFDM 60 MBit:      20 steps (10 dB)
 346  *     CCK all rates:     10 steps (5 dB)
 347  *
 348  *     Backoff values apply to saturation txpower on a per-transmitter basis;
 349  *     when using MIMO (2 transmitters), each transmitter uses the same
 350  *     saturation level provided in EEPROM, and the same backoff values;
 351  *     no reduction (such as with regulatory txpower limits) is required.
 352  *
 353  *     Saturation and Backoff values apply equally to 20 Mhz (legacy) channel
 354  *     widths and 40 Mhz (.11n HT40) channel widths; there is no separate
 355  *     factory measurement for ht40 channels.
 356  *
 357  *     The result of this step is the final target txpower.  The rest of
 358  *     the steps figure out the proper settings for the device to achieve
 359  *     that target txpower.
 360  *
 361  *
 362  * 3)  Determine (EEPROM) calibration sub band for the target channel, by
 363  *     comparing against first and last channels in each sub band
 364  *     (see struct il4965_eeprom_calib_subband_info).
 365  *
 366  *
 367  * 4)  Linearly interpolate (EEPROM) factory calibration measurement sets,
 368  *     referencing the 2 factory-measured (sample) channels within the sub band.
 369  *
 370  *     Interpolation is based on difference between target channel's frequency
 371  *     and the sample channels' frequencies.  Since channel numbers are based
 372  *     on frequency (5 MHz between each channel number), this is equivalent
 373  *     to interpolating based on channel number differences.
 374  *
 375  *     Note that the sample channels may or may not be the channels at the
 376  *     edges of the sub band.  The target channel may be "outside" of the
 377  *     span of the sampled channels.
 378  *
 379  *     Driver may choose the pair (for 2 Tx chains) of measurements (see
 380  *     struct il4965_eeprom_calib_ch_info) for which the actual measured
 381  *     txpower comes closest to the desired txpower.  Usually, though,
 382  *     the middle set of measurements is closest to the regulatory limits,
 383  *     and is therefore a good choice for all txpower calculations (this
 384  *     assumes that high accuracy is needed for maximizing legal txpower,
 385  *     while lower txpower configurations do not need as much accuracy).
 386  *
 387  *     Driver should interpolate both members of the chosen measurement pair,
 388  *     i.e. for both Tx chains (radio transmitters), unless the driver knows
 389  *     that only one of the chains will be used (e.g. only one tx antenna
 390  *     connected, but this should be unusual).  The rate scaling algorithm
 391  *     switches antennas to find best performance, so both Tx chains will
 392  *     be used (although only one at a time) even for non-MIMO transmissions.
 393  *
 394  *     Driver should interpolate factory values for temperature, gain table
 395  *     idx, and actual power.  The power amplifier detector values are
 396  *     not used by the driver.
 397  *
 398  *     Sanity check:  If the target channel happens to be one of the sample
 399  *     channels, the results should agree with the sample channel's
 400  *     measurements!
 401  *
 402  *
 403  * 5)  Find difference between desired txpower and (interpolated)
 404  *     factory-measured txpower.  Using (interpolated) factory gain table idx
 405  *     (shown elsewhere) as a starting point, adjust this idx lower to
 406  *     increase txpower, or higher to decrease txpower, until the target
 407  *     txpower is reached.  Each step in the gain table is 1/2 dB.
 408  *
 409  *     For example, if factory measured txpower is 16 dBm, and target txpower
 410  *     is 13 dBm, add 6 steps to the factory gain idx to reduce txpower
 411  *     by 3 dB.
 412  *
 413  *
 414  * 6)  Find difference between current device temperature and (interpolated)
 415  *     factory-measured temperature for sub-band.  Factory values are in
 416  *     degrees Celsius.  To calculate current temperature, see comments for
 417  *     "4965 temperature calculation".
 418  *
 419  *     If current temperature is higher than factory temperature, driver must
 420  *     increase gain (lower gain table idx), and vice verse.
 421  *
 422  *     Temperature affects gain differently for different channels:
 423  *
 424  *     2.4 GHz all channels:  3.5 degrees per half-dB step
 425  *     5 GHz channels 34-43:  4.5 degrees per half-dB step
 426  *     5 GHz channels >= 44:  4.0 degrees per half-dB step
 427  *
 428  *     NOTE:  Temperature can increase rapidly when transmitting, especially
 429  *            with heavy traffic at high txpowers.  Driver should update
 430  *            temperature calculations often under these conditions to
 431  *            maintain strong txpower in the face of rising temperature.
 432  *
 433  *
 434  * 7)  Find difference between current power supply voltage indicator
 435  *     (from "initialize alive") and factory-measured power supply voltage
 436  *     indicator (EEPROM).
 437  *
 438  *     If the current voltage is higher (indicator is lower) than factory
 439  *     voltage, gain should be reduced (gain table idx increased) by:
 440  *
 441  *     (eeprom - current) / 7
 442  *
 443  *     If the current voltage is lower (indicator is higher) than factory
 444  *     voltage, gain should be increased (gain table idx decreased) by:
 445  *
 446  *     2 * (current - eeprom) / 7
 447  *
 448  *     If number of idx steps in either direction turns out to be > 2,
 449  *     something is wrong ... just use 0.
 450  *
 451  *     NOTE:  Voltage compensation is independent of band/channel.
 452  *
 453  *     NOTE:  "Initialize" uCode measures current voltage, which is assumed
 454  *            to be constant after this initial measurement.  Voltage
 455  *            compensation for txpower (number of steps in gain table)
 456  *            may be calculated once and used until the next uCode bootload.
 457  *
 458  *
 459  * 8)  If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
 460  *     adjust txpower for each transmitter chain, so txpower is balanced
 461  *     between the two chains.  There are 5 pairs of tx_atten[group][chain]
 462  *     values in "initialize alive", one pair for each of 5 channel ranges:
 463  *
 464  *     Group 0:  5 GHz channel 34-43
 465  *     Group 1:  5 GHz channel 44-70
 466  *     Group 2:  5 GHz channel 71-124
 467  *     Group 3:  5 GHz channel 125-200
 468  *     Group 4:  2.4 GHz all channels
 469  *
 470  *     Add the tx_atten[group][chain] value to the idx for the target chain.
 471  *     The values are signed, but are in pairs of 0 and a non-negative number,
 472  *     so as to reduce gain (if necessary) of the "hotter" channel.  This
 473  *     avoids any need to double-check for regulatory compliance after
 474  *     this step.
 475  *
 476  *
 477  * 9)  If setting up for a CCK rate, lower the gain by adding a CCK compensation
 478  *     value to the idx:
 479  *
 480  *     Hardware rev B:  9 steps (4.5 dB)
 481  *     Hardware rev C:  5 steps (2.5 dB)
 482  *
 483  *     Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
 484  *     bits [3:2], 1 = B, 2 = C.
 485  *
 486  *     NOTE:  This compensation is in addition to any saturation backoff that
 487  *            might have been applied in an earlier step.
 488  *
 489  *
 490  * 10) Select the gain table, based on band (2.4 vs 5 GHz).
 491  *
 492  *     Limit the adjusted idx to stay within the table!
 493  *
 494  *
 495  * 11) Read gain table entries for DSP and radio gain, place into appropriate
 496  *     location(s) in command (struct il4965_txpowertable_cmd).
 497  */
 498
 499 /**
 500  * When MIMO is used (2 transmitters operating simultaneously), driver should
 501  * limit each transmitter to deliver a max of 3 dB below the regulatory limit
 502  * for the device.  That is, use half power for each transmitter, so total
 503  * txpower is within regulatory limits.
 504  *
 505  * The value "6" represents number of steps in gain table to reduce power 3 dB.
 506  * Each step is 1/2 dB.
 507  */
 508 #define IL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
 509
 510 /**
 511  * CCK gain compensation.
 512  *
 513  * When calculating txpowers for CCK, after making sure that the target power
 514  * is within regulatory and saturation limits, driver must additionally
 515  * back off gain by adding these values to the gain table idx.
 516  *
 517  * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG,
 518  * bits [3:2], 1 = B, 2 = C.
 519  */
 520 #define IL_TX_POWER_CCK_COMPENSATION_B_STEP (9)
 521 #define IL_TX_POWER_CCK_COMPENSATION_C_STEP (5)
 522
 523 /*
 524  * 4965 power supply voltage compensation for txpower
 525  */
 526 #define TX_POWER_IL_VOLTAGE_CODES_PER_03V   (7)
 527
 528 /**
 529  * Gain tables.
 530  *
 531  * The following tables contain pair of values for setting txpower, i.e.
 532  * gain settings for the output of the device's digital signal processor (DSP),
 533  * and for the analog gain structure of the transmitter.
 534  *
 535  * Each entry in the gain tables represents a step of 1/2 dB.  Note that these
 536  * are *relative* steps, not indications of absolute output power.  Output
 537  * power varies with temperature, voltage, and channel frequency, and also
 538  * requires consideration of average power (to satisfy regulatory constraints),
 539  * and peak power (to avoid distortion of the output signal).
 540  *
 541  * Each entry contains two values:
 542  * 1)  DSP gain (or sometimes called DSP attenuation).  This is a fine-grained
 543  *     linear value that multiplies the output of the digital signal processor,
 544  *     before being sent to the analog radio.
 545  * 2)  Radio gain.  This sets the analog gain of the radio Tx path.
 546  *     It is a coarser setting, and behaves in a logarithmic (dB) fashion.
 547  *
 548  * EEPROM contains factory calibration data for txpower.  This maps actual
 549  * measured txpower levels to gain settings in the "well known" tables
 550  * below ("well-known" means here that both factory calibration *and* the
 551  * driver work with the same table).
 552  *
 553  * There are separate tables for 2.4 GHz and 5 GHz bands.  The 5 GHz table
 554  * has an extension (into negative idxes), in case the driver needs to
 555  * boost power setting for high device temperatures (higher than would be
 556  * present during factory calibration).  A 5 Ghz EEPROM idx of "40"
 557  * corresponds to the 49th entry in the table used by the driver.
 558  */
 559 #define MIN_TX_GAIN_IDX         (0)     /* highest gain, lowest idx, 2.4 */
 560 #define MIN_TX_GAIN_IDX_52GHZ_EXT       (-9)    /* highest gain, lowest idx, 5 */
 561
 562 /**
 563  * 2.4 GHz gain table
 564  *
 565  * Index    Dsp gain   Radio gain
 566  *   0        110         0x3f      (highest gain)
 567  *   1        104         0x3f
 568  *   2         98         0x3f
 569  *   3        110         0x3e
 570  *   4        104         0x3e
 571  *   5         98         0x3e
 572  *   6        110         0x3d
 573  *   7        104         0x3d
 574  *   8         98         0x3d
 575  *   9        110         0x3c
 576  *  10        104         0x3c
 577  *  11         98         0x3c
 578  *  12        110         0x3b
 579  *  13        104         0x3b
 580  *  14         98         0x3b
 581  *  15        110         0x3a
 582  *  16        104         0x3a
 583  *  17         98         0x3a
 584  *  18        110         0x39
 585  *  19        104         0x39
 586  *  20         98         0x39
 587  *  21        110         0x38
 588  *  22        104         0x38
 589  *  23         98         0x38
 590  *  24        110         0x37
 591  *  25        104         0x37
 592  *  26         98         0x37
 593  *  27        110         0x36
 594  *  28        104         0x36
 595  *  29         98         0x36
 596  *  30        110         0x35
 597  *  31        104         0x35
 598  *  32         98         0x35
 599  *  33        110         0x34
 600  *  34        104         0x34
 601  *  35         98         0x34
 602  *  36        110         0x33
 603  *  37        104         0x33
 604  *  38         98         0x33
 605  *  39        110         0x32
 606  *  40        104         0x32
 607  *  41         98         0x32
 608  *  42        110         0x31
 609  *  43        104         0x31
 610  *  44         98         0x31
 611  *  45        110         0x30
 612  *  46        104         0x30
 613  *  47         98         0x30
 614  *  48        110          0x6
 615  *  49        104          0x6
 616  *  50         98          0x6
 617  *  51        110          0x5
 618  *  52        104          0x5
 619  *  53         98          0x5
 620  *  54        110          0x4
 621  *  55        104          0x4
 622  *  56         98          0x4
 623  *  57        110          0x3
 624  *  58        104          0x3
 625  *  59         98          0x3
 626  *  60        110          0x2
 627  *  61        104          0x2
 628  *  62         98          0x2
 629  *  63        110          0x1
 630  *  64        104          0x1
 631  *  65         98          0x1
 632  *  66        110          0x0
 633  *  67        104          0x0
 634  *  68         98          0x0
 635  *  69         97            0
 636  *  70         96            0
 637  *  71         95            0
 638  *  72         94            0
 639  *  73         93            0
 640  *  74         92            0
 641  *  75         91            0
 642  *  76         90            0
 643  *  77         89            0
 644  *  78         88            0
 645  *  79         87            0
 646  *  80         86            0
 647  *  81         85            0
 648  *  82         84            0
 649  *  83         83            0
 650  *  84         82            0
 651  *  85         81            0
 652  *  86         80            0
 653  *  87         79            0
 654  *  88         78            0
 655  *  89         77            0
 656  *  90         76            0
 657  *  91         75            0
 658  *  92         74            0
 659  *  93         73            0
 660  *  94         72            0
 661  *  95         71            0
 662  *  96         70            0
 663  *  97         69            0
 664  *  98         68            0
 665  */
 666
 667 /**
 668  * 5 GHz gain table
 669  *
 670  * Index    Dsp gain   Radio gain
 671  *  -9        123         0x3F      (highest gain)
 672  *  -8        117         0x3F
 673  *  -7        110         0x3F
 674  *  -6        104         0x3F
 675  *  -5         98         0x3F
 676  *  -4        110         0x3E
 677  *  -3        104         0x3E
 678  *  -2         98         0x3E
 679  *  -1        110         0x3D
 680  *   0        104         0x3D
 681  *   1         98         0x3D
 682  *   2        110         0x3C
 683  *   3        104         0x3C
 684  *   4         98         0x3C
 685  *   5        110         0x3B
 686  *   6        104         0x3B
 687  *   7         98         0x3B
 688  *   8        110         0x3A
 689  *   9        104         0x3A
 690  *  10         98         0x3A
 691  *  11        110         0x39
 692  *  12        104         0x39
 693  *  13         98         0x39
 694  *  14        110         0x38
 695  *  15        104         0x38
 696  *  16         98         0x38
 697  *  17        110         0x37
 698  *  18        104         0x37
 699  *  19         98         0x37
 700  *  20        110         0x36
 701  *  21        104         0x36
 702  *  22         98         0x36
 703  *  23        110         0x35
 704  *  24        104         0x35
 705  *  25         98         0x35
 706  *  26        110         0x34
 707  *  27        104         0x34
 708  *  28         98         0x34
 709  *  29        110         0x33
 710  *  30        104         0x33
 711  *  31         98         0x33
 712  *  32        110         0x32
 713  *  33        104         0x32
 714  *  34         98         0x32
 715  *  35        110         0x31
 716  *  36        104         0x31
 717  *  37         98         0x31
 718  *  38        110         0x30
 719  *  39        104         0x30
 720  *  40         98         0x30
 721  *  41        110         0x25
 722  *  42        104         0x25
 723  *  43         98         0x25
 724  *  44        110         0x24
 725  *  45        104         0x24
 726  *  46         98         0x24
 727  *  47        110         0x23
 728  *  48        104         0x23
 729  *  49         98         0x23
 730  *  50        110         0x22
 731  *  51        104         0x18
 732  *  52         98         0x18
 733  *  53        110         0x17
 734  *  54        104         0x17
 735  *  55         98         0x17
 736  *  56        110         0x16
 737  *  57        104         0x16
 738  *  58         98         0x16
 739  *  59        110         0x15
 740  *  60        104         0x15
 741  *  61         98         0x15
 742  *  62        110         0x14
 743  *  63        104         0x14
 744  *  64         98         0x14
 745  *  65        110         0x13
 746  *  66        104         0x13
 747  *  67         98         0x13
 748  *  68        110         0x12
 749  *  69        104         0x08
 750  *  70         98         0x08
 751  *  71        110         0x07
 752  *  72        104         0x07
 753  *  73         98         0x07
 754  *  74        110         0x06
 755  *  75        104         0x06
 756  *  76         98         0x06
 757  *  77        110         0x05
 758  *  78        104         0x05
 759  *  79         98         0x05
 760  *  80        110         0x04
 761  *  81        104         0x04
 762  *  82         98         0x04
 763  *  83        110         0x03
 764  *  84        104         0x03
 765  *  85         98         0x03
 766  *  86        110         0x02
 767  *  87        104         0x02
 768  *  88         98         0x02
 769  *  89        110         0x01
 770  *  90        104         0x01
 771  *  91         98         0x01
 772  *  92        110         0x00
 773  *  93        104         0x00
 774  *  94         98         0x00
 775  *  95         93         0x00
 776  *  96         88         0x00
 777  *  97         83         0x00
 778  *  98         78         0x00
 779  */
 780
 781 /**
 782  * Sanity checks and default values for EEPROM regulatory levels.
 783  * If EEPROM values fall outside MIN/MAX range, use default values.
 784  *
 785  * Regulatory limits refer to the maximum average txpower allowed by
 786  * regulatory agencies in the geographies in which the device is meant
 787  * to be operated.  These limits are SKU-specific (i.e. geography-specific),
 788  * and channel-specific; each channel has an individual regulatory limit
 789  * listed in the EEPROM.
 790  *
 791  * Units are in half-dBm (i.e. "34" means 17 dBm).
 792  */
 793 #define IL_TX_POWER_DEFAULT_REGULATORY_24   (34)
 794 #define IL_TX_POWER_DEFAULT_REGULATORY_52   (34)
 795 #define IL_TX_POWER_REGULATORY_MIN          (0)
 796 #define IL_TX_POWER_REGULATORY_MAX          (34)
 797
 798 /**
 799  * Sanity checks and default values for EEPROM saturation levels.
 800  * If EEPROM values fall outside MIN/MAX range, use default values.
 801  *
 802  * Saturation is the highest level that the output power amplifier can produce
 803  * without significant clipping distortion.  This is a "peak" power level.
 804  * Different types of modulation (i.e. various "rates", and OFDM vs. CCK)
 805  * require differing amounts of backoff, relative to their average power output,
 806  * in order to avoid clipping distortion.
 807  *
 808  * Driver must make sure that it is violating neither the saturation limit,
 809  * nor the regulatory limit, when calculating Tx power settings for various
 810  * rates.
 811  *
 812  * Units are in half-dBm (i.e. "38" means 19 dBm).
 813  */
 814 #define IL_TX_POWER_DEFAULT_SATURATION_24   (38)
 815 #define IL_TX_POWER_DEFAULT_SATURATION_52   (38)
 816 #define IL_TX_POWER_SATURATION_MIN          (20)
 817 #define IL_TX_POWER_SATURATION_MAX          (50)
 818
 819 /**
 820  * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance)
 821  * and thermal Txpower calibration.
 822  *
 823  * When calculating txpower, driver must compensate for current device
 824  * temperature; higher temperature requires higher gain.  Driver must calculate
 825  * current temperature (see "4965 temperature calculation"), then compare vs.
 826  * factory calibration temperature in EEPROM; if current temperature is higher
 827  * than factory temperature, driver must *increase* gain by proportions shown
 828  * in table below.  If current temperature is lower than factory, driver must
 829  * *decrease* gain.
 830  *
 831  * Different frequency ranges require different compensation, as shown below.
 832  */
 833 /* Group 0, 5.2 GHz ch 34-43:  4.5 degrees per 1/2 dB. */
 834 #define CALIB_IL_TX_ATTEN_GR1_FCH 34
 835 #define CALIB_IL_TX_ATTEN_GR1_LCH 43
 836
 837 /* Group 1, 5.3 GHz ch 44-70:  4.0 degrees per 1/2 dB. */
 838 #define CALIB_IL_TX_ATTEN_GR2_FCH 44
 839 #define CALIB_IL_TX_ATTEN_GR2_LCH 70
 840
 841 /* Group 2, 5.5 GHz ch 71-124:  4.0 degrees per 1/2 dB. */
 842 #define CALIB_IL_TX_ATTEN_GR3_FCH 71
 843 #define CALIB_IL_TX_ATTEN_GR3_LCH 124
 844
 845 /* Group 3, 5.7 GHz ch 125-200:  4.0 degrees per 1/2 dB. */
 846 #define CALIB_IL_TX_ATTEN_GR4_FCH 125
 847 #define CALIB_IL_TX_ATTEN_GR4_LCH 200
 848
 849 /* Group 4, 2.4 GHz all channels:  3.5 degrees per 1/2 dB. */
 850 #define CALIB_IL_TX_ATTEN_GR5_FCH 1
 851 #define CALIB_IL_TX_ATTEN_GR5_LCH 20
 852
 853 enum {
 854         CALIB_CH_GROUP_1 = 0,
 855         CALIB_CH_GROUP_2 = 1,
 856         CALIB_CH_GROUP_3 = 2,
 857         CALIB_CH_GROUP_4 = 3,
 858         CALIB_CH_GROUP_5 = 4,
 859         CALIB_CH_GROUP_MAX
 860 };
 861
 862 /********************* END TXPOWER *****************************************/
 863
 864 /**
 865  * Tx/Rx Queues
 866  *
 867  * Most communication between driver and 4965 is via queues of data buffers.
 868  * For example, all commands that the driver issues to device's embedded
 869  * controller (uCode) are via the command queue (one of the Tx queues).  All
 870  * uCode command responses/replies/notifications, including Rx frames, are
 871  * conveyed from uCode to driver via the Rx queue.
 872  *
 873  * Most support for these queues, including handshake support, resides in
 874  * structures in host DRAM, shared between the driver and the device.  When
 875  * allocating this memory, the driver must make sure that data written by
 876  * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's
 877  * cache memory), so DRAM and cache are consistent, and the device can
 878  * immediately see changes made by the driver.
 879  *
 880  * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via
 881  * up to 7 DMA channels (FIFOs).  Each Tx queue is supported by a circular array
 882  * in DRAM containing 256 Transmit Frame Descriptors (TFDs).
 883  */
 884 #define IL49_NUM_FIFOS  7
 885 #define IL49_CMD_FIFO_NUM       4
 886 #define IL49_NUM_QUEUES 16
 887 #define IL49_NUM_AMPDU_QUEUES   8
 888
 889 /**
 890  * struct il4965_schedq_bc_tbl
 891  *
 892  * Byte Count table
 893  *
 894  * Each Tx queue uses a byte-count table containing 320 entries:
 895  * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that
 896  * duplicate the first 64 entries (to avoid wrap-around within a Tx win;
 897  * max Tx win is 64 TFDs).
 898  *
 899  * When driver sets up a new TFD, it must also enter the total byte count
 900  * of the frame to be transmitted into the corresponding entry in the byte
 901  * count table for the chosen Tx queue.  If the TFD idx is 0-63, the driver
 902  * must duplicate the byte count entry in corresponding idx 256-319.
 903  *
 904  * padding puts each byte count table on a 1024-byte boundary;
 905  * 4965 assumes tables are separated by 1024 bytes.
 906  */
 907 struct il4965_scd_bc_tbl {
 908         __le16 tfd_offset[TFD_QUEUE_BC_SIZE];
 909         u8 pad[1024 - (TFD_QUEUE_BC_SIZE) * sizeof(__le16)];
 910 } __packed;
 911
 912 #define IL4965_RTC_INST_LOWER_BOUND             (0x000000)
 913
 914 /* RSSI to dBm */
 915 #define IL4965_RSSI_OFFSET      44
 916
 917 /* PCI registers */
 918 #define PCI_CFG_RETRY_TIMEOUT   0x041
 919
 920 #define IL4965_DEFAULT_TX_RETRY  15
 921
 922 /* EEPROM */
 923 #define IL4965_FIRST_AMPDU_QUEUE        10
 924
 925 /* Calibration */
 926 void il4965_chain_noise_calibration(struct il_priv *il, void *stat_resp);
 927 void il4965_sensitivity_calibration(struct il_priv *il, void *resp);
 928 void il4965_init_sensitivity(struct il_priv *il);
 929 void il4965_reset_run_time_calib(struct il_priv *il);
 930
 931 /* Debug */
 932 #ifdef CONFIG_IWLEGACY_DEBUGFS
 933 extern const struct il_debugfs_ops il4965_debugfs_ops;
 934 #endif
 935
 936 /****************************/
 937 /* Flow Handler Definitions */
 938 /****************************/
 939
 940 /**
 941  * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
 942  * Addresses are offsets from device's PCI hardware base address.
 943  */
 944 #define FH49_MEM_LOWER_BOUND                   (0x1000)
 945 #define FH49_MEM_UPPER_BOUND                   (0x2000)
 946
 947 /**
 948  * Keep-Warm (KW) buffer base address.
 949  *
 950  * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
 951  * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
 952  * DRAM access when 4965 is Txing or Rxing.  The dummy accesses prevent host
 953  * from going into a power-savings mode that would cause higher DRAM latency,
 954  * and possible data over/under-runs, before all Tx/Rx is complete.
 955  *
 956  * Driver loads FH49_KW_MEM_ADDR_REG with the physical address (bits 35:4)
 957  * of the buffer, which must be 4K aligned.  Once this is set up, the 4965
 958  * automatically invokes keep-warm accesses when normal accesses might not
 959  * be sufficient to maintain fast DRAM response.
 960  *
 961  * Bit fields:
 962  *  31-0:  Keep-warm buffer physical base address [35:4], must be 4K aligned
 963  */
 964 #define FH49_KW_MEM_ADDR_REG                 (FH49_MEM_LOWER_BOUND + 0x97C)
 965
 966 /**
 967  * TFD Circular Buffers Base (CBBC) addresses
 968  *
 969  * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
 970  * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
 971  * (see struct il_tfd_frame).  These 16 pointer registers are offset by 0x04
 972  * bytes from one another.  Each TFD circular buffer in DRAM must be 256-byte
 973  * aligned (address bits 0-7 must be 0).
 974  *
 975  * Bit fields in each pointer register:
 976  *  27-0: TFD CB physical base address [35:8], must be 256-byte aligned
 977  */
 978 #define FH49_MEM_CBBC_LOWER_BOUND          (FH49_MEM_LOWER_BOUND + 0x9D0)
 979 #define FH49_MEM_CBBC_UPPER_BOUND          (FH49_MEM_LOWER_BOUND + 0xA10)
 980
 981 /* Find TFD CB base pointer for given queue (range 0-15). */
 982 #define FH49_MEM_CBBC_QUEUE(x)  (FH49_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
 983
 984 /**
 985  * Rx SRAM Control and Status Registers (RSCSR)
 986  *
 987  * These registers provide handshake between driver and 4965 for the Rx queue
 988  * (this queue handles *all* command responses, notifications, Rx data, etc.
 989  * sent from 4965 uCode to host driver).  Unlike Tx, there is only one Rx
 990  * queue, and only one Rx DMA/FIFO channel.  Also unlike Tx, which can
 991  * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
 992  * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
 993  * mapping between RBDs and RBs.
 994  *
 995  * Driver must allocate host DRAM memory for the following, and set the
 996  * physical address of each into 4965 registers:
 997  *
 998  * 1)  Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
 999  *     entries (although any power of 2, up to 4096, is selectable by driver).
1000  *     Each entry (1 dword) points to a receive buffer (RB) of consistent size
1001  *     (typically 4K, although 8K or 16K are also selectable by driver).
1002  *     Driver sets up RB size and number of RBDs in the CB via Rx config
1003  *     register FH49_MEM_RCSR_CHNL0_CONFIG_REG.
1004  *
1005  *     Bit fields within one RBD:
1006  *     27-0:  Receive Buffer physical address bits [35:8], 256-byte aligned
1007  *
1008  *     Driver sets physical address [35:8] of base of RBD circular buffer
1009  *     into FH49_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1010  *
1011  * 2)  Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
1012  *     (RBs) have been filled, via a "write pointer", actually the idx of
1013  *     the RB's corresponding RBD within the circular buffer.  Driver sets
1014  *     physical address [35:4] into FH49_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1015  *
1016  *     Bit fields in lower dword of Rx status buffer (upper dword not used
1017  *     by driver; see struct il4965_shared, val0):
1018  *     31-12:  Not used by driver
1019  *     11- 0:  Index of last filled Rx buffer descriptor
1020  *             (4965 writes, driver reads this value)
1021  *
1022  * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
1023  * enter pointers to these RBs into contiguous RBD circular buffer entries,
1024  * and update the 4965's "write" idx register,
1025  * FH49_RSCSR_CHNL0_RBDCB_WPTR_REG.
1026  *
1027  * This "write" idx corresponds to the *next* RBD that the driver will make
1028  * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1029  * the circular buffer.  This value should initially be 0 (before preparing any
1030  * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1031  * wrap back to 0 at the end of the circular buffer (but don't wrap before
1032  * "read" idx has advanced past 1!  See below).
1033  * NOTE:  4965 EXPECTS THE WRITE IDX TO BE INCREMENTED IN MULTIPLES OF 8.
1034  *
1035  * As the 4965 fills RBs (referenced from contiguous RBDs within the circular
1036  * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1037  * to tell the driver the idx of the latest filled RBD.  The driver must
1038  * read this "read" idx from DRAM after receiving an Rx interrupt from 4965.
1039  *
1040  * The driver must also internally keep track of a third idx, which is the
1041  * next RBD to process.  When receiving an Rx interrupt, driver should process
1042  * all filled but unprocessed RBs up to, but not including, the RB
1043  * corresponding to the "read" idx.  For example, if "read" idx becomes "1",
1044  * driver may process the RB pointed to by RBD 0.  Depending on volume of
1045  * traffic, there may be many RBs to process.
1046  *
1047  * If read idx == write idx, 4965 thinks there is no room to put new data.
1048  * Due to this, the maximum number of filled RBs is 255, instead of 256.  To
1049  * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1050  * and "read" idxes; that is, make sure that there are no more than 254
1051  * buffers waiting to be filled.
1052  */
1053 #define FH49_MEM_RSCSR_LOWER_BOUND      (FH49_MEM_LOWER_BOUND + 0xBC0)
1054 #define FH49_MEM_RSCSR_UPPER_BOUND      (FH49_MEM_LOWER_BOUND + 0xC00)
1055 #define FH49_MEM_RSCSR_CHNL0            (FH49_MEM_RSCSR_LOWER_BOUND)
1056
1057 /**
1058  * Physical base address of 8-byte Rx Status buffer.
1059  * Bit fields:
1060  *  31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1061  */
1062 #define FH49_RSCSR_CHNL0_STTS_WPTR_REG  (FH49_MEM_RSCSR_CHNL0)
1063
1064 /**
1065  * Physical base address of Rx Buffer Descriptor Circular Buffer.
1066  * Bit fields:
1067  *  27-0:  RBD CD physical base address [35:8], must be 256-byte aligned.
1068  */
1069 #define FH49_RSCSR_CHNL0_RBDCB_BASE_REG (FH49_MEM_RSCSR_CHNL0 + 0x004)
1070
1071 /**
1072  * Rx write pointer (idx, really!).
1073  * Bit fields:
1074  *  11-0:  Index of driver's most recent prepared-to-be-filled RBD, + 1.
1075  *         NOTE:  For 256-entry circular buffer, use only bits [7:0].
1076  */
1077 #define FH49_RSCSR_CHNL0_RBDCB_WPTR_REG (FH49_MEM_RSCSR_CHNL0 + 0x008)
1078 #define FH49_RSCSR_CHNL0_WPTR        (FH49_RSCSR_CHNL0_RBDCB_WPTR_REG)
1079
1080 /**
1081  * Rx Config/Status Registers (RCSR)
1082  * Rx Config Reg for channel 0 (only channel used)
1083  *
1084  * Driver must initialize FH49_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1085  * normal operation (see bit fields).
1086  *
1087  * Clearing FH49_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1088  * Driver should poll FH49_MEM_RSSR_RX_STATUS_REG       for
1089  * FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1090  *
1091  * Bit fields:
1092  * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1093  *        '10' operate normally
1094  * 29-24: reserved
1095  * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1096  *        min "5" for 32 RBDs, max "12" for 4096 RBDs.
1097  * 19-18: reserved
1098  * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1099  *        '10' 12K, '11' 16K.
1100  * 15-14: reserved
1101  * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1102  * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1103  *        typical value 0x10 (about 1/2 msec)
1104  *  3- 0: reserved
1105  */
1106 #define FH49_MEM_RCSR_LOWER_BOUND      (FH49_MEM_LOWER_BOUND + 0xC00)
1107 #define FH49_MEM_RCSR_UPPER_BOUND      (FH49_MEM_LOWER_BOUND + 0xCC0)
1108 #define FH49_MEM_RCSR_CHNL0            (FH49_MEM_RCSR_LOWER_BOUND)
1109
1110 #define FH49_MEM_RCSR_CHNL0_CONFIG_REG  (FH49_MEM_RCSR_CHNL0)
1111
1112 #define FH49_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0)   /* bits 4-11 */
1113 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK   (0x00001000)   /* bits 12 */
1114 #define FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1115 #define FH49_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK   (0x00030000)    /* bits 16-17 */
1116 #define FH49_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000)   /* bits 20-23 */
1117 #define FH49_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000)  /* bits 30-31 */
1118
1119 #define FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS      (20)
1120 #define FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS    (4)
1121 #define RX_RB_TIMEOUT   (0x10)
1122
1123 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL         (0x00000000)
1124 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL     (0x40000000)
1125 #define FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL        (0x80000000)
1126
1127 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K    (0x00000000)
1128 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K    (0x00010000)
1129 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K   (0x00020000)
1130 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K   (0x00030000)
1131
1132 #define FH49_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY              (0x00000004)
1133 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL    (0x00000000)
1134 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL  (0x00001000)
1135
1136 /**
1137  * Rx Shared Status Registers (RSSR)
1138  *
1139  * After stopping Rx DMA channel (writing 0 to
1140  * FH49_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1141  * FH49_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1142  *
1143  * Bit fields:
1144  *  24:  1 = Channel 0 is idle
1145  *
1146  * FH49_MEM_RSSR_SHARED_CTRL_REG and FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1147  * contain default values that should not be altered by the driver.
1148  */
1149 #define FH49_MEM_RSSR_LOWER_BOUND           (FH49_MEM_LOWER_BOUND + 0xC40)
1150 #define FH49_MEM_RSSR_UPPER_BOUND           (FH49_MEM_LOWER_BOUND + 0xD00)
1151
1152 #define FH49_MEM_RSSR_SHARED_CTRL_REG       (FH49_MEM_RSSR_LOWER_BOUND)
1153 #define FH49_MEM_RSSR_RX_STATUS_REG     (FH49_MEM_RSSR_LOWER_BOUND + 0x004)
1154 #define FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1155                                         (FH49_MEM_RSSR_LOWER_BOUND + 0x008)
1156
1157 #define FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE     (0x01000000)
1158
1159 #define FH49_MEM_TFDIB_REG1_ADDR_BITSHIFT       28
1160
1161 /* TFDB  Area - TFDs buffer table */
1162 #define FH49_MEM_TFDIB_DRAM_ADDR_LSB_MSK      (0xFFFFFFFF)
1163 #define FH49_TFDIB_LOWER_BOUND       (FH49_MEM_LOWER_BOUND + 0x900)
1164 #define FH49_TFDIB_UPPER_BOUND       (FH49_MEM_LOWER_BOUND + 0x958)
1165 #define FH49_TFDIB_CTRL0_REG(_chnl)  (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1166 #define FH49_TFDIB_CTRL1_REG(_chnl)  (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1167
1168 /**
1169  * Transmit DMA Channel Control/Status Registers (TCSR)
1170  *
1171  * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
1172  * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1173  * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1174  *
1175  * To use a Tx DMA channel, driver must initialize its
1176  * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1177  *
1178  * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1179  * FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1180  *
1181  * All other bits should be 0.
1182  *
1183  * Bit fields:
1184  * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1185  *        '10' operate normally
1186  * 29- 4: Reserved, set to "0"
1187  *     3: Enable internal DMA requests (1, normal operation), disable (0)
1188  *  2- 0: Reserved, set to "0"
1189  */
1190 #define FH49_TCSR_LOWER_BOUND  (FH49_MEM_LOWER_BOUND + 0xD00)
1191 #define FH49_TCSR_UPPER_BOUND  (FH49_MEM_LOWER_BOUND + 0xE60)
1192
1193 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1194 #define FH49_TCSR_CHNL_NUM                            (7)
1195 #define FH50_TCSR_CHNL_NUM                            (8)
1196
1197 /* TCSR: tx_config register values */
1198 #define FH49_TCSR_CHNL_TX_CONFIG_REG(_chnl)     \
1199                 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1200 #define FH49_TCSR_CHNL_TX_CREDIT_REG(_chnl)     \
1201                 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1202 #define FH49_TCSR_CHNL_TX_BUF_STS_REG(_chnl)    \
1203                 (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1204
1205 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF                (0x00000000)
1206 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV                (0x00000001)
1207
1208 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE  (0x00000000)
1209 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE   (0x00000008)
1210
1211 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT     (0x00000000)
1212 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD    (0x00100000)
1213 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD     (0x00200000)
1214
1215 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT      (0x00000000)
1216 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD     (0x00400000)
1217 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD      (0x00800000)
1218
1219 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE      (0x00000000)
1220 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF  (0x40000000)
1221 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE     (0x80000000)
1222
1223 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY    (0x00000000)
1224 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT     (0x00002000)
1225 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID    (0x00000003)
1226
1227 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM                (20)
1228 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX                (12)
1229
1230 /**
1231  * Tx Shared Status Registers (TSSR)
1232  *
1233  * After stopping Tx DMA channel (writing 0 to
1234  * FH49_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1235  * FH49_TSSR_TX_STATUS_REG until selected Tx channel is idle
1236  * (channel's buffers empty | no pending requests).
1237  *
1238  * Bit fields:
1239  * 31-24:  1 = Channel buffers empty (channel 7:0)
1240  * 23-16:  1 = No pending requests (channel 7:0)
1241  */
1242 #define FH49_TSSR_LOWER_BOUND           (FH49_MEM_LOWER_BOUND + 0xEA0)
1243 #define FH49_TSSR_UPPER_BOUND           (FH49_MEM_LOWER_BOUND + 0xEC0)
1244
1245 #define FH49_TSSR_TX_STATUS_REG         (FH49_TSSR_LOWER_BOUND + 0x010)
1246
1247 /**
1248  * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1249  * 31:  Indicates an address error when accessed to internal memory
1250  *      uCode/driver must write "1" in order to clear this flag
1251  * 30:  Indicates that Host did not send the expected number of dwords to FH
1252  *      uCode/driver must write "1" in order to clear this flag
1253  * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1254  *      command was received from the scheduler while the TRB was already full
1255  *      with previous command
1256  *      uCode/driver must write "1" in order to clear this flag
1257  * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1258  *      bit is set, it indicates that the FH has received a full indication
1259  *      from the RTC TxFIFO and the current value of the TxCredit counter was
1260  *      not equal to zero. This mean that the credit mechanism was not
1261  *      synchronized to the TxFIFO status
1262  *      uCode/driver must write "1" in order to clear this flag
1263  */
1264 #define FH49_TSSR_TX_ERROR_REG          (FH49_TSSR_LOWER_BOUND + 0x018)
1265
1266 #define FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1267
1268 /* Tx service channels */
1269 #define FH49_SRVC_CHNL          (9)
1270 #define FH49_SRVC_LOWER_BOUND   (FH49_MEM_LOWER_BOUND + 0x9C8)
1271 #define FH49_SRVC_UPPER_BOUND   (FH49_MEM_LOWER_BOUND + 0x9D0)
1272 #define FH49_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1273                 (FH49_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1274
1275 #define FH49_TX_CHICKEN_BITS_REG        (FH49_MEM_LOWER_BOUND + 0xE98)
1276 /* Instruct FH to increment the retry count of a packet when
1277  * it is brought from the memory to TX-FIFO
1278  */
1279 #define FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN  (0x00000002)
1280
1281 /* Keep Warm Size */
1282 #define IL_KW_SIZE 0x1000       /* 4k */
1283
1284 #endif /* __il_4965_h__ */