ARM: mm: Recreate kernel mappings in early_paging_init()
[linux/fpc-iii.git] / drivers / net / wireless / iwlwifi / iwl-nvm-parse.c
blobb76a9a8fc0b3dbe831f74ce7d20a811e6cf17ada
1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
6 * GPL LICENSE SUMMARY
8 * Copyright(c) 2008 - 2013 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
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21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
24 * The full GNU General Public License is included in this distribution
25 * in the file called COPYING.
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28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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33 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
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37 * modification, are permitted provided that the following conditions
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50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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61 *****************************************************************************/
62 #include <linux/types.h>
63 #include <linux/slab.h>
64 #include <linux/export.h>
65 #include "iwl-drv.h"
66 #include "iwl-modparams.h"
67 #include "iwl-nvm-parse.h"
69 /* NVM offsets (in words) definitions */
70 enum wkp_nvm_offsets {
71 /* NVM HW-Section offset (in words) definitions */
72 HW_ADDR = 0x15,
74 /* NVM SW-Section offset (in words) definitions */
75 NVM_SW_SECTION = 0x1C0,
76 NVM_VERSION = 0,
77 RADIO_CFG = 1,
78 SKU = 2,
79 N_HW_ADDRS = 3,
80 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
82 /* NVM calibration section offset (in words) definitions */
83 NVM_CALIB_SECTION = 0x2B8,
84 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION
87 /* SKU Capabilities (actual values from NVM definition) */
88 enum nvm_sku_bits {
89 NVM_SKU_CAP_BAND_24GHZ = BIT(0),
90 NVM_SKU_CAP_BAND_52GHZ = BIT(1),
91 NVM_SKU_CAP_11N_ENABLE = BIT(2),
92 NVM_SKU_CAP_11AC_ENABLE = BIT(3),
95 /* radio config bits (actual values from NVM definition) */
96 #define NVM_RF_CFG_DASH_MSK(x) (x & 0x3) /* bits 0-1 */
97 #define NVM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
98 #define NVM_RF_CFG_TYPE_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
99 #define NVM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
100 #define NVM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
101 #define NVM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
104 * These are the channel numbers in the order that they are stored in the NVM
106 static const u8 iwl_nvm_channels[] = {
107 /* 2.4 GHz */
108 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
109 /* 5 GHz */
110 36, 40, 44 , 48, 52, 56, 60, 64,
111 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
112 149, 153, 157, 161, 165
115 #define IWL_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
116 #define NUM_2GHZ_CHANNELS 14
117 #define FIRST_2GHZ_HT_MINUS 5
118 #define LAST_2GHZ_HT_PLUS 9
119 #define LAST_5GHZ_HT 161
121 #define DEFAULT_MAX_TX_POWER 16
123 /* rate data (static) */
124 static struct ieee80211_rate iwl_cfg80211_rates[] = {
125 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
126 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
127 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
128 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
129 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
130 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
131 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
132 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
133 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
134 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
135 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
136 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
137 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
138 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
139 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
141 #define RATES_24_OFFS 0
142 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
143 #define RATES_52_OFFS 4
144 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
147 * enum iwl_nvm_channel_flags - channel flags in NVM
148 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
149 * @NVM_CHANNEL_IBSS: usable as an IBSS channel
150 * @NVM_CHANNEL_ACTIVE: active scanning allowed
151 * @NVM_CHANNEL_RADAR: radar detection required
152 * @NVM_CHANNEL_DFS: dynamic freq selection candidate
153 * @NVM_CHANNEL_WIDE: 20 MHz channel okay (?)
154 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay (?)
155 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay (?)
156 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay (?)
158 enum iwl_nvm_channel_flags {
159 NVM_CHANNEL_VALID = BIT(0),
160 NVM_CHANNEL_IBSS = BIT(1),
161 NVM_CHANNEL_ACTIVE = BIT(3),
162 NVM_CHANNEL_RADAR = BIT(4),
163 NVM_CHANNEL_DFS = BIT(7),
164 NVM_CHANNEL_WIDE = BIT(8),
165 NVM_CHANNEL_40MHZ = BIT(9),
166 NVM_CHANNEL_80MHZ = BIT(10),
167 NVM_CHANNEL_160MHZ = BIT(11),
170 #define CHECK_AND_PRINT_I(x) \
171 ((ch_flags & NVM_CHANNEL_##x) ? # x " " : "")
173 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
174 struct iwl_nvm_data *data,
175 const __le16 * const nvm_ch_flags)
177 int ch_idx;
178 int n_channels = 0;
179 struct ieee80211_channel *channel;
180 u16 ch_flags;
181 bool is_5ghz;
183 for (ch_idx = 0; ch_idx < IWL_NUM_CHANNELS; ch_idx++) {
184 ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx);
185 if (!(ch_flags & NVM_CHANNEL_VALID)) {
186 IWL_DEBUG_EEPROM(dev,
187 "Ch. %d Flags %x [%sGHz] - No traffic\n",
188 iwl_nvm_channels[ch_idx],
189 ch_flags,
190 (ch_idx >= NUM_2GHZ_CHANNELS) ?
191 "5.2" : "2.4");
192 continue;
195 channel = &data->channels[n_channels];
196 n_channels++;
198 channel->hw_value = iwl_nvm_channels[ch_idx];
199 channel->band = (ch_idx < NUM_2GHZ_CHANNELS) ?
200 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
201 channel->center_freq =
202 ieee80211_channel_to_frequency(
203 channel->hw_value, channel->band);
205 /* TODO: Need to be dependent to the NVM */
206 channel->flags = IEEE80211_CHAN_NO_HT40;
207 if (ch_idx < NUM_2GHZ_CHANNELS &&
208 (ch_flags & NVM_CHANNEL_40MHZ)) {
209 if (iwl_nvm_channels[ch_idx] <= LAST_2GHZ_HT_PLUS)
210 channel->flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
211 if (iwl_nvm_channels[ch_idx] >= FIRST_2GHZ_HT_MINUS)
212 channel->flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
213 } else if (iwl_nvm_channels[ch_idx] <= LAST_5GHZ_HT &&
214 (ch_flags & NVM_CHANNEL_40MHZ)) {
215 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
216 channel->flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
217 else
218 channel->flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
220 if (!(ch_flags & NVM_CHANNEL_80MHZ))
221 channel->flags |= IEEE80211_CHAN_NO_80MHZ;
222 if (!(ch_flags & NVM_CHANNEL_160MHZ))
223 channel->flags |= IEEE80211_CHAN_NO_160MHZ;
225 if (!(ch_flags & NVM_CHANNEL_IBSS))
226 channel->flags |= IEEE80211_CHAN_NO_IBSS;
228 if (!(ch_flags & NVM_CHANNEL_ACTIVE))
229 channel->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
231 if (ch_flags & NVM_CHANNEL_RADAR)
232 channel->flags |= IEEE80211_CHAN_RADAR;
234 /* Initialize regulatory-based run-time data */
237 * Default value - highest tx power value. max_power
238 * is not used in mvm, and is used for backwards compatibility
240 channel->max_power = DEFAULT_MAX_TX_POWER;
241 is_5ghz = channel->band == IEEE80211_BAND_5GHZ;
242 IWL_DEBUG_EEPROM(dev,
243 "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n",
244 channel->hw_value,
245 is_5ghz ? "5.2" : "2.4",
246 CHECK_AND_PRINT_I(VALID),
247 CHECK_AND_PRINT_I(IBSS),
248 CHECK_AND_PRINT_I(ACTIVE),
249 CHECK_AND_PRINT_I(RADAR),
250 CHECK_AND_PRINT_I(WIDE),
251 CHECK_AND_PRINT_I(DFS),
252 ch_flags,
253 channel->max_power,
254 ((ch_flags & NVM_CHANNEL_IBSS) &&
255 !(ch_flags & NVM_CHANNEL_RADAR))
256 ? "" : "not ");
259 return n_channels;
262 static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg,
263 struct iwl_nvm_data *data,
264 struct ieee80211_sta_vht_cap *vht_cap)
266 vht_cap->vht_supported = true;
268 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
269 IEEE80211_VHT_CAP_RXSTBC_1 |
270 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
271 7 << IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
273 if (iwlwifi_mod_params.amsdu_size_8K)
274 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
276 vht_cap->vht_mcs.rx_mcs_map =
277 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
278 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
279 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
280 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
281 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
282 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
283 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
284 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
286 if (data->valid_rx_ant == 1 || cfg->rx_with_siso_diversity) {
287 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN |
288 IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
289 /* this works because NOT_SUPPORTED == 3 */
290 vht_cap->vht_mcs.rx_mcs_map |=
291 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
294 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
297 static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
298 struct iwl_nvm_data *data, const __le16 *nvm_sw,
299 bool enable_vht, u8 tx_chains, u8 rx_chains)
301 int n_channels = iwl_init_channel_map(dev, cfg, data,
302 &nvm_sw[NVM_CHANNELS]);
303 int n_used = 0;
304 struct ieee80211_supported_band *sband;
306 sband = &data->bands[IEEE80211_BAND_2GHZ];
307 sband->band = IEEE80211_BAND_2GHZ;
308 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
309 sband->n_bitrates = N_RATES_24;
310 n_used += iwl_init_sband_channels(data, sband, n_channels,
311 IEEE80211_BAND_2GHZ);
312 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_2GHZ,
313 tx_chains, rx_chains);
315 sband = &data->bands[IEEE80211_BAND_5GHZ];
316 sband->band = IEEE80211_BAND_5GHZ;
317 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
318 sband->n_bitrates = N_RATES_52;
319 n_used += iwl_init_sband_channels(data, sband, n_channels,
320 IEEE80211_BAND_5GHZ);
321 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_5GHZ,
322 tx_chains, rx_chains);
323 if (enable_vht)
324 iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap);
326 if (n_channels != n_used)
327 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
328 n_used, n_channels);
331 struct iwl_nvm_data *
332 iwl_parse_nvm_data(struct device *dev, const struct iwl_cfg *cfg,
333 const __le16 *nvm_hw, const __le16 *nvm_sw,
334 const __le16 *nvm_calib, u8 tx_chains, u8 rx_chains)
336 struct iwl_nvm_data *data;
337 u8 hw_addr[ETH_ALEN];
338 u16 radio_cfg, sku;
340 data = kzalloc(sizeof(*data) +
341 sizeof(struct ieee80211_channel) * IWL_NUM_CHANNELS,
342 GFP_KERNEL);
343 if (!data)
344 return NULL;
346 data->nvm_version = le16_to_cpup(nvm_sw + NVM_VERSION);
348 radio_cfg = le16_to_cpup(nvm_sw + RADIO_CFG);
349 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
350 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
351 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
352 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
353 data->valid_tx_ant = NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
354 data->valid_rx_ant = NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
356 sku = le16_to_cpup(nvm_sw + SKU);
357 data->sku_cap_band_24GHz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
358 data->sku_cap_band_52GHz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
359 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
360 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
361 data->sku_cap_11n_enable = false;
363 /* check overrides (some devices have wrong NVM) */
364 if (cfg->valid_tx_ant)
365 data->valid_tx_ant = cfg->valid_tx_ant;
366 if (cfg->valid_rx_ant)
367 data->valid_rx_ant = cfg->valid_rx_ant;
369 if (!data->valid_tx_ant || !data->valid_rx_ant) {
370 IWL_ERR_DEV(dev, "invalid antennas (0x%x, 0x%x)\n",
371 data->valid_tx_ant, data->valid_rx_ant);
372 kfree(data);
373 return NULL;
376 data->n_hw_addrs = le16_to_cpup(nvm_sw + N_HW_ADDRS);
378 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
379 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
381 /* The byte order is little endian 16 bit, meaning 214365 */
382 memcpy(hw_addr, nvm_hw + HW_ADDR, ETH_ALEN);
383 data->hw_addr[0] = hw_addr[1];
384 data->hw_addr[1] = hw_addr[0];
385 data->hw_addr[2] = hw_addr[3];
386 data->hw_addr[3] = hw_addr[2];
387 data->hw_addr[4] = hw_addr[5];
388 data->hw_addr[5] = hw_addr[4];
390 iwl_init_sbands(dev, cfg, data, nvm_sw, sku & NVM_SKU_CAP_11AC_ENABLE,
391 tx_chains, rx_chains);
393 data->calib_version = 255; /* TODO:
394 this value will prevent some checks from
395 failing, we need to check if this
396 field is still needed, and if it does,
397 where is it in the NVM*/
399 return data;
401 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);