drivers/net/wireless/rt2x00/rt2800pci.h

   1 /*
   2         Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10         <http://rt2x00.serialmonkey.com>
  11
  12         This program is free software; you can redistribute it and/or modify
  13         it under the terms of the GNU General Public License as published by
  14         the Free Software Foundation; either version 2 of the License, or
  15         (at your option) any later version.
  16
  17         This program is distributed in the hope that it will be useful,
  18         but WITHOUT ANY WARRANTY; without even the implied warranty of
  19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20         GNU General Public License for more details.
  21
  22         You should have received a copy of the GNU General Public License
  23         along with this program; if not, write to the
  24         Free Software Foundation, Inc.,
  25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  */
  27
  28 /*
  29         Module: rt2800pci
  30         Abstract: Data structures and registers for the rt2800pci module.
  31         Supported chipsets: RT2800E & RT2800ED.
  32  */
  33
  34 #ifndef RT2800PCI_H
  35 #define RT2800PCI_H
  36
  37 /*
  38  * Queue register offset macros
  39  */
  40 #define TX_QUEUE_REG_OFFSET             0x10
  41 #define TX_BASE_PTR(__x)                (TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET))
  42 #define TX_MAX_CNT(__x)                 (TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET))
  43 #define TX_CTX_IDX(__x)                 (TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET))
  44 #define TX_DTX_IDX(__x)                 (TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET))
  45
  46 /*
  47  * 8051 firmware image.
  48  */
  49 #define FIRMWARE_RT2860                 "rt2860.bin"
  50 #define FIRMWARE_RT3290                 "rt3290.bin"
  51 #define FIRMWARE_IMAGE_BASE             0x2000
  52
  53 /*
  54  * DMA descriptor defines.
  55  */
  56 #define TXD_DESC_SIZE                   (4 * sizeof(__le32))
  57 #define RXD_DESC_SIZE                   (4 * sizeof(__le32))
  58
  59 /*
  60  * TX descriptor format for TX, PRIO and Beacon Ring.
  61  */
  62
  63 /*
  64  * Word0
  65  */
  66 #define TXD_W0_SD_PTR0                  FIELD32(0xffffffff)
  67
  68 /*
  69  * Word1
  70  */
  71 #define TXD_W1_SD_LEN1                  FIELD32(0x00003fff)
  72 #define TXD_W1_LAST_SEC1                FIELD32(0x00004000)
  73 #define TXD_W1_BURST                    FIELD32(0x00008000)
  74 #define TXD_W1_SD_LEN0                  FIELD32(0x3fff0000)
  75 #define TXD_W1_LAST_SEC0                FIELD32(0x40000000)
  76 #define TXD_W1_DMA_DONE                 FIELD32(0x80000000)
  77
  78 /*
  79  * Word2
  80  */
  81 #define TXD_W2_SD_PTR1                  FIELD32(0xffffffff)
  82
  83 /*
  84  * Word3
  85  * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
  86  * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
  87  *       0:MGMT, 1:HCCA 2:EDCA
  88  */
  89 #define TXD_W3_WIV                      FIELD32(0x01000000)
  90 #define TXD_W3_QSEL                     FIELD32(0x06000000)
  91 #define TXD_W3_TCO                      FIELD32(0x20000000)
  92 #define TXD_W3_UCO                      FIELD32(0x40000000)
  93 #define TXD_W3_ICO                      FIELD32(0x80000000)
  94
  95 /*
  96  * RX descriptor format for RX Ring.
  97  */
  98
  99 /*
 100  * Word0
 101  */
 102 #define RXD_W0_SDP0                     FIELD32(0xffffffff)
 103
 104 /*
 105  * Word1
 106  */
 107 #define RXD_W1_SDL1                     FIELD32(0x00003fff)
 108 #define RXD_W1_SDL0                     FIELD32(0x3fff0000)
 109 #define RXD_W1_LS0                      FIELD32(0x40000000)
 110 #define RXD_W1_DMA_DONE                 FIELD32(0x80000000)
 111
 112 /*
 113  * Word2
 114  */
 115 #define RXD_W2_SDP1                     FIELD32(0xffffffff)
 116
 117 /*
 118  * Word3
 119  * AMSDU: RX with 802.3 header, not 802.11 header.
 120  * DECRYPTED: This frame is being decrypted.
 121  */
 122 #define RXD_W3_BA                       FIELD32(0x00000001)
 123 #define RXD_W3_DATA                     FIELD32(0x00000002)
 124 #define RXD_W3_NULLDATA                 FIELD32(0x00000004)
 125 #define RXD_W3_FRAG                     FIELD32(0x00000008)
 126 #define RXD_W3_UNICAST_TO_ME            FIELD32(0x00000010)
 127 #define RXD_W3_MULTICAST                FIELD32(0x00000020)
 128 #define RXD_W3_BROADCAST                FIELD32(0x00000040)
 129 #define RXD_W3_MY_BSS                   FIELD32(0x00000080)
 130 #define RXD_W3_CRC_ERROR                FIELD32(0x00000100)
 131 #define RXD_W3_CIPHER_ERROR             FIELD32(0x00000600)
 132 #define RXD_W3_AMSDU                    FIELD32(0x00000800)
 133 #define RXD_W3_HTC                      FIELD32(0x00001000)
 134 #define RXD_W3_RSSI                     FIELD32(0x00002000)
 135 #define RXD_W3_L2PAD                    FIELD32(0x00004000)
 136 #define RXD_W3_AMPDU                    FIELD32(0x00008000)
 137 #define RXD_W3_DECRYPTED                FIELD32(0x00010000)
 138 #define RXD_W3_PLCP_SIGNAL              FIELD32(0x00020000)
 139 #define RXD_W3_PLCP_RSSI                FIELD32(0x00040000)
 140
 141 #endif /* RT2800PCI_H */