drivers/misc/mei/hw-txe.c

   1 /*
   2  *
   3  * Intel Management Engine Interface (Intel MEI) Linux driver
   4  * Copyright (c) 2013-2014, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13  * more details.
  14  *
  15  */
  16
  17 #include <linux/pci.h>
  18 #include <linux/jiffies.h>
  19 #include <linux/delay.h>
  20 #include <linux/kthread.h>
  21 #include <linux/irqreturn.h>
  22
  23 #include <linux/mei.h>
  24
  25 #include "mei_dev.h"
  26 #include "hw-txe.h"
  27 #include "client.h"
  28 #include "hbm.h"
  29
  30 /**
  31  * mei_txe_reg_read - Reads 32bit data from the device
  32  *
  33  * @base_addr: registers base address
  34  * @offset: register offset
  35  *
  36  */
  37 static inline u32 mei_txe_reg_read(void __iomem *base_addr,
  38                                         unsigned long offset)
  39 {
  40         return ioread32(base_addr + offset);
  41 }
  42
  43 /**
  44  * mei_txe_reg_write - Writes 32bit data to the device
  45  *
  46  * @base_addr: registers base address
  47  * @offset: register offset
  48  * @value: the value to write
  49  */
  50 static inline void mei_txe_reg_write(void __iomem *base_addr,
  51                                 unsigned long offset, u32 value)
  52 {
  53         iowrite32(value, base_addr + offset);
  54 }
  55
  56 /**
  57  * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR
  58  *
  59  * @dev: the device structure
  60  * @offset: register offset
  61  *
  62  * Doesn't check for aliveness while Reads 32bit data from the SeC BAR
  63  */
  64 static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw,
  65                                 unsigned long offset)
  66 {
  67         return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset);
  68 }
  69
  70 /**
  71  * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR
  72  *
  73  * @dev: the device structure
  74  * @offset: register offset
  75  *
  76  * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set
  77  */
  78 static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw,
  79                                 unsigned long offset)
  80 {
  81         WARN(!hw->aliveness, "sec read: aliveness not asserted\n");
  82         return mei_txe_sec_reg_read_silent(hw, offset);
  83 }
  84 /**
  85  * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR
  86  *   doesn't check for aliveness
  87  *
  88  * @hw: the txe hardware structure
  89  * @offset: register offset
  90  * @value: value to write
  91  *
  92  * Doesn't check for aliveness while writes 32bit data from to the SeC BAR
  93  */
  94 static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw,
  95                                 unsigned long offset, u32 value)
  96 {
  97         mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value);
  98 }
  99
 100 /**
 101  * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR
 102  *
 103  * @hw: the txe hardware structure
 104  * @offset: register offset
 105  * @value: value to write
 106  *
 107  * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set
 108  */
 109 static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw,
 110                                 unsigned long offset, u32 value)
 111 {
 112         WARN(!hw->aliveness, "sec write: aliveness not asserted\n");
 113         mei_txe_sec_reg_write_silent(hw, offset, value);
 114 }
 115 /**
 116  * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR
 117  *
 118  * @hw: the device structure
 119  * @offset: offset from which to read the data
 120  *
 121  */
 122 static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw,
 123                                 unsigned long offset)
 124 {
 125         return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset);
 126 }
 127
 128 /**
 129  * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR
 130  *
 131  * @hw: the txe hardware structure
 132  * @offset: offset from which to write the data
 133  * @value: the byte to write
 134  */
 135 static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw,
 136                                 unsigned long offset, u32 value)
 137 {
 138         mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value);
 139 }
 140
 141 /**
 142  * mei_txe_aliveness_set - request for aliveness change
 143  *
 144  * @dev: the device structure
 145  * @req: requested aliveness value
 146  *
 147  * Request for aliveness change and returns true if the change is
 148  *   really needed and false if aliveness is already
 149  *   in the requested state
 150  * Requires device lock to be held
 151  */
 152 static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req)
 153 {
 154
 155         struct mei_txe_hw *hw = to_txe_hw(dev);
 156         bool do_req = hw->aliveness != req;
 157
 158         dev_dbg(dev->dev, "Aliveness current=%d request=%d\n",
 159                                 hw->aliveness, req);
 160         if (do_req) {
 161                 dev->pg_event = MEI_PG_EVENT_WAIT;
 162                 mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req);
 163         }
 164         return do_req;
 165 }
 166
 167
 168 /**
 169  * mei_txe_aliveness_req_get - get aliveness requested register value
 170  *
 171  * @dev: the device structure
 172  *
 173  * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from
 174  * from HICR_HOST_ALIVENESS_REQ register value
 175  */
 176 static u32 mei_txe_aliveness_req_get(struct mei_device *dev)
 177 {
 178         struct mei_txe_hw *hw = to_txe_hw(dev);
 179         u32 reg;
 180
 181         reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG);
 182         return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED;
 183 }
 184
 185 /**
 186  * mei_txe_aliveness_get - get aliveness response register value
 187  * @dev: the device structure
 188  *
 189  * Extract HICR_HOST_ALIVENESS_RESP_ACK bit
 190  * from HICR_HOST_ALIVENESS_RESP register value
 191  */
 192 static u32 mei_txe_aliveness_get(struct mei_device *dev)
 193 {
 194         struct mei_txe_hw *hw = to_txe_hw(dev);
 195         u32 reg;
 196
 197         reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG);
 198         return reg & HICR_HOST_ALIVENESS_RESP_ACK;
 199 }
 200
 201 /**
 202  * mei_txe_aliveness_poll - waits for aliveness to settle
 203  *
 204  * @dev: the device structure
 205  * @expected: expected aliveness value
 206  *
 207  * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
 208  *
 209  * Return: > 0 if the expected value was received, -ETIME otherwise
 210  */
 211 static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected)
 212 {
 213         struct mei_txe_hw *hw = to_txe_hw(dev);
 214         int t = 0;
 215
 216         do {
 217                 hw->aliveness = mei_txe_aliveness_get(dev);
 218                 if (hw->aliveness == expected) {
 219                         dev->pg_event = MEI_PG_EVENT_IDLE;
 220                         dev_dbg(dev->dev,
 221                                 "aliveness settled after %d msecs\n", t);
 222                         return t;
 223                 }
 224                 mutex_unlock(&dev->device_lock);
 225                 msleep(MSEC_PER_SEC / 5);
 226                 mutex_lock(&dev->device_lock);
 227                 t += MSEC_PER_SEC / 5;
 228         } while (t < SEC_ALIVENESS_WAIT_TIMEOUT);
 229
 230         dev->pg_event = MEI_PG_EVENT_IDLE;
 231         dev_err(dev->dev, "aliveness timed out\n");
 232         return -ETIME;
 233 }
 234
 235 /**
 236  * mei_txe_aliveness_wait - waits for aliveness to settle
 237  *
 238  * @dev: the device structure
 239  * @expected: expected aliveness value
 240  *
 241  * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
 242  *
 243  * Return: 0 on success and < 0 otherwise
 244  */
 245 static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected)
 246 {
 247         struct mei_txe_hw *hw = to_txe_hw(dev);
 248         const unsigned long timeout =
 249                         msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT);
 250         long err;
 251         int ret;
 252
 253         hw->aliveness = mei_txe_aliveness_get(dev);
 254         if (hw->aliveness == expected)
 255                 return 0;
 256
 257         mutex_unlock(&dev->device_lock);
 258         err = wait_event_timeout(hw->wait_aliveness_resp,
 259                         dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
 260         mutex_lock(&dev->device_lock);
 261
 262         hw->aliveness = mei_txe_aliveness_get(dev);
 263         ret = hw->aliveness == expected ? 0 : -ETIME;
 264
 265         if (ret)
 266                 dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n",
 267                         err, hw->aliveness, dev->pg_event);
 268         else
 269                 dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n",
 270                         jiffies_to_msecs(timeout - err),
 271                         hw->aliveness, dev->pg_event);
 272
 273         dev->pg_event = MEI_PG_EVENT_IDLE;
 274         return ret;
 275 }
 276
 277 /**
 278  * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete
 279  *
 280  * @dev: the device structure
 281  *
 282  * Return: 0 on success and < 0 otherwise
 283  */
 284 int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req)
 285 {
 286         if (mei_txe_aliveness_set(dev, req))
 287                 return mei_txe_aliveness_wait(dev, req);
 288         return 0;
 289 }
 290
 291 /**
 292  * mei_txe_pg_is_enabled - detect if PG is supported by HW
 293  *
 294  * @dev: the device structure
 295  *
 296  * Return: true is pg supported, false otherwise
 297  */
 298 static bool mei_txe_pg_is_enabled(struct mei_device *dev)
 299 {
 300         return true;
 301 }
 302
 303 /**
 304  * mei_txe_pg_state  - translate aliveness register value
 305  *   to the mei power gating state
 306  *
 307  * @dev: the device structure
 308  *
 309  * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
 310  */
 311 static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev)
 312 {
 313         struct mei_txe_hw *hw = to_txe_hw(dev);
 314
 315         return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON;
 316 }
 317
 318 /**
 319  * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt
 320  *
 321  * @dev: the device structure
 322  */
 323 static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev)
 324 {
 325         struct mei_txe_hw *hw = to_txe_hw(dev);
 326         u32 hintmsk;
 327         /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */
 328         hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG);
 329         hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY;
 330         mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk);
 331 }
 332
 333 /**
 334  * mei_txe_input_doorbell_set - sets bit 0 in
 335  *    SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL.
 336  *
 337  * @hw: the txe hardware structure
 338  */
 339 static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw)
 340 {
 341         /* Clear the interrupt cause */
 342         clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause);
 343         mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1);
 344 }
 345
 346 /**
 347  * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1
 348  *
 349  * @hw: the txe hardware structure
 350  */
 351 static void mei_txe_output_ready_set(struct mei_txe_hw *hw)
 352 {
 353         mei_txe_br_reg_write(hw,
 354                         SICR_SEC_IPC_OUTPUT_STATUS_REG,
 355                         SEC_IPC_OUTPUT_STATUS_RDY);
 356 }
 357
 358 /**
 359  * mei_txe_is_input_ready - check if TXE is ready for receiving data
 360  *
 361  * @dev: the device structure
 362  */
 363 static bool mei_txe_is_input_ready(struct mei_device *dev)
 364 {
 365         struct mei_txe_hw *hw = to_txe_hw(dev);
 366         u32 status;
 367
 368         status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG);
 369         return !!(SEC_IPC_INPUT_STATUS_RDY & status);
 370 }
 371
 372 /**
 373  * mei_txe_intr_clear - clear all interrupts
 374  *
 375  * @dev: the device structure
 376  */
 377 static inline void mei_txe_intr_clear(struct mei_device *dev)
 378 {
 379         struct mei_txe_hw *hw = to_txe_hw(dev);
 380
 381         mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG,
 382                 SEC_IPC_HOST_INT_STATUS_PENDING);
 383         mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK);
 384         mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK);
 385 }
 386
 387 /**
 388  * mei_txe_intr_disable - disable all interrupts
 389  *
 390  * @dev: the device structure
 391  */
 392 static void mei_txe_intr_disable(struct mei_device *dev)
 393 {
 394         struct mei_txe_hw *hw = to_txe_hw(dev);
 395
 396         mei_txe_br_reg_write(hw, HHIER_REG, 0);
 397         mei_txe_br_reg_write(hw, HIER_REG, 0);
 398 }
 399 /**
 400  * mei_txe_intr_disable - enable all interrupts
 401  *
 402  * @dev: the device structure
 403  */
 404 static void mei_txe_intr_enable(struct mei_device *dev)
 405 {
 406         struct mei_txe_hw *hw = to_txe_hw(dev);
 407
 408         mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK);
 409         mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK);
 410 }
 411
 412 /**
 413  * mei_txe_pending_interrupts - check if there are pending interrupts
 414  *      only Aliveness, Input ready, and output doorbell are of relevance
 415  *
 416  * @dev: the device structure
 417  *
 418  * Checks if there are pending interrupts
 419  * only Aliveness, Readiness, Input ready, and Output doorbell are relevant
 420  */
 421 static bool mei_txe_pending_interrupts(struct mei_device *dev)
 422 {
 423
 424         struct mei_txe_hw *hw = to_txe_hw(dev);
 425         bool ret = (hw->intr_cause & (TXE_INTR_READINESS |
 426                                       TXE_INTR_ALIVENESS |
 427                                       TXE_INTR_IN_READY  |
 428                                       TXE_INTR_OUT_DB));
 429
 430         if (ret) {
 431                 dev_dbg(dev->dev,
 432                         "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n",
 433                         !!(hw->intr_cause & TXE_INTR_IN_READY),
 434                         !!(hw->intr_cause & TXE_INTR_READINESS),
 435                         !!(hw->intr_cause & TXE_INTR_ALIVENESS),
 436                         !!(hw->intr_cause & TXE_INTR_OUT_DB));
 437         }
 438         return ret;
 439 }
 440
 441 /**
 442  * mei_txe_input_payload_write - write a dword to the host buffer
 443  *      at offset idx
 444  *
 445  * @dev: the device structure
 446  * @idx: index in the host buffer
 447  * @value: value
 448  */
 449 static void mei_txe_input_payload_write(struct mei_device *dev,
 450                         unsigned long idx, u32 value)
 451 {
 452         struct mei_txe_hw *hw = to_txe_hw(dev);
 453
 454         mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG +
 455                         (idx * sizeof(u32)), value);
 456 }
 457
 458 /**
 459  * mei_txe_out_data_read - read dword from the device buffer
 460  *      at offset idx
 461  *
 462  * @dev: the device structure
 463  * @idx: index in the device buffer
 464  *
 465  * Return: register value at index
 466  */
 467 static u32 mei_txe_out_data_read(const struct mei_device *dev,
 468                                         unsigned long idx)
 469 {
 470         struct mei_txe_hw *hw = to_txe_hw(dev);
 471
 472         return mei_txe_br_reg_read(hw,
 473                 BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32)));
 474 }
 475
 476 /* Readiness */
 477
 478 /**
 479  * mei_txe_readiness_set_host_rdy
 480  *
 481  * @dev: the device structure
 482  */
 483 static void mei_txe_readiness_set_host_rdy(struct mei_device *dev)
 484 {
 485         struct mei_txe_hw *hw = to_txe_hw(dev);
 486
 487         mei_txe_br_reg_write(hw,
 488                 SICR_HOST_IPC_READINESS_REQ_REG,
 489                 SICR_HOST_IPC_READINESS_HOST_RDY);
 490 }
 491
 492 /**
 493  * mei_txe_readiness_clear
 494  *
 495  * @dev: the device structure
 496  */
 497 static void mei_txe_readiness_clear(struct mei_device *dev)
 498 {
 499         struct mei_txe_hw *hw = to_txe_hw(dev);
 500
 501         mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG,
 502                                 SICR_HOST_IPC_READINESS_RDY_CLR);
 503 }
 504 /**
 505  * mei_txe_readiness_get - Reads and returns
 506  *      the HICR_SEC_IPC_READINESS register value
 507  *
 508  * @dev: the device structure
 509  *
 510  * Return: the HICR_SEC_IPC_READINESS register value
 511  */
 512 static u32 mei_txe_readiness_get(struct mei_device *dev)
 513 {
 514         struct mei_txe_hw *hw = to_txe_hw(dev);
 515
 516         return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
 517 }
 518
 519
 520 /**
 521  * mei_txe_readiness_is_sec_rdy - check readiness
 522  *  for HICR_SEC_IPC_READINESS_SEC_RDY
 523  *
 524  * @readiness - cached readiness state
 525  */
 526 static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness)
 527 {
 528         return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY);
 529 }
 530
 531 /**
 532  * mei_txe_hw_is_ready - check if the hw is ready
 533  *
 534  * @dev: the device structure
 535  */
 536 static bool mei_txe_hw_is_ready(struct mei_device *dev)
 537 {
 538         u32 readiness =  mei_txe_readiness_get(dev);
 539
 540         return mei_txe_readiness_is_sec_rdy(readiness);
 541 }
 542
 543 /**
 544  * mei_txe_host_is_ready - check if the host is ready
 545  *
 546  * @dev: the device structure
 547  */
 548 static inline bool mei_txe_host_is_ready(struct mei_device *dev)
 549 {
 550         struct mei_txe_hw *hw = to_txe_hw(dev);
 551         u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
 552
 553         return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY);
 554 }
 555
 556 /**
 557  * mei_txe_readiness_wait - wait till readiness settles
 558  *
 559  * @dev: the device structure
 560  *
 561  * Return: 0 on success and -ETIME on timeout
 562  */
 563 static int mei_txe_readiness_wait(struct mei_device *dev)
 564 {
 565         if (mei_txe_hw_is_ready(dev))
 566                 return 0;
 567
 568         mutex_unlock(&dev->device_lock);
 569         wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready,
 570                         msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT));
 571         mutex_lock(&dev->device_lock);
 572         if (!dev->recvd_hw_ready) {
 573                 dev_err(dev->dev, "wait for readiness failed\n");
 574                 return -ETIME;
 575         }
 576
 577         dev->recvd_hw_ready = false;
 578         return 0;
 579 }
 580
 581 const struct mei_fw_status mei_txe_fw_sts = {
 582         .count = 2,
 583         .status[0] = PCI_CFG_TXE_FW_STS0,
 584         .status[1] = PCI_CFG_TXE_FW_STS1
 585 };
 586
 587 /**
 588  * mei_txe_fw_status - read fw status register from pci config space
 589  *
 590  * @dev: mei device
 591  * @fw_status: fw status register values
 592  */
 593 static int mei_txe_fw_status(struct mei_device *dev,
 594                              struct mei_fw_status *fw_status)
 595 {
 596         const struct mei_fw_status *fw_src = &mei_txe_fw_sts;
 597         struct pci_dev *pdev = to_pci_dev(dev->dev);
 598         int ret;
 599         int i;
 600
 601         if (!fw_status)
 602                 return -EINVAL;
 603
 604         fw_status->count = fw_src->count;
 605         for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
 606                 ret = pci_read_config_dword(pdev,
 607                         fw_src->status[i], &fw_status->status[i]);
 608                 if (ret)
 609                         return ret;
 610         }
 611
 612         return 0;
 613 }
 614
 615 /**
 616  *  mei_txe_hw_config - configure hardware at the start of the devices
 617  *
 618  * @dev: the device structure
 619  *
 620  * Configure hardware at the start of the device should be done only
 621  *   once at the device probe time
 622  */
 623 static void mei_txe_hw_config(struct mei_device *dev)
 624 {
 625
 626         struct mei_txe_hw *hw = to_txe_hw(dev);
 627
 628         /* Doesn't change in runtime */
 629         dev->hbuf_depth = PAYLOAD_SIZE / 4;
 630
 631         hw->aliveness = mei_txe_aliveness_get(dev);
 632         hw->readiness = mei_txe_readiness_get(dev);
 633
 634         dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n",
 635                 hw->aliveness, hw->readiness);
 636 }
 637
 638
 639 /**
 640  * mei_txe_write - writes a message to device.
 641  *
 642  * @dev: the device structure
 643  * @header: header of message
 644  * @buf: message buffer will be written
 645  *
 646  * Return: if success, 0 - otherwise.
 647  */
 648
 649 static int mei_txe_write(struct mei_device *dev,
 650                 struct mei_msg_hdr *header, unsigned char *buf)
 651 {
 652         struct mei_txe_hw *hw = to_txe_hw(dev);
 653         unsigned long rem;
 654         unsigned long length;
 655         int slots = dev->hbuf_depth;
 656         u32 *reg_buf = (u32 *)buf;
 657         u32 dw_cnt;
 658         int i;
 659
 660         if (WARN_ON(!header || !buf))
 661                 return -EINVAL;
 662
 663         length = header->length;
 664
 665         dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
 666
 667         dw_cnt = mei_data2slots(length);
 668         if (dw_cnt > slots)
 669                 return -EMSGSIZE;
 670
 671         if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n"))
 672                 return -EAGAIN;
 673
 674         /* Enable Input Ready Interrupt. */
 675         mei_txe_input_ready_interrupt_enable(dev);
 676
 677         if (!mei_txe_is_input_ready(dev)) {
 678                 struct mei_fw_status fw_status;
 679
 680                 mei_fw_status(dev, &fw_status);
 681                 dev_err(dev->dev, "Input is not ready " FW_STS_FMT "\n",
 682                         FW_STS_PRM(fw_status));
 683                 return -EAGAIN;
 684         }
 685
 686         mei_txe_input_payload_write(dev, 0, *((u32 *)header));
 687
 688         for (i = 0; i < length / 4; i++)
 689                 mei_txe_input_payload_write(dev, i + 1, reg_buf[i]);
 690
 691         rem = length & 0x3;
 692         if (rem > 0) {
 693                 u32 reg = 0;
 694
 695                 memcpy(&reg, &buf[length - rem], rem);
 696                 mei_txe_input_payload_write(dev, i + 1, reg);
 697         }
 698
 699         /* after each write the whole buffer is consumed */
 700         hw->slots = 0;
 701
 702         /* Set Input-Doorbell */
 703         mei_txe_input_doorbell_set(hw);
 704
 705         return 0;
 706 }
 707
 708 /**
 709  * mei_txe_hbuf_max_len - mimics the me hbuf circular buffer
 710  *
 711  * @dev: the device structure
 712  *
 713  * Return: PAYLOAD_SIZE - 4
 714  */
 715 static size_t mei_txe_hbuf_max_len(const struct mei_device *dev)
 716 {
 717         return PAYLOAD_SIZE - sizeof(struct mei_msg_hdr);
 718 }
 719
 720 /**
 721  * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer
 722  *
 723  * @dev: the device structure
 724  *
 725  * Return: always hbuf_depth
 726  */
 727 static int mei_txe_hbuf_empty_slots(struct mei_device *dev)
 728 {
 729         struct mei_txe_hw *hw = to_txe_hw(dev);
 730
 731         return hw->slots;
 732 }
 733
 734 /**
 735  * mei_txe_count_full_read_slots - mimics the me device circular buffer
 736  *
 737  * @dev: the device structure
 738  *
 739  * Return: always buffer size in dwords count
 740  */
 741 static int mei_txe_count_full_read_slots(struct mei_device *dev)
 742 {
 743         /* read buffers has static size */
 744         return  PAYLOAD_SIZE / 4;
 745 }
 746
 747 /**
 748  * mei_txe_read_hdr - read message header which is always in 4 first bytes
 749  *
 750  * @dev: the device structure
 751  *
 752  * Return: mei message header
 753  */
 754
 755 static u32 mei_txe_read_hdr(const struct mei_device *dev)
 756 {
 757         return mei_txe_out_data_read(dev, 0);
 758 }
 759 /**
 760  * mei_txe_read - reads a message from the txe device.
 761  *
 762  * @dev: the device structure
 763  * @buf: message buffer will be written
 764  * @len: message size will be read
 765  *
 766  * Return: -EINVAL on error wrong argument and 0 on success
 767  */
 768 static int mei_txe_read(struct mei_device *dev,
 769                 unsigned char *buf, unsigned long len)
 770 {
 771
 772         struct mei_txe_hw *hw = to_txe_hw(dev);
 773         u32 *reg_buf, reg;
 774         u32 rem;
 775         u32 i;
 776
 777         if (WARN_ON(!buf || !len))
 778                 return -EINVAL;
 779
 780         reg_buf = (u32 *)buf;
 781         rem = len & 0x3;
 782
 783         dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n",
 784                 len, mei_txe_out_data_read(dev, 0));
 785
 786         for (i = 0; i < len / 4; i++) {
 787                 /* skip header: index starts from 1 */
 788                 reg = mei_txe_out_data_read(dev, i + 1);
 789                 dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg);
 790                 *reg_buf++ = reg;
 791         }
 792
 793         if (rem) {
 794                 reg = mei_txe_out_data_read(dev, i + 1);
 795                 memcpy(reg_buf, &reg, rem);
 796         }
 797
 798         mei_txe_output_ready_set(hw);
 799         return 0;
 800 }
 801
 802 /**
 803  * mei_txe_hw_reset - resets host and fw.
 804  *
 805  * @dev: the device structure
 806  * @intr_enable: if interrupt should be enabled after reset.
 807  *
 808  * Return: 0 on success and < 0 in case of error
 809  */
 810 static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable)
 811 {
 812         struct mei_txe_hw *hw = to_txe_hw(dev);
 813
 814         u32 aliveness_req;
 815         /*
 816          * read input doorbell to ensure consistency between  Bridge and SeC
 817          * return value might be garbage return
 818          */
 819         (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG);
 820
 821         aliveness_req = mei_txe_aliveness_req_get(dev);
 822         hw->aliveness = mei_txe_aliveness_get(dev);
 823
 824         /* Disable interrupts in this stage we will poll */
 825         mei_txe_intr_disable(dev);
 826
 827         /*
 828          * If Aliveness Request and Aliveness Response are not equal then
 829          * wait for them to be equal
 830          * Since we might have interrupts disabled - poll for it
 831          */
 832         if (aliveness_req != hw->aliveness)
 833                 if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) {
 834                         dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n");
 835                         return -EIO;
 836                 }
 837
 838         /*
 839          * If Aliveness Request and Aliveness Response are set then clear them
 840          */
 841         if (aliveness_req) {
 842                 mei_txe_aliveness_set(dev, 0);
 843                 if (mei_txe_aliveness_poll(dev, 0) < 0) {
 844                         dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
 845                         return -EIO;
 846                 }
 847         }
 848
 849         /*
 850          * Set readiness RDY_CLR bit
 851          */
 852         mei_txe_readiness_clear(dev);
 853
 854         return 0;
 855 }
 856
 857 /**
 858  * mei_txe_hw_start - start the hardware after reset
 859  *
 860  * @dev: the device structure
 861  *
 862  * Return: 0 on success and < 0 in case of error
 863  */
 864 static int mei_txe_hw_start(struct mei_device *dev)
 865 {
 866         struct mei_txe_hw *hw = to_txe_hw(dev);
 867         int ret;
 868
 869         u32 hisr;
 870
 871         /* bring back interrupts */
 872         mei_txe_intr_enable(dev);
 873
 874         ret = mei_txe_readiness_wait(dev);
 875         if (ret < 0) {
 876                 dev_err(dev->dev, "waiting for readiness failed\n");
 877                 return ret;
 878         }
 879
 880         /*
 881          * If HISR.INT2_STS interrupt status bit is set then clear it.
 882          */
 883         hisr = mei_txe_br_reg_read(hw, HISR_REG);
 884         if (hisr & HISR_INT_2_STS)
 885                 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS);
 886
 887         /* Clear the interrupt cause of OutputDoorbell */
 888         clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause);
 889
 890         ret = mei_txe_aliveness_set_sync(dev, 1);
 891         if (ret < 0) {
 892                 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
 893                 return ret;
 894         }
 895
 896         /* enable input ready interrupts:
 897          * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK
 898          */
 899         mei_txe_input_ready_interrupt_enable(dev);
 900
 901
 902         /*  Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */
 903         mei_txe_output_ready_set(hw);
 904
 905         /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY
 906          */
 907         mei_txe_readiness_set_host_rdy(dev);
 908
 909         return 0;
 910 }
 911
 912 /**
 913  * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into
 914  *  single bit mask and acknowledge the interrupts
 915  *
 916  * @dev: the device structure
 917  * @do_ack: acknowledge interrupts
 918  */
 919 static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack)
 920 {
 921         struct mei_txe_hw *hw = to_txe_hw(dev);
 922         u32 hisr;
 923         u32 hhisr;
 924         u32 ipc_isr;
 925         u32 aliveness;
 926         bool generated;
 927
 928         /* read interrupt registers */
 929         hhisr = mei_txe_br_reg_read(hw, HHISR_REG);
 930         generated = (hhisr & IPC_HHIER_MSK);
 931         if (!generated)
 932                 goto out;
 933
 934         hisr = mei_txe_br_reg_read(hw, HISR_REG);
 935
 936         aliveness = mei_txe_aliveness_get(dev);
 937         if (hhisr & IPC_HHIER_SEC && aliveness)
 938                 ipc_isr = mei_txe_sec_reg_read_silent(hw,
 939                                 SEC_IPC_HOST_INT_STATUS_REG);
 940         else
 941                 ipc_isr = 0;
 942
 943         generated = generated ||
 944                 (hisr & HISR_INT_STS_MSK) ||
 945                 (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING);
 946
 947         if (generated && do_ack) {
 948                 /* Save the interrupt causes */
 949                 hw->intr_cause |= hisr & HISR_INT_STS_MSK;
 950                 if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY)
 951                         hw->intr_cause |= TXE_INTR_IN_READY;
 952
 953
 954                 mei_txe_intr_disable(dev);
 955                 /* Clear the interrupts in hierarchy:
 956                  * IPC and Bridge, than the High Level */
 957                 mei_txe_sec_reg_write_silent(hw,
 958                         SEC_IPC_HOST_INT_STATUS_REG, ipc_isr);
 959                 mei_txe_br_reg_write(hw, HISR_REG, hisr);
 960                 mei_txe_br_reg_write(hw, HHISR_REG, hhisr);
 961         }
 962
 963 out:
 964         return generated;
 965 }
 966
 967 /**
 968  * mei_txe_irq_quick_handler - The ISR of the MEI device
 969  *
 970  * @irq: The irq number
 971  * @dev_id: pointer to the device structure
 972  *
 973  * Return: IRQ_WAKE_THREAD if interrupt is designed for the device
 974  *         IRQ_NONE otherwise
 975  */
 976 irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id)
 977 {
 978         struct mei_device *dev = dev_id;
 979
 980         if (mei_txe_check_and_ack_intrs(dev, true))
 981                 return IRQ_WAKE_THREAD;
 982         return IRQ_NONE;
 983 }
 984
 985
 986 /**
 987  * mei_txe_irq_thread_handler - txe interrupt thread
 988  *
 989  * @irq: The irq number
 990  * @dev_id: pointer to the device structure
 991  *
 992  * Return: IRQ_HANDLED
 993  *
 994  */
 995 irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id)
 996 {
 997         struct mei_device *dev = (struct mei_device *) dev_id;
 998         struct mei_txe_hw *hw = to_txe_hw(dev);
 999         struct mei_cl_cb complete_list;
1000         s32 slots;
1001         int rets = 0;
1002
1003         dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n",
1004                 mei_txe_br_reg_read(hw, HHISR_REG),
1005                 mei_txe_br_reg_read(hw, HISR_REG),
1006                 mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG));
1007
1008
1009         /* initialize our complete list */
1010         mutex_lock(&dev->device_lock);
1011         mei_io_list_init(&complete_list);
1012
1013         if (pci_dev_msi_enabled(to_pci_dev(dev->dev)))
1014                 mei_txe_check_and_ack_intrs(dev, true);
1015
1016         /* show irq events */
1017         mei_txe_pending_interrupts(dev);
1018
1019         hw->aliveness = mei_txe_aliveness_get(dev);
1020         hw->readiness = mei_txe_readiness_get(dev);
1021
1022         /* Readiness:
1023          * Detection of TXE driver going through reset
1024          * or TXE driver resetting the HECI interface.
1025          */
1026         if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) {
1027                 dev_dbg(dev->dev, "Readiness Interrupt was received...\n");
1028
1029                 /* Check if SeC is going through reset */
1030                 if (mei_txe_readiness_is_sec_rdy(hw->readiness)) {
1031                         dev_dbg(dev->dev, "we need to start the dev.\n");
1032                         dev->recvd_hw_ready = true;
1033                 } else {
1034                         dev->recvd_hw_ready = false;
1035                         if (dev->dev_state != MEI_DEV_RESETTING) {
1036
1037                                 dev_warn(dev->dev, "FW not ready: resetting.\n");
1038                                 schedule_work(&dev->reset_work);
1039                                 goto end;
1040
1041                         }
1042                 }
1043                 wake_up(&dev->wait_hw_ready);
1044         }
1045
1046         /************************************************************/
1047         /* Check interrupt cause:
1048          * Aliveness: Detection of SeC acknowledge of host request that
1049          * it remain alive or host cancellation of that request.
1050          */
1051
1052         if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) {
1053                 /* Clear the interrupt cause */
1054                 dev_dbg(dev->dev,
1055                         "Aliveness Interrupt: Status: %d\n", hw->aliveness);
1056                 dev->pg_event = MEI_PG_EVENT_RECEIVED;
1057                 if (waitqueue_active(&hw->wait_aliveness_resp))
1058                         wake_up(&hw->wait_aliveness_resp);
1059         }
1060
1061
1062         /* Output Doorbell:
1063          * Detection of SeC having sent output to host
1064          */
1065         slots = mei_count_full_read_slots(dev);
1066         if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) {
1067                 /* Read from TXE */
1068                 rets = mei_irq_read_handler(dev, &complete_list, &slots);
1069                 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
1070                         dev_err(dev->dev,
1071                                 "mei_irq_read_handler ret = %d.\n", rets);
1072
1073                         schedule_work(&dev->reset_work);
1074                         goto end;
1075                 }
1076         }
1077         /* Input Ready: Detection if host can write to SeC */
1078         if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) {
1079                 dev->hbuf_is_ready = true;
1080                 hw->slots = dev->hbuf_depth;
1081         }
1082
1083         if (hw->aliveness && dev->hbuf_is_ready) {
1084                 /* get the real register value */
1085                 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1086                 rets = mei_irq_write_handler(dev, &complete_list);
1087                 if (rets && rets != -EMSGSIZE)
1088                         dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n",
1089                                 rets);
1090                 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1091         }
1092
1093         mei_irq_compl_handler(dev, &complete_list);
1094
1095 end:
1096         dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
1097
1098         mutex_unlock(&dev->device_lock);
1099
1100         mei_enable_interrupts(dev);
1101         return IRQ_HANDLED;
1102 }
1103
1104 static const struct mei_hw_ops mei_txe_hw_ops = {
1105
1106         .host_is_ready = mei_txe_host_is_ready,
1107
1108         .fw_status = mei_txe_fw_status,
1109         .pg_state = mei_txe_pg_state,
1110
1111         .hw_is_ready = mei_txe_hw_is_ready,
1112         .hw_reset = mei_txe_hw_reset,
1113         .hw_config = mei_txe_hw_config,
1114         .hw_start = mei_txe_hw_start,
1115
1116         .pg_is_enabled = mei_txe_pg_is_enabled,
1117
1118         .intr_clear = mei_txe_intr_clear,
1119         .intr_enable = mei_txe_intr_enable,
1120         .intr_disable = mei_txe_intr_disable,
1121
1122         .hbuf_free_slots = mei_txe_hbuf_empty_slots,
1123         .hbuf_is_ready = mei_txe_is_input_ready,
1124         .hbuf_max_len = mei_txe_hbuf_max_len,
1125
1126         .write = mei_txe_write,
1127
1128         .rdbuf_full_slots = mei_txe_count_full_read_slots,
1129         .read_hdr = mei_txe_read_hdr,
1130
1131         .read = mei_txe_read,
1132
1133 };
1134
1135 /**
1136  * mei_txe_dev_init - allocates and initializes txe hardware specific structure
1137  *
1138  * @pdev - pci device
1139  *
1140  * Return: struct mei_device * on success or NULL;
1141  *
1142  */
1143 struct mei_device *mei_txe_dev_init(struct pci_dev *pdev)
1144 {
1145         struct mei_device *dev;
1146         struct mei_txe_hw *hw;
1147
1148         dev = kzalloc(sizeof(struct mei_device) +
1149                          sizeof(struct mei_txe_hw), GFP_KERNEL);
1150         if (!dev)
1151                 return NULL;
1152
1153         mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops);
1154
1155         hw = to_txe_hw(dev);
1156
1157         init_waitqueue_head(&hw->wait_aliveness_resp);
1158
1159         return dev;
1160 }
1161
1162 /**
1163  * mei_txe_setup_satt2 - SATT2 configuration for DMA support.
1164  *
1165  * @dev:   the device structure
1166  * @addr:  physical address start of the range
1167  * @range: physical range size
1168  */
1169 int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range)
1170 {
1171         struct mei_txe_hw *hw = to_txe_hw(dev);
1172
1173         u32 lo32 = lower_32_bits(addr);
1174         u32 hi32 = upper_32_bits(addr);
1175         u32 ctrl;
1176
1177         /* SATT is limited to 36 Bits */
1178         if (hi32 & ~0xF)
1179                 return -EINVAL;
1180
1181         /* SATT has to be 16Byte aligned */
1182         if (lo32 & 0xF)
1183                 return -EINVAL;
1184
1185         /* SATT range has to be 4Bytes aligned */
1186         if (range & 0x4)
1187                 return -EINVAL;
1188
1189         /* SATT is limited to 32 MB range*/
1190         if (range > SATT_RANGE_MAX)
1191                 return -EINVAL;
1192
1193         ctrl = SATT2_CTRL_VALID_MSK;
1194         ctrl |= hi32  << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT;
1195
1196         mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range);
1197         mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32);
1198         mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl);
1199         dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n",
1200                 range, lo32, ctrl);
1201
1202         return 0;
1203 }