| blob | 1bc64cda819e0b70530575ed1ec6d5c57e19b075 |
1 /*
2 * Copyright 2014 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
26 #include "skeleton.dtsi"
28 / {
29 model = "ARM RealView PB1176";
30 compatible = "arm,realview-pb1176";
32 chosen { };
34 aliases {
35 serial0 = &pb1176_serial0;
36 serial1 = &pb1176_serial1;
37 serial2 = &pb1176_serial2;
38 serial3 = &pb1176_serial3;
39 serial4 = &fpga_serial;
40 };
42 memory {
43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
45 };
47 /* The voltage to the MMC card is hardwired at 3.3V */
48 vmmc: fixedregulator@0 {
49 compatible = "regulator-fixed";
50 regulator-name = "vmmc";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 regulator-boot-on;
54 };
56 xtal24mhz: xtal24mhz@24M {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
60 };
62 timclk: timclk@1M {
63 #clock-cells = <0>;
64 compatible = "fixed-factor-clock";
65 clock-div = <24>;
66 clock-mult = <1>;
67 clocks = <&xtal24mhz>;
68 };
70 mclk: mclk@24M {
71 #clock-cells = <0>;
72 compatible = "fixed-factor-clock";
73 clock-div = <1>;
74 clock-mult = <1>;
75 clocks = <&xtal24mhz>;
76 };
78 kmiclk: kmiclk@24M {
79 #clock-cells = <0>;
80 compatible = "fixed-factor-clock";
81 clock-div = <1>;
82 clock-mult = <1>;
83 clocks = <&xtal24mhz>;
84 };
86 sspclk: sspclk@24M {
87 #clock-cells = <0>;
88 compatible = "fixed-factor-clock";
89 clock-div = <1>;
90 clock-mult = <1>;
91 clocks = <&xtal24mhz>;
92 };
94 uartclk: uartclk@24M {
95 #clock-cells = <0>;
96 compatible = "fixed-factor-clock";
97 clock-div = <1>;
98 clock-mult = <1>;
99 clocks = <&xtal24mhz>;
100 };
102 /* FIXME: this actually hangs off the PLL clocks */
103 pclk: pclk@0 {
104 #clock-cells = <0>;
105 compatible = "fixed-clock";
106 clock-frequency = <0>;
107 };
109 soc {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "arm,realview-pb1176-soc", "simple-bus";
113 regmap = <&syscon>;
114 ranges;
116 syscon: syscon@10000000 {
117 compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd";
118 reg = <0x10000000 0x1000>;
120 led@08.0 {
121 compatible = "register-bit-led";
122 offset = <0x08>;
123 mask = <0x01>;
124 label = "versatile:0";
125 linux,default-trigger = "heartbeat";
126 default-state = "on";
127 };
128 led@08.1 {
129 compatible = "register-bit-led";
130 offset = <0x08>;
131 mask = <0x02>;
132 label = "versatile:1";
133 linux,default-trigger = "mmc0";
134 default-state = "off";
135 };
136 led@08.2 {
137 compatible = "register-bit-led";
138 offset = <0x08>;
139 mask = <0x04>;
140 label = "versatile:2";
141 linux,default-trigger = "cpu0";
142 default-state = "off";
143 };
144 led@08.3 {
145 compatible = "register-bit-led";
146 offset = <0x08>;
147 mask = <0x08>;
148 label = "versatile:3";
149 default-state = "off";
150 };
151 led@08.4 {
152 compatible = "register-bit-led";
153 offset = <0x08>;
154 mask = <0x10>;
155 label = "versatile:4";
156 default-state = "off";
157 };
158 led@08.5 {
159 compatible = "register-bit-led";
160 offset = <0x08>;
161 mask = <0x20>;
162 label = "versatile:5";
163 default-state = "off";
164 };
165 led@08.6 {
166 compatible = "register-bit-led";
167 offset = <0x08>;
168 mask = <0x40>;
169 label = "versatile:6";
170 default-state = "off";
171 };
172 led@08.7 {
173 compatible = "register-bit-led";
174 offset = <0x08>;
175 mask = <0x80>;
176 label = "versatile:7";
177 default-state = "off";
178 };
179 };
181 /* Primary DevChip GIC synthesized with the CPU */
182 intc_dc1176: interrupt-controller@10120000 {
183 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
184 #interrupt-cells = <3>;
185 #address-cells = <1>;
186 interrupt-controller;
187 reg = <0x10121000 0x1000>,
188 <0x10120000 0x100>;
189 };
191 L2: l2-cache {
192 compatible = "arm,l220-cache";
193 reg = <0x10110000 0x1000>;
194 interrupt-parent = <&intc_dc1176>;
195 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
196 cache-unified;
197 cache-level = <2>;
198 /*
199 * Override default cache size, sets and
200 * associativity as these may be erroneously set
201 * up by boot loader(s).
202 */
203 arm,override-auxreg;
204 cache-size = <131072>; // 128kB
205 cache-sets = <512>;
206 cache-line-size = <32>;
207 };
209 pmu {
210 compatible = "arm,arm1176-pmu";
211 interrupt-parent = <&intc_dc1176>;
212 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
213 };
215 timer01: timer@10104000 {
216 compatible = "arm,sp804", "arm,primecell";
217 reg = <0x10104000 0x1000>;
218 interrupt-parent = <&intc_dc1176>;
219 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&timclk>, <&timclk>, <&pclk>;
221 clock-names = "timer1", "timer2", "apb_pclk";
222 };
224 timer23: timer@10105000 {
225 compatible = "arm,sp804", "arm,primecell";
226 reg = <0x10105000 0x1000>;
227 interrupt-parent = <&intc_dc1176>;
228 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
229 arm,sp804-has-irq = <1>;
230 clocks = <&timclk>, <&timclk>, <&pclk>;
231 clock-names = "timer1", "timer2", "apb_pclk";
232 };
234 pb1176_rtc: rtc@10108000 {
235 compatible = "arm,pl031", "arm,primecell";
236 reg = <0x10108000 0x1000>;
237 interrupt-parent = <&intc_dc1176>;
238 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&pclk>;
240 clock-names = "apb_pclk";
241 };
243 pb1176_gpio0: gpio@1010a000 {
244 compatible = "arm,pl061", "arm,primecell";
245 reg = <0x1010a000 0x1000>;
246 gpio-controller;
247 interrupt-parent = <&intc_dc1176>;
248 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
249 #gpio-cells = <2>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 clocks = <&pclk>;
253 clock-names = "apb_pclk";
254 };
256 pb1176_ssp: ssp@1010b000 {
257 compatible = "arm,pl022", "arm,primecell";
258 reg = <0x1010b000 0x1000>;
259 interrupt-parent = <&intc_dc1176>;
260 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&sspclk>, <&pclk>;
262 clock-names = "SSPCLK", "apb_pclk";
263 };
265 pb1176_serial0: serial@1010c000 {
266 compatible = "arm,pl011", "arm,primecell";
267 reg = <0x1010c000 0x1000>;
268 interrupt-parent = <&intc_dc1176>;
269 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&uartclk>, <&pclk>;
271 clock-names = "uartclk", "apb_pclk";
272 };
274 pb1176_serial1: serial@1010d000 {
275 compatible = "arm,pl011", "arm,primecell";
276 reg = <0x1010d000 0x1000>;
277 interrupt-parent = <&intc_dc1176>;
278 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&uartclk>, <&pclk>;
280 clock-names = "uartclk", "apb_pclk";
281 };
283 pb1176_serial2: serial@1010e000 {
284 compatible = "arm,pl011", "arm,primecell";
285 reg = <0x1010e000 0x1000>;
286 interrupt-parent = <&intc_dc1176>;
287 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&uartclk>, <&pclk>;
289 clock-names = "uartclk", "apb_pclk";
290 };
292 pb1176_serial3: serial@1010f000 {
293 compatible = "arm,pl011", "arm,primecell";
294 reg = <0x1010f000 0x1000>;
295 interrupt-parent = <&intc_dc1176>;
296 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&uartclk>, <&pclk>;
298 clock-names = "uartclk", "apb_pclk";
299 };
300 };
302 /* These peripherals are inside the FPGA rather than the DevChip */
303 fpga {
304 #address-cells = <1>;
305 #size-cells = <1>;
306 compatible = "simple-bus";
307 ranges;
309 fpga_mci: mmcsd@10005000 {
310 compatible = "arm,pl18x", "arm,primecell";
311 reg = <0x10005000 0x1000>;
312 interrupt-parent = <&intc_fpga1176>;
313 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
314 <0 2 IRQ_TYPE_LEVEL_HIGH>;
315 /* Due to frequent FIFO overruns, use just 500 kHz */
316 max-frequency = <500000>;
317 bus-width = <4>;
318 cap-sd-highspeed;
319 cap-mmc-highspeed;
320 clocks = <&mclk>, <&pclk>;
321 clock-names = "mclk", "apb_pclk";
322 vmmc-supply = <&vmmc>;
323 cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
324 wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>;
325 };
327 fpga_kmi0: kmi@10006000 {
328 compatible = "arm,pl050", "arm,primecell";
329 reg = <0x10006000 0x1000>;
330 interrupt-parent = <&intc_fpga1176>;
331 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&kmiclk>, <&pclk>;
333 clock-names = "KMIREFCLK", "apb_pclk";
334 };
336 fpga_kmi1: kmi@10007000 {
337 compatible = "arm,pl050", "arm,primecell";
338 reg = <0x10007000 0x1000>;
339 interrupt-parent = <&intc_fpga1176>;
340 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&kmiclk>, <&pclk>;
342 clock-names = "KMIREFCLK", "apb_pclk";
343 };
345 fpga_charlcd: charlcd@10008000 {
346 compatible = "arm,versatile-lcd";
347 reg = <0x10008000 0x1000>;
348 interrupt-parent = <&intc_fpga1176>;
349 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&pclk>;
351 clock-names = "apb_pclk";
352 };
354 fpga_serial: serial@10009000 {
355 compatible = "arm,pl011", "arm,primecell";
356 reg = <0x10009000 0x1000>;
357 interrupt-parent = <&intc_fpga1176>;
358 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&uartclk>, <&pclk>;
360 clock-names = "uartclk", "apb_pclk";
361 };
363 /* This GIC on the board is cascaded off the DevChip GIC */
364 intc_fpga1176: interrupt-controller@10040000 {
365 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
366 #interrupt-cells = <3>;
367 #address-cells = <1>;
368 interrupt-controller;
369 reg = <0x10041000 0x1000>,
370 <0x10040000 0x100>;
371 interrupt-parent = <&intc_dc1176>;
372 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
373 };
375 fpga_gpio0: gpio@10014000 {
376 compatible = "arm,pl061", "arm,primecell";
377 reg = <0x10014000 0x1000>;
378 gpio-controller;
379 interrupt-parent = <&intc_fpga1176>;
380 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 clocks = <&pclk>;
385 clock-names = "apb_pclk";
386 };
388 fpga_gpio1: gpio@10015000 {
389 compatible = "arm,pl061", "arm,primecell";
390 reg = <0x10015000 0x1000>;
391 gpio-controller;
392 interrupt-parent = <&intc_fpga1176>;
393 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
394 #gpio-cells = <2>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 clocks = <&pclk>;
398 clock-names = "apb_pclk";
399 };
401 fpga_rtc: rtc@10017000 {
402 compatible = "arm,pl031", "arm,primecell";
403 reg = <0x10017000 0x1000>;
404 interrupt-parent = <&intc_fpga1176>;
405 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&pclk>;
407 clock-names = "apb_pclk";
408 };
411 };
412 };