2 * Device Tree file for Marvell Armada 388 Reference Design board
5 * Copyright (C) 2014 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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50 #include "armada-388.dtsi"
53 model = "Marvell Armada 385 Reference Design";
54 compatible = "marvell,a385-rd", "marvell,armada388",
55 "marvell,armada385","marvell,armada380";
58 stdout-path = "serial0:115200n8";
62 device_type = "memory";
63 reg = <0x00000000 0x10000000>; /* 256 MB */
67 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
68 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
69 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
70 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
79 compatible = "st,m25p128", "jedec,spi-nor";
80 reg = <0>; /* Chip select 0 */
81 spi-max-frequency = <108000000>;
87 clock-frequency = <100000>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&sdhci_pins>;
107 phy-mode = "rgmii-id";
113 phy-mode = "rgmii-id";
118 phy0: ethernet-phy@0 {
122 phy1: ethernet-phy@1 {
135 * One PCIe units is accessible through
136 * standard PCIe slot on the board.