arch/arm/boot/dts/armada-xp-db.dts

   1 /*
   2  * Device Tree file for Marvell Armada XP evaluation board
   3  * (DB-78460-BP)
   4  *
   5  * Copyright (C) 2012-2014 Marvell
   6  *
   7  * Lior Amsalem <alior@marvell.com>
   8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is dual-licensed: you can use it either under the terms
  12  * of the GPL or the X11 license, at your option. Note that this dual
  13  * licensing only applies to this file, and not this project as a
  14  * whole.
  15  *
  16  *  a) This file is free software; you can redistribute it and/or
  17  *     modify it under the terms of the GNU General Public License as
  18  *     published by the Free Software Foundation; either version 2 of the
  19  *     License, or (at your option) any later version.
  20  *
  21  *     This file is distributed in the hope that it will be useful
  22  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  *     GNU General Public License for more details.
  25  *
  26  * Or, alternatively
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48   *
  49  * Note: this Device Tree assumes that the bootloader has remapped the
  50  * internal registers to 0xf1000000 (instead of the default
  51  * 0xd0000000). The 0xf1000000 is the default used by the recent,
  52  * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
  53  * boards were delivered with an older version of the bootloader that
  54  * left internal registers mapped at 0xd0000000. If you are in this
  55  * situation, you should either update your bootloader (preferred
  56  * solution) or the below Device Tree should be adjusted.
  57  */
  58
  59 /dts-v1/;
  60 #include "armada-xp-mv78460.dtsi"
  61
  62 / {
  63         model = "Marvell Armada XP Evaluation Board";
  64         compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  65
  66         chosen {
  67                 stdout-path = "serial0:115200n8";
  68         };
  69
  70         memory {
  71                 device_type = "memory";
  72                 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
  73         };
  74
  75         soc {
  76                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
  77                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
  78                           MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
  79                           MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
  80                           MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
  81
  82                 devbus-bootcs {
  83                         status = "okay";
  84
  85                         /* Device Bus parameters are required */
  86
  87                         /* Read parameters */
  88                         devbus,bus-width    = <16>;
  89                         devbus,turn-off-ps  = <60000>;
  90                         devbus,badr-skew-ps = <0>;
  91                         devbus,acc-first-ps = <124000>;
  92                         devbus,acc-next-ps  = <248000>;
  93                         devbus,rd-setup-ps  = <0>;
  94                         devbus,rd-hold-ps   = <0>;
  95
  96                         /* Write parameters */
  97                         devbus,sync-enable = <0>;
  98                         devbus,wr-high-ps  = <60000>;
  99                         devbus,wr-low-ps   = <60000>;
 100                         devbus,ale-wr-ps   = <60000>;
 101
 102                         /* NOR 16 MiB */
 103                         nor@0 {
 104                                 compatible = "cfi-flash";
 105                                 reg = <0 0x1000000>;
 106                                 bank-width = <2>;
 107                         };
 108                 };
 109
 110                 pcie-controller {
 111                         status = "okay";
 112
 113                         /*
 114                          * All 6 slots are physically present as
 115                          * standard PCIe slots on the board.
 116                          */
 117                         pcie@1,0 {
 118                                 /* Port 0, Lane 0 */
 119                                 status = "okay";
 120                         };
 121                         pcie@2,0 {
 122                                 /* Port 0, Lane 1 */
 123                                 status = "okay";
 124                         };
 125                         pcie@3,0 {
 126                                 /* Port 0, Lane 2 */
 127                                 status = "okay";
 128                         };
 129                         pcie@4,0 {
 130                                 /* Port 0, Lane 3 */
 131                                 status = "okay";
 132                         };
 133                         pcie@9,0 {
 134                                 /* Port 2, Lane 0 */
 135                                 status = "okay";
 136                         };
 137                         pcie@10,0 {
 138                                 /* Port 3, Lane 0 */
 139                                 status = "okay";
 140                         };
 141                 };
 142
 143                 internal-regs {
 144                         serial@12000 {
 145                                 status = "okay";
 146                         };
 147                         serial@12100 {
 148                                 status = "okay";
 149                         };
 150                         serial@12200 {
 151                                 status = "okay";
 152                         };
 153                         serial@12300 {
 154                                 status = "okay";
 155                         };
 156
 157                         sata@a0000 {
 158                                 nr-ports = <2>;
 159                                 status = "okay";
 160                         };
 161
 162                         mdio {
 163                                 phy0: ethernet-phy@0 {
 164                                         reg = <0>;
 165                                 };
 166
 167                                 phy1: ethernet-phy@1 {
 168                                         reg = <1>;
 169                                 };
 170
 171                                 phy2: ethernet-phy@2 {
 172                                         reg = <25>;
 173                                 };
 174
 175                                 phy3: ethernet-phy@3 {
 176                                         reg = <27>;
 177                                 };
 178                         };
 179
 180                         ethernet@70000 {
 181                                 status = "okay";
 182                                 phy = <&phy0>;
 183                                 phy-mode = "rgmii-id";
 184                         };
 185                         ethernet@74000 {
 186                                 status = "okay";
 187                                 phy = <&phy1>;
 188                                 phy-mode = "rgmii-id";
 189                         };
 190                         ethernet@30000 {
 191                                 status = "okay";
 192                                 phy = <&phy2>;
 193                                 phy-mode = "sgmii";
 194                         };
 195                         ethernet@34000 {
 196                                 status = "okay";
 197                                 phy = <&phy3>;
 198                                 phy-mode = "sgmii";
 199                         };
 200
 201                         mvsdio@d4000 {
 202                                 pinctrl-0 = <&sdio_pins>;
 203                                 pinctrl-names = "default";
 204                                 status = "okay";
 205                                 /* No CD or WP GPIOs */
 206                                 broken-cd;
 207                         };
 208
 209                         usb@50000 {
 210                                 status = "okay";
 211                         };
 212
 213                         usb@51000 {
 214                                 status = "okay";
 215                         };
 216
 217                         usb@52000 {
 218                                 status = "okay";
 219                         };
 220
 221                         spi0: spi@10600 {
 222                                 status = "okay";
 223
 224                                 spi-flash@0 {
 225                                         #address-cells = <1>;
 226                                         #size-cells = <1>;
 227                                         compatible = "m25p64", "jedec,spi-nor";
 228                                         reg = <0>; /* Chip select 0 */
 229                                         spi-max-frequency = <20000000>;
 230                                 };
 231                         };
 232                 };
 233         };
 234 };