| blob | c5fdc99f0dbebb47f88e135a4013fdfb9d732772 |
1 /*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 *
46 * Contains definitions specific to the Armada XP MV78260 SoC that are not
47 * common to all Armada XP SoCs.
48 */
50 #include "armada-xp.dtsi"
52 / {
53 model = "Marvell Armada XP MV78260 SoC";
54 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
56 aliases {
57 gpio0 = &gpio0;
58 gpio1 = &gpio1;
59 gpio2 = &gpio2;
60 };
62 cpus {
63 #address-cells = <1>;
64 #size-cells = <0>;
65 enable-method = "marvell,armada-xp-smp";
67 cpu@0 {
68 device_type = "cpu";
69 compatible = "marvell,sheeva-v7";
70 reg = <0>;
71 clocks = <&cpuclk 0>;
72 clock-latency = <1000000>;
73 };
75 cpu@1 {
76 device_type = "cpu";
77 compatible = "marvell,sheeva-v7";
78 reg = <1>;
79 clocks = <&cpuclk 1>;
80 clock-latency = <1000000>;
81 };
82 };
84 soc {
85 /*
86 * MV78260 has 3 PCIe units Gen2.0: Two units can be
87 * configured as x4 or quad x1 lanes. One unit is
88 * x4 only.
89 */
90 pcie-controller {
91 compatible = "marvell,armada-xp-pcie";
92 status = "disabled";
93 device_type = "pci";
95 #address-cells = <3>;
96 #size-cells = <2>;
98 msi-parent = <&mpic>;
99 bus-range = <0x00 0xff>;
101 ranges =
102 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
103 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
104 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
105 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
106 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
107 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
108 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
109 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
110 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
111 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
112 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
113 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
114 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
115 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
116 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
117 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
118 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
120 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
121 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
122 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
123 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
124 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
125 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
126 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
127 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
129 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
130 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
132 pcie@1,0 {
133 device_type = "pci";
134 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
135 reg = <0x0800 0 0 0 0>;
136 #address-cells = <3>;
137 #size-cells = <2>;
138 #interrupt-cells = <1>;
139 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
140 0x81000000 0 0 0x81000000 0x1 0 1 0>;
141 interrupt-map-mask = <0 0 0 0>;
142 interrupt-map = <0 0 0 0 &mpic 58>;
143 marvell,pcie-port = <0>;
144 marvell,pcie-lane = <0>;
145 clocks = <&gateclk 5>;
146 status = "disabled";
147 };
149 pcie@2,0 {
150 device_type = "pci";
151 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
152 reg = <0x1000 0 0 0 0>;
153 #address-cells = <3>;
154 #size-cells = <2>;
155 #interrupt-cells = <1>;
156 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
157 0x81000000 0 0 0x81000000 0x2 0 1 0>;
158 interrupt-map-mask = <0 0 0 0>;
159 interrupt-map = <0 0 0 0 &mpic 59>;
160 marvell,pcie-port = <0>;
161 marvell,pcie-lane = <1>;
162 clocks = <&gateclk 6>;
163 status = "disabled";
164 };
166 pcie@3,0 {
167 device_type = "pci";
168 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
169 reg = <0x1800 0 0 0 0>;
170 #address-cells = <3>;
171 #size-cells = <2>;
172 #interrupt-cells = <1>;
173 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
174 0x81000000 0 0 0x81000000 0x3 0 1 0>;
175 interrupt-map-mask = <0 0 0 0>;
176 interrupt-map = <0 0 0 0 &mpic 60>;
177 marvell,pcie-port = <0>;
178 marvell,pcie-lane = <2>;
179 clocks = <&gateclk 7>;
180 status = "disabled";
181 };
183 pcie@4,0 {
184 device_type = "pci";
185 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
186 reg = <0x2000 0 0 0 0>;
187 #address-cells = <3>;
188 #size-cells = <2>;
189 #interrupt-cells = <1>;
190 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
191 0x81000000 0 0 0x81000000 0x4 0 1 0>;
192 interrupt-map-mask = <0 0 0 0>;
193 interrupt-map = <0 0 0 0 &mpic 61>;
194 marvell,pcie-port = <0>;
195 marvell,pcie-lane = <3>;
196 clocks = <&gateclk 8>;
197 status = "disabled";
198 };
200 pcie@5,0 {
201 device_type = "pci";
202 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
203 reg = <0x2800 0 0 0 0>;
204 #address-cells = <3>;
205 #size-cells = <2>;
206 #interrupt-cells = <1>;
207 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
208 0x81000000 0 0 0x81000000 0x5 0 1 0>;
209 interrupt-map-mask = <0 0 0 0>;
210 interrupt-map = <0 0 0 0 &mpic 62>;
211 marvell,pcie-port = <1>;
212 marvell,pcie-lane = <0>;
213 clocks = <&gateclk 9>;
214 status = "disabled";
215 };
217 pcie@6,0 {
218 device_type = "pci";
219 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
220 reg = <0x3000 0 0 0 0>;
221 #address-cells = <3>;
222 #size-cells = <2>;
223 #interrupt-cells = <1>;
224 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
225 0x81000000 0 0 0x81000000 0x6 0 1 0>;
226 interrupt-map-mask = <0 0 0 0>;
227 interrupt-map = <0 0 0 0 &mpic 63>;
228 marvell,pcie-port = <1>;
229 marvell,pcie-lane = <1>;
230 clocks = <&gateclk 10>;
231 status = "disabled";
232 };
234 pcie@7,0 {
235 device_type = "pci";
236 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
237 reg = <0x3800 0 0 0 0>;
238 #address-cells = <3>;
239 #size-cells = <2>;
240 #interrupt-cells = <1>;
241 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
242 0x81000000 0 0 0x81000000 0x7 0 1 0>;
243 interrupt-map-mask = <0 0 0 0>;
244 interrupt-map = <0 0 0 0 &mpic 64>;
245 marvell,pcie-port = <1>;
246 marvell,pcie-lane = <2>;
247 clocks = <&gateclk 11>;
248 status = "disabled";
249 };
251 pcie@8,0 {
252 device_type = "pci";
253 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
254 reg = <0x4000 0 0 0 0>;
255 #address-cells = <3>;
256 #size-cells = <2>;
257 #interrupt-cells = <1>;
258 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
259 0x81000000 0 0 0x81000000 0x8 0 1 0>;
260 interrupt-map-mask = <0 0 0 0>;
261 interrupt-map = <0 0 0 0 &mpic 65>;
262 marvell,pcie-port = <1>;
263 marvell,pcie-lane = <3>;
264 clocks = <&gateclk 12>;
265 status = "disabled";
266 };
268 pcie@9,0 {
269 device_type = "pci";
270 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
271 reg = <0x4800 0 0 0 0>;
272 #address-cells = <3>;
273 #size-cells = <2>;
274 #interrupt-cells = <1>;
275 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
276 0x81000000 0 0 0x81000000 0x9 0 1 0>;
277 interrupt-map-mask = <0 0 0 0>;
278 interrupt-map = <0 0 0 0 &mpic 99>;
279 marvell,pcie-port = <2>;
280 marvell,pcie-lane = <0>;
281 clocks = <&gateclk 26>;
282 status = "disabled";
283 };
284 };
286 internal-regs {
287 gpio0: gpio@18100 {
288 compatible = "marvell,orion-gpio";
289 reg = <0x18100 0x40>;
290 ngpios = <32>;
291 gpio-controller;
292 #gpio-cells = <2>;
293 interrupt-controller;
294 #interrupt-cells = <2>;
295 interrupts = <82>, <83>, <84>, <85>;
296 };
298 gpio1: gpio@18140 {
299 compatible = "marvell,orion-gpio";
300 reg = <0x18140 0x40>;
301 ngpios = <32>;
302 gpio-controller;
303 #gpio-cells = <2>;
304 interrupt-controller;
305 #interrupt-cells = <2>;
306 interrupts = <87>, <88>, <89>, <90>;
307 };
309 gpio2: gpio@18180 {
310 compatible = "marvell,orion-gpio";
311 reg = <0x18180 0x40>;
312 ngpios = <3>;
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 interrupts = <91>;
318 };
320 eth3: ethernet@34000 {
321 compatible = "marvell,armada-xp-neta";
322 reg = <0x34000 0x4000>;
323 interrupts = <14>;
324 clocks = <&gateclk 1>;
325 status = "disabled";
326 };
327 };
328 };
329 };
331 &pinctrl {
332 compatible = "marvell,mv78260-pinctrl";
333 };