arch/arm/boot/dts/bcm63138.dtsi

   1 /*
   2  * Broadcom BCM63138 DSL SoCs Device Tree
   3  */
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/interrupt-controller/irq.h>
   7
   8 #include "skeleton.dtsi"
   9
  10 / {
  11         compatible = "brcm,bcm63138";
  12         model = "Broadcom BCM63138 DSL SoC";
  13         interrupt-parent = <&gic>;
  14
  15         aliases {
  16                 uart0 = &serial0;
  17                 uart1 = &serial1;
  18         };
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a9";
  27                         next-level-cache = <&L2>;
  28                         reg = <0>;
  29                         enable-method = "brcm,bcm63138";
  30                 };
  31
  32                 cpu@1 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a9";
  35                         next-level-cache = <&L2>;
  36                         reg = <1>;
  37                         enable-method = "brcm,bcm63138";
  38                         resets = <&pmb0 4 1>;
  39                 };
  40         };
  41
  42         clocks {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 arm_timer_clk: arm_timer_clk {
  47                         #clock-cells = <0>;
  48                         compatible = "fixed-clock";
  49                         clock-frequency = <500000000>;
  50                 };
  51
  52                 periph_clk: periph_clk {
  53                         #clock-cells = <0>;
  54                         compatible = "fixed-clock";
  55                         clock-frequency = <50000000>;
  56                         clock-output-names = "periph";
  57                 };
  58         };
  59
  60         /* ARM bus */
  61         axi@80000000 {
  62                 compatible = "simple-bus";
  63                 ranges = <0 0x80000000 0x784000>;
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66
  67                 L2: cache-controller@1d000 {
  68                         compatible = "arm,pl310-cache";
  69                         reg = <0x1d000 0x1000>;
  70                         cache-unified;
  71                         cache-level = <2>;
  72                         cache-size = <524288>;
  73                         cache-sets = <1024>;
  74                         cache-line-size = <32>;
  75                         interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
  76                 };
  77
  78                 scu: scu@1e000 {
  79                         compatible = "arm,cortex-a9-scu";
  80                         reg = <0x1e000 0x100>;
  81                 };
  82
  83                 gic: interrupt-controller@1e100 {
  84                         compatible = "arm,cortex-a9-gic";
  85                         reg = <0x1f000 0x1000
  86                                 0x1e100 0x100>;
  87                         #interrupt-cells = <3>;
  88                         #address-cells = <0>;
  89                         interrupt-controller;
  90                 };
  91
  92                 global_timer: timer@1e200 {
  93                         compatible = "arm,cortex-a9-global-timer";
  94                         reg = <0x1e200 0x20>;
  95                         interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  96                         clocks = <&arm_timer_clk>;
  97                 };
  98
  99                 local_timer: local-timer@1e600 {
 100                         compatible = "arm,cortex-a9-twd-timer";
 101                         reg = <0x1e600 0x20>;
 102                         interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
 103                         clocks = <&arm_timer_clk>;
 104                 };
 105
 106                 twd_watchdog: watchdog@1e620 {
 107                         compatible = "arm,cortex-a9-twd-wdt";
 108                         reg = <0x1e620 0x20>;
 109                         interrupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
 110                 };
 111
 112                 pmb0: reset-controller@4800c0 {
 113                         compatible = "brcm,bcm63138-pmb";
 114                         reg = <0x4800c0 0x10>;
 115                         #reset-cells = <2>;
 116                 };
 117
 118                 pmb1: reset-controller@4800e0 {
 119                         compatible = "brcm,bcm63138-pmb";
 120                         reg = <0x4800e0 0x10>;
 121                         #reset-cells = <2>;
 122                 };
 123         };
 124
 125         /* Legacy UBUS base */
 126         ubus@fffe8000 {
 127                 compatible = "simple-bus";
 128                 #address-cells = <1>;
 129                 #size-cells = <1>;
 130                 ranges = <0 0xfffe8000 0x8100>;
 131
 132                 timer: timer@80 {
 133                         compatible = "brcm,bcm6328-timer", "syscon";
 134                         reg = <0x80 0x3c>;
 135                 };
 136
 137                 serial0: serial@600 {
 138                         compatible = "brcm,bcm6345-uart";
 139                         reg = <0x600 0x1b>;
 140                         interrupts = <GIC_SPI 32 0>;
 141                         clocks = <&periph_clk>;
 142                         clock-names = "periph";
 143                         status = "disabled";
 144                 };
 145
 146                 serial1: serial@620 {
 147                         compatible = "brcm,bcm6345-uart";
 148                         reg = <0x620 0x1b>;
 149                         interrupts = <GIC_SPI 33 0>;
 150                         clocks = <&periph_clk>;
 151                         clock-names = "periph";
 152                         status = "disabled";
 153                 };
 154
 155                 nand: nand@2000 {
 156                         #address-cells = <1>;
 157                         #size-cells = <0>;
 158                         compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
 159                         reg = <0x2000 0x600>, <0xf0 0x10>;
 160                         reg-names = "nand", "nand-int-base";
 161                         status = "disabled";
 162                         interrupts = <GIC_SPI 38 0>;
 163                         interrupt-names = "nand";
 164                 };
 165
 166                 bootlut: bootlut@8000 {
 167                         compatible = "brcm,bcm63138-bootlut";
 168                         reg = <0x8000 0x50>;
 169                 };
 170
 171                 reboot {
 172                         compatible = "syscon-reboot";
 173                         regmap = <&timer>;
 174                         offset = <0x34>;
 175                         mask = <1>;
 176                 };
 177         };
 178 };