| blob | 864f60020124e44181a66706797c0c16c6970044 |
1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
10 #include "dra74x.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/clk/ti-dra7-atl.h>
13 #include <dt-bindings/input/input.h>
15 / {
16 model = "TI DRA742";
17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
19 memory {
20 device_type = "memory";
21 reg = <0x80000000 0x60000000>; /* 1536 MB */
22 };
24 evm_3v3_sd: fixedregulator-sd {
25 compatible = "regulator-fixed";
26 regulator-name = "evm_3v3_sd";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 enable-active-high;
30 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
31 };
33 evm_3v3_sw: fixedregulator-evm_3v3_sw {
34 compatible = "regulator-fixed";
35 regulator-name = "evm_3v3_sw";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 };
40 aic_dvdd: fixedregulator-aic_dvdd {
41 /* TPS77018DBVT */
42 compatible = "regulator-fixed";
43 regulator-name = "aic_dvdd";
44 vin-supply = <&evm_3v3_sw>;
45 regulator-min-microvolt = <1800000>;
46 regulator-max-microvolt = <1800000>;
47 };
49 extcon_usb1: extcon_usb1 {
50 compatible = "linux,extcon-usb-gpio";
51 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
52 };
54 extcon_usb2: extcon_usb2 {
55 compatible = "linux,extcon-usb-gpio";
56 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
57 };
59 vtt_fixed: fixedregulator-vtt {
60 compatible = "regulator-fixed";
61 regulator-name = "vtt_fixed";
62 regulator-min-microvolt = <1350000>;
63 regulator-max-microvolt = <1350000>;
64 regulator-always-on;
65 regulator-boot-on;
66 enable-active-high;
67 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
68 };
70 sound0: sound@0 {
71 compatible = "simple-audio-card";
72 simple-audio-card,name = "DRA7xx-EVM";
73 simple-audio-card,widgets =
74 "Headphone", "Headphone Jack",
75 "Line", "Line Out",
76 "Microphone", "Mic Jack",
77 "Line", "Line In";
78 simple-audio-card,routing =
79 "Headphone Jack", "HPLOUT",
80 "Headphone Jack", "HPROUT",
81 "Line Out", "LLOUT",
82 "Line Out", "RLOUT",
83 "MIC3L", "Mic Jack",
84 "MIC3R", "Mic Jack",
85 "Mic Jack", "Mic Bias",
86 "LINE1L", "Line In",
87 "LINE1R", "Line In";
88 simple-audio-card,format = "dsp_b";
89 simple-audio-card,bitclock-master = <&sound0_master>;
90 simple-audio-card,frame-master = <&sound0_master>;
91 simple-audio-card,bitclock-inversion;
93 sound0_master: simple-audio-card,cpu {
94 sound-dai = <&mcasp3>;
95 system-clock-frequency = <5644800>;
96 };
98 simple-audio-card,codec {
99 sound-dai = <&tlv320aic3106>;
100 clocks = <&atl_clkin2_ck>;
101 };
102 };
104 leds {
105 compatible = "gpio-leds";
106 led@0 {
107 label = "dra7:usr1";
108 gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
109 default-state = "off";
110 };
112 led@1 {
113 label = "dra7:usr2";
114 gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
115 default-state = "off";
116 };
118 led@2 {
119 label = "dra7:usr3";
120 gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
121 default-state = "off";
122 };
124 led@3 {
125 label = "dra7:usr4";
126 gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
127 default-state = "off";
128 };
129 };
131 gpio_keys {
132 compatible = "gpio-keys";
133 #address-cells = <1>;
134 #size-cells = <0>;
135 autorepeat;
137 USER1 {
138 label = "btnUser1";
139 linux,code = <BTN_0>;
140 gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
141 };
143 USER2 {
144 label = "btnUser2";
145 linux,code = <BTN_1>;
146 gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
147 };
148 };
149 };
151 &dra7_pmx_core {
152 pinctrl-names = "default";
153 pinctrl-0 = <&vtt_pin>;
155 vtt_pin: pinmux_vtt_pin {
156 pinctrl-single,pins = <
157 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
158 >;
159 };
161 i2c1_pins: pinmux_i2c1_pins {
162 pinctrl-single,pins = <
163 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
164 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
165 >;
166 };
168 i2c2_pins: pinmux_i2c2_pins {
169 pinctrl-single,pins = <
170 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
171 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
172 >;
173 };
175 i2c3_pins: pinmux_i2c3_pins {
176 pinctrl-single,pins = <
177 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
178 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
179 >;
180 };
182 mcspi1_pins: pinmux_mcspi1_pins {
183 pinctrl-single,pins = <
184 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
185 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
186 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
187 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
188 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
189 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
190 >;
191 };
193 mcspi2_pins: pinmux_mcspi2_pins {
194 pinctrl-single,pins = <
195 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
196 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
197 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
198 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
199 >;
200 };
202 uart1_pins: pinmux_uart1_pins {
203 pinctrl-single,pins = <
204 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
205 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
206 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
207 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
208 >;
209 };
211 uart2_pins: pinmux_uart2_pins {
212 pinctrl-single,pins = <
213 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
214 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
215 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
216 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
217 >;
218 };
220 uart3_pins: pinmux_uart3_pins {
221 pinctrl-single,pins = <
222 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
223 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
224 >;
225 };
227 qspi1_pins: pinmux_qspi1_pins {
228 pinctrl-single,pins = <
229 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
230 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
231 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
232 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
233 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
234 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
235 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
236 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
237 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
238 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
239 >;
240 };
242 usb1_pins: pinmux_usb1_pins {
243 pinctrl-single,pins = <
244 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
245 >;
246 };
248 usb2_pins: pinmux_usb2_pins {
249 pinctrl-single,pins = <
250 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
251 >;
252 };
254 nand_flash_x16: nand_flash_x16 {
255 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
256 * So NAND flash requires following switch settings:
257 * SW5.9 (GPMC_WPN) = LOW
258 * SW5.1 (NAND_BOOTn) = HIGH */
259 pinctrl-single,pins = <
260 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
261 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
262 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
263 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
264 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
265 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
266 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
267 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
268 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
269 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
270 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
271 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
272 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
273 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
274 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
275 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
276 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
277 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
278 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
279 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
280 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
281 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
282 >;
283 };
285 cpsw_default: cpsw_default {
286 pinctrl-single,pins = <
287 /* Slave 1 */
288 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
289 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
290 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
291 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
292 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
293 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
294 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
295 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
296 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
297 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
298 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
299 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
301 /* Slave 2 */
302 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
303 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
304 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
305 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
306 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
307 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
308 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
309 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
310 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
311 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
312 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
313 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
314 >;
316 };
318 cpsw_sleep: cpsw_sleep {
319 pinctrl-single,pins = <
320 /* Slave 1 */
321 0x250 (MUX_MODE15)
322 0x254 (MUX_MODE15)
323 0x258 (MUX_MODE15)
324 0x25c (MUX_MODE15)
325 0x260 (MUX_MODE15)
326 0x264 (MUX_MODE15)
327 0x268 (MUX_MODE15)
328 0x26c (MUX_MODE15)
329 0x270 (MUX_MODE15)
330 0x274 (MUX_MODE15)
331 0x278 (MUX_MODE15)
332 0x27c (MUX_MODE15)
334 /* Slave 2 */
335 0x198 (MUX_MODE15)
336 0x19c (MUX_MODE15)
337 0x1a0 (MUX_MODE15)
338 0x1a4 (MUX_MODE15)
339 0x1a8 (MUX_MODE15)
340 0x1ac (MUX_MODE15)
341 0x1b0 (MUX_MODE15)
342 0x1b4 (MUX_MODE15)
343 0x1b8 (MUX_MODE15)
344 0x1bc (MUX_MODE15)
345 0x1c0 (MUX_MODE15)
346 0x1c4 (MUX_MODE15)
347 >;
348 };
350 davinci_mdio_default: davinci_mdio_default {
351 pinctrl-single,pins = <
352 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
353 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
354 >;
355 };
357 davinci_mdio_sleep: davinci_mdio_sleep {
358 pinctrl-single,pins = <
359 0x23c (MUX_MODE15)
360 0x240 (MUX_MODE15)
361 >;
362 };
364 dcan1_pins_default: dcan1_pins_default {
365 pinctrl-single,pins = <
366 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
367 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
368 >;
369 };
371 dcan1_pins_sleep: dcan1_pins_sleep {
372 pinctrl-single,pins = <
373 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
374 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
375 >;
376 };
378 atl_pins: pinmux_atl_pins {
379 pinctrl-single,pins = <
380 0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
381 0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
382 >;
383 };
385 mcasp3_pins: pinmux_mcasp3_pins {
386 pinctrl-single,pins = <
387 0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
388 0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
389 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
390 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
391 >;
392 };
394 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
395 pinctrl-single,pins = <
396 0x324 (MUX_MODE15)
397 0x328 (MUX_MODE15)
398 0x32c (MUX_MODE15)
399 0x330 (MUX_MODE15)
400 >;
401 };
402 };
404 &i2c1 {
405 status = "okay";
406 pinctrl-names = "default";
407 pinctrl-0 = <&i2c1_pins>;
408 clock-frequency = <400000>;
410 tps659038: tps659038@58 {
411 compatible = "ti,tps659038";
412 reg = <0x58>;
414 tps659038_pmic {
415 compatible = "ti,tps659038-pmic";
417 regulators {
418 smps123_reg: smps123 {
419 /* VDD_MPU */
420 regulator-name = "smps123";
421 regulator-min-microvolt = < 850000>;
422 regulator-max-microvolt = <1250000>;
423 regulator-always-on;
424 regulator-boot-on;
425 };
427 smps45_reg: smps45 {
428 /* VDD_DSPEVE */
429 regulator-name = "smps45";
430 regulator-min-microvolt = < 850000>;
431 regulator-max-microvolt = <1150000>;
432 regulator-always-on;
433 regulator-boot-on;
434 };
436 smps6_reg: smps6 {
437 /* VDD_GPU - over VDD_SMPS6 */
438 regulator-name = "smps6";
439 regulator-min-microvolt = <850000>;
440 regulator-max-microvolt = <1250000>;
441 regulator-always-on;
442 regulator-boot-on;
443 };
445 smps7_reg: smps7 {
446 /* CORE_VDD */
447 regulator-name = "smps7";
448 regulator-min-microvolt = <850000>;
449 regulator-max-microvolt = <1060000>;
450 regulator-always-on;
451 regulator-boot-on;
452 };
454 smps8_reg: smps8 {
455 /* VDD_IVAHD */
456 regulator-name = "smps8";
457 regulator-min-microvolt = < 850000>;
458 regulator-max-microvolt = <1250000>;
459 regulator-always-on;
460 regulator-boot-on;
461 };
463 smps9_reg: smps9 {
464 /* VDDS1V8 */
465 regulator-name = "smps9";
466 regulator-min-microvolt = <1800000>;
467 regulator-max-microvolt = <1800000>;
468 regulator-always-on;
469 regulator-boot-on;
470 };
472 ldo1_reg: ldo1 {
473 /* LDO1_OUT --> SDIO */
474 regulator-name = "ldo1";
475 regulator-min-microvolt = <1800000>;
476 regulator-max-microvolt = <3300000>;
477 regulator-always-on;
478 regulator-boot-on;
479 };
481 ldo2_reg: ldo2 {
482 /* VDD_RTCIO */
483 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
484 regulator-name = "ldo2";
485 regulator-min-microvolt = <3300000>;
486 regulator-max-microvolt = <3300000>;
487 regulator-always-on;
488 regulator-boot-on;
489 };
491 ldo3_reg: ldo3 {
492 /* VDDA_1V8_PHY */
493 regulator-name = "ldo3";
494 regulator-min-microvolt = <1800000>;
495 regulator-max-microvolt = <1800000>;
496 regulator-always-on;
497 regulator-boot-on;
498 };
500 ldo9_reg: ldo9 {
501 /* VDD_RTC */
502 regulator-name = "ldo9";
503 regulator-min-microvolt = <1050000>;
504 regulator-max-microvolt = <1050000>;
505 regulator-always-on;
506 regulator-boot-on;
507 };
509 ldoln_reg: ldoln {
510 /* VDDA_1V8_PLL */
511 regulator-name = "ldoln";
512 regulator-min-microvolt = <1800000>;
513 regulator-max-microvolt = <1800000>;
514 regulator-always-on;
515 regulator-boot-on;
516 };
518 ldousb_reg: ldousb {
519 /* VDDA_3V_USB: VDDA_USBHS33 */
520 regulator-name = "ldousb";
521 regulator-min-microvolt = <3300000>;
522 regulator-max-microvolt = <3300000>;
523 regulator-boot-on;
524 };
525 };
526 };
527 };
529 pcf_lcd: gpio@20 {
530 compatible = "nxp,pcf8575";
531 reg = <0x20>;
532 gpio-controller;
533 #gpio-cells = <2>;
534 interrupt-parent = <&gpio6>;
535 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
536 interrupt-controller;
537 #interrupt-cells = <2>;
538 };
540 pcf_gpio_21: gpio@21 {
541 compatible = "ti,pcf8575";
542 reg = <0x21>;
543 lines-initial-states = <0x1408>;
544 gpio-controller;
545 #gpio-cells = <2>;
546 interrupt-parent = <&gpio6>;
547 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
548 interrupt-controller;
549 #interrupt-cells = <2>;
550 };
552 tlv320aic3106: tlv320aic3106@19 {
553 #sound-dai-cells = <0>;
554 compatible = "ti,tlv320aic3106";
555 reg = <0x19>;
556 adc-settle-ms = <40>;
557 ai3x-micbias-vg = <1>; /* 2.0V */
558 status = "okay";
560 /* Regulators */
561 AVDD-supply = <&evm_3v3_sw>;
562 IOVDD-supply = <&evm_3v3_sw>;
563 DRVDD-supply = <&evm_3v3_sw>;
564 DVDD-supply = <&aic_dvdd>;
565 };
566 };
568 &i2c2 {
569 status = "okay";
570 pinctrl-names = "default";
571 pinctrl-0 = <&i2c2_pins>;
572 clock-frequency = <400000>;
574 pcf_hdmi: gpio@26 {
575 compatible = "nxp,pcf8575";
576 reg = <0x26>;
577 gpio-controller;
578 #gpio-cells = <2>;
579 p1 {
580 /* vin6_sel_s0: high: VIN6, low: audio */
581 gpio-hog;
582 gpios = <1 GPIO_ACTIVE_HIGH>;
583 output-low;
584 line-name = "vin6_sel_s0";
585 };
586 };
587 };
589 &i2c3 {
590 status = "okay";
591 pinctrl-names = "default";
592 pinctrl-0 = <&i2c3_pins>;
593 clock-frequency = <400000>;
594 };
596 &mcspi1 {
597 status = "okay";
598 pinctrl-names = "default";
599 pinctrl-0 = <&mcspi1_pins>;
600 };
602 &mcspi2 {
603 status = "okay";
604 pinctrl-names = "default";
605 pinctrl-0 = <&mcspi2_pins>;
606 };
608 &uart1 {
609 status = "okay";
610 pinctrl-names = "default";
611 pinctrl-0 = <&uart1_pins>;
612 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
613 <&dra7_pmx_core 0x3e0>;
614 };
616 &uart2 {
617 status = "okay";
618 pinctrl-names = "default";
619 pinctrl-0 = <&uart2_pins>;
620 };
622 &uart3 {
623 status = "okay";
624 pinctrl-names = "default";
625 pinctrl-0 = <&uart3_pins>;
626 };
628 &mmc1 {
629 status = "okay";
630 vmmc-supply = <&evm_3v3_sd>;
631 vmmc_aux-supply = <&ldo1_reg>;
632 bus-width = <4>;
633 /*
634 * SDCD signal is not being used here - using the fact that GPIO mode
635 * is always hardwired.
636 */
637 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
638 };
640 &mmc2 {
641 status = "okay";
642 vmmc-supply = <&evm_3v3_sw>;
643 bus-width = <8>;
644 };
646 &cpu0 {
647 cpu0-supply = <&smps123_reg>;
648 };
650 &qspi {
651 status = "okay";
652 pinctrl-names = "default";
653 pinctrl-0 = <&qspi1_pins>;
655 spi-max-frequency = <48000000>;
656 m25p80@0 {
657 compatible = "s25fl256s1";
658 spi-max-frequency = <48000000>;
659 reg = <0>;
660 spi-tx-bus-width = <1>;
661 spi-rx-bus-width = <4>;
662 spi-cpol;
663 spi-cpha;
664 #address-cells = <1>;
665 #size-cells = <1>;
667 /* MTD partition table.
668 * The ROM checks the first four physical blocks
669 * for a valid file to boot and the flash here is
670 * 64KiB block size.
671 */
672 partition@0 {
673 label = "QSPI.SPL";
674 reg = <0x00000000 0x000010000>;
675 };
676 partition@1 {
677 label = "QSPI.SPL.backup1";
678 reg = <0x00010000 0x00010000>;
679 };
680 partition@2 {
681 label = "QSPI.SPL.backup2";
682 reg = <0x00020000 0x00010000>;
683 };
684 partition@3 {
685 label = "QSPI.SPL.backup3";
686 reg = <0x00030000 0x00010000>;
687 };
688 partition@4 {
689 label = "QSPI.u-boot";
690 reg = <0x00040000 0x00100000>;
691 };
692 partition@5 {
693 label = "QSPI.u-boot-spl-os";
694 reg = <0x00140000 0x00080000>;
695 };
696 partition@6 {
697 label = "QSPI.u-boot-env";
698 reg = <0x001c0000 0x00010000>;
699 };
700 partition@7 {
701 label = "QSPI.u-boot-env.backup1";
702 reg = <0x001d0000 0x0010000>;
703 };
704 partition@8 {
705 label = "QSPI.kernel";
706 reg = <0x001e0000 0x0800000>;
707 };
708 partition@9 {
709 label = "QSPI.file-system";
710 reg = <0x009e0000 0x01620000>;
711 };
712 };
713 };
715 &omap_dwc3_1 {
716 extcon = <&extcon_usb1>;
717 };
719 &omap_dwc3_2 {
720 extcon = <&extcon_usb2>;
721 };
723 &usb1 {
724 dr_mode = "peripheral";
725 pinctrl-names = "default";
726 pinctrl-0 = <&usb1_pins>;
727 };
729 &usb2 {
730 dr_mode = "host";
731 pinctrl-names = "default";
732 pinctrl-0 = <&usb2_pins>;
733 };
735 &elm {
736 status = "okay";
737 };
739 &gpmc {
740 status = "okay";
741 pinctrl-names = "default";
742 pinctrl-0 = <&nand_flash_x16>;
743 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
744 nand@0,0 {
745 reg = <0 0 4>; /* device IO registers */
746 ti,nand-ecc-opt = "bch8";
747 ti,elm-id = <&elm>;
748 nand-bus-width = <16>;
749 gpmc,device-width = <2>;
750 gpmc,sync-clk-ps = <0>;
751 gpmc,cs-on-ns = <0>;
752 gpmc,cs-rd-off-ns = <80>;
753 gpmc,cs-wr-off-ns = <80>;
754 gpmc,adv-on-ns = <0>;
755 gpmc,adv-rd-off-ns = <60>;
756 gpmc,adv-wr-off-ns = <60>;
757 gpmc,we-on-ns = <10>;
758 gpmc,we-off-ns = <50>;
759 gpmc,oe-on-ns = <4>;
760 gpmc,oe-off-ns = <40>;
761 gpmc,access-ns = <40>;
762 gpmc,wr-access-ns = <80>;
763 gpmc,rd-cycle-ns = <80>;
764 gpmc,wr-cycle-ns = <80>;
765 gpmc,bus-turnaround-ns = <0>;
766 gpmc,cycle2cycle-delay-ns = <0>;
767 gpmc,clk-activation-ns = <0>;
768 gpmc,wait-monitoring-ns = <0>;
769 gpmc,wr-data-mux-bus-ns = <0>;
770 /* MTD partition table */
771 /* All SPL-* partitions are sized to minimal length
772 * which can be independently programmable. For
773 * NAND flash this is equal to size of erase-block */
774 #address-cells = <1>;
775 #size-cells = <1>;
776 partition@0 {
777 label = "NAND.SPL";
778 reg = <0x00000000 0x000020000>;
779 };
780 partition@1 {
781 label = "NAND.SPL.backup1";
782 reg = <0x00020000 0x00020000>;
783 };
784 partition@2 {
785 label = "NAND.SPL.backup2";
786 reg = <0x00040000 0x00020000>;
787 };
788 partition@3 {
789 label = "NAND.SPL.backup3";
790 reg = <0x00060000 0x00020000>;
791 };
792 partition@4 {
793 label = "NAND.u-boot-spl-os";
794 reg = <0x00080000 0x00040000>;
795 };
796 partition@5 {
797 label = "NAND.u-boot";
798 reg = <0x000c0000 0x00100000>;
799 };
800 partition@6 {
801 label = "NAND.u-boot-env";
802 reg = <0x001c0000 0x00020000>;
803 };
804 partition@7 {
805 label = "NAND.u-boot-env.backup1";
806 reg = <0x001e0000 0x00020000>;
807 };
808 partition@8 {
809 label = "NAND.kernel";
810 reg = <0x00200000 0x00800000>;
811 };
812 partition@9 {
813 label = "NAND.file-system";
814 reg = <0x00a00000 0x0f600000>;
815 };
816 };
817 };
819 &usb2_phy1 {
820 phy-supply = <&ldousb_reg>;
821 };
823 &usb2_phy2 {
824 phy-supply = <&ldousb_reg>;
825 };
827 &gpio7 {
828 ti,no-reset-on-init;
829 ti,no-idle-on-init;
830 };
832 &mac {
833 status = "okay";
834 pinctrl-names = "default", "sleep";
835 pinctrl-0 = <&cpsw_default>;
836 pinctrl-1 = <&cpsw_sleep>;
837 dual_emac;
838 };
840 &cpsw_emac0 {
841 phy_id = <&davinci_mdio>, <2>;
842 phy-mode = "rgmii";
843 dual_emac_res_vlan = <1>;
844 };
846 &cpsw_emac1 {
847 phy_id = <&davinci_mdio>, <3>;
848 phy-mode = "rgmii";
849 dual_emac_res_vlan = <2>;
850 };
852 &davinci_mdio {
853 pinctrl-names = "default", "sleep";
854 pinctrl-0 = <&davinci_mdio_default>;
855 pinctrl-1 = <&davinci_mdio_sleep>;
856 };
858 &dcan1 {
859 status = "ok";
860 pinctrl-names = "default", "sleep", "active";
861 pinctrl-0 = <&dcan1_pins_sleep>;
862 pinctrl-1 = <&dcan1_pins_sleep>;
863 pinctrl-2 = <&dcan1_pins_default>;
864 };
866 &atl {
867 pinctrl-names = "default";
868 pinctrl-0 = <&atl_pins>;
870 assigned-clocks = <&abe_dpll_sys_clk_mux>,
871 <&atl_gfclk_mux>,
872 <&dpll_abe_ck>,
873 <&dpll_abe_m2x2_ck>,
874 <&atl_clkin2_ck>;
875 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
876 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
878 status = "okay";
880 atl2 {
881 bws = <DRA7_ATL_WS_MCASP2_FSX>;
882 aws = <DRA7_ATL_WS_MCASP3_FSX>;
883 };
884 };
886 &mcasp3 {
887 #sound-dai-cells = <0>;
888 pinctrl-names = "default", "sleep";
889 pinctrl-0 = <&mcasp3_pins>;
890 pinctrl-1 = <&mcasp3_sleep_pins>;
892 assigned-clocks = <&mcasp3_ahclkx_mux>;
893 assigned-clock-parents = <&atl_clkin2_ck>;
895 status = "okay";
897 op-mode = <0>; /* MCASP_IIS_MODE */
898 tdm-slots = <2>;
899 /* 4 serializer */
900 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
901 1 2 0 0
902 >;
903 };
905 &mailbox5 {
906 status = "okay";
907 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
908 status = "okay";
909 };
910 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
911 status = "okay";
912 };
913 };
915 &mailbox6 {
916 status = "okay";
917 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
918 status = "okay";
919 };
920 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
921 status = "okay";
922 };
923 };