| blob | c52722b14e4a01577af7768a2b840f97836afbdd |
1 /*
2 * Copyright (c) 2013-2014 Linaro Ltd.
3 * Copyright (c) 2013-2014 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
10 #include "skeleton.dtsi"
11 #include <dt-bindings/clock/hix5hd2-clock.h>
13 / {
14 aliases {
15 serial0 = &uart0;
16 };
18 gic: interrupt-controller@f8a01000 {
19 compatible = "arm,cortex-a9-gic";
20 #interrupt-cells = <3>;
21 #address-cells = <0>;
22 interrupt-controller;
23 /* gic dist base, gic cpu base */
24 reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
25 };
27 soc {
28 #address-cells = <1>;
29 #size-cells = <1>;
30 compatible = "simple-bus";
31 interrupt-parent = <&gic>;
32 ranges = <0 0xf8000000 0x8000000>;
34 amba {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "arm,amba-bus";
38 ranges;
40 timer0: timer@00002000 {
41 compatible = "arm,sp804", "arm,primecell";
42 reg = <0x00002000 0x1000>;
43 /* timer00 & timer01 */
44 interrupts = <0 24 4>;
45 clocks = <&clock HIX5HD2_FIXED_24M>;
46 status = "disabled";
47 };
49 timer1: timer@00a29000 {
50 /*
51 * Only used in NORMAL state, not available ins
52 * SLOW or DOZE state.
53 * The rate is fixed in 24MHz.
54 */
55 compatible = "arm,sp804", "arm,primecell";
56 reg = <0x00a29000 0x1000>;
57 /* timer10 & timer11 */
58 interrupts = <0 25 4>;
59 clocks = <&clock HIX5HD2_FIXED_24M>;
60 status = "disabled";
61 };
63 timer2: timer@00a2a000 {
64 compatible = "arm,sp804", "arm,primecell";
65 reg = <0x00a2a000 0x1000>;
66 /* timer20 & timer21 */
67 interrupts = <0 26 4>;
68 clocks = <&clock HIX5HD2_FIXED_24M>;
69 status = "disabled";
70 };
72 timer3: timer@00a2b000 {
73 compatible = "arm,sp804", "arm,primecell";
74 reg = <0x00a2b000 0x1000>;
75 /* timer30 & timer31 */
76 interrupts = <0 27 4>;
77 clocks = <&clock HIX5HD2_FIXED_24M>;
78 status = "disabled";
79 };
81 timer4: timer@00a81000 {
82 compatible = "arm,sp804", "arm,primecell";
83 reg = <0x00a81000 0x1000>;
84 /* timer30 & timer31 */
85 interrupts = <0 28 4>;
86 clocks = <&clock HIX5HD2_FIXED_24M>;
87 status = "disabled";
88 };
90 uart0: uart@00b00000 {
91 compatible = "arm,pl011", "arm,primecell";
92 reg = <0x00b00000 0x1000>;
93 interrupts = <0 49 4>;
94 clocks = <&clock HIX5HD2_FIXED_83M>;
95 clock-names = "apb_pclk";
96 status = "disabled";
97 };
99 uart1: uart@00006000 {
100 compatible = "arm,pl011", "arm,primecell";
101 reg = <0x00006000 0x1000>;
102 interrupts = <0 50 4>;
103 clocks = <&clock HIX5HD2_FIXED_83M>;
104 clock-names = "apb_pclk";
105 status = "disabled";
106 };
108 uart2: uart@00b02000 {
109 compatible = "arm,pl011", "arm,primecell";
110 reg = <0x00b02000 0x1000>;
111 interrupts = <0 51 4>;
112 clocks = <&clock HIX5HD2_FIXED_83M>;
113 clock-names = "apb_pclk";
114 status = "disabled";
115 };
117 uart3: uart@00b03000 {
118 compatible = "arm,pl011", "arm,primecell";
119 reg = <0x00b03000 0x1000>;
120 interrupts = <0 52 4>;
121 clocks = <&clock HIX5HD2_FIXED_83M>;
122 clock-names = "apb_pclk";
123 status = "disabled";
124 };
126 uart4: uart@00b04000 {
127 compatible = "arm,pl011", "arm,primecell";
128 reg = <0xb04000 0x1000>;
129 interrupts = <0 53 4>;
130 clocks = <&clock HIX5HD2_FIXED_83M>;
131 clock-names = "apb_pclk";
132 status = "disabled";
133 };
135 gpio0: gpio@b20000 {
136 compatible = "arm,pl061", "arm,primecell";
137 reg = <0xb20000 0x1000>;
138 interrupts = <0 108 0x4>;
139 gpio-controller;
140 #gpio-cells = <2>;
141 clocks = <&clock HIX5HD2_FIXED_100M>;
142 clock-names = "apb_pclk";
143 interrupt-controller;
144 #interrupt-cells = <2>;
145 status = "disabled";
146 };
148 gpio1: gpio@b21000 {
149 compatible = "arm,pl061", "arm,primecell";
150 reg = <0xb21000 0x1000>;
151 interrupts = <0 109 0x4>;
152 gpio-controller;
153 #gpio-cells = <2>;
154 clocks = <&clock HIX5HD2_FIXED_100M>;
155 clock-names = "apb_pclk";
156 interrupt-controller;
157 #interrupt-cells = <2>;
158 status = "disabled";
159 };
161 gpio2: gpio@b22000 {
162 compatible = "arm,pl061", "arm,primecell";
163 reg = <0xb22000 0x1000>;
164 interrupts = <0 110 0x4>;
165 gpio-controller;
166 #gpio-cells = <2>;
167 clocks = <&clock HIX5HD2_FIXED_100M>;
168 clock-names = "apb_pclk";
169 interrupt-controller;
170 #interrupt-cells = <2>;
171 status = "disabled";
172 };
174 gpio3: gpio@b23000 {
175 compatible = "arm,pl061", "arm,primecell";
176 reg = <0xb23000 0x1000>;
177 interrupts = <0 111 0x4>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 clocks = <&clock HIX5HD2_FIXED_100M>;
181 clock-names = "apb_pclk";
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 status = "disabled";
185 };
187 gpio4: gpio@b24000 {
188 compatible = "arm,pl061", "arm,primecell";
189 reg = <0xb24000 0x1000>;
190 interrupts = <0 112 0x4>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 clocks = <&clock HIX5HD2_FIXED_100M>;
194 clock-names = "apb_pclk";
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 status = "disabled";
198 };
200 gpio5: gpio@004000 {
201 compatible = "arm,pl061", "arm,primecell";
202 reg = <0x004000 0x1000>;
203 interrupts = <0 113 0x4>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 clocks = <&clock HIX5HD2_FIXED_100M>;
207 clock-names = "apb_pclk";
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 status = "disabled";
211 };
213 gpio6: gpio@b26000 {
214 compatible = "arm,pl061", "arm,primecell";
215 reg = <0xb26000 0x1000>;
216 interrupts = <0 114 0x4>;
217 gpio-controller;
218 #gpio-cells = <2>;
219 clocks = <&clock HIX5HD2_FIXED_100M>;
220 clock-names = "apb_pclk";
221 interrupt-controller;
222 #interrupt-cells = <2>;
223 status = "disabled";
224 };
226 gpio7: gpio@b27000 {
227 compatible = "arm,pl061", "arm,primecell";
228 reg = <0xb27000 0x1000>;
229 interrupts = <0 115 0x4>;
230 gpio-controller;
231 #gpio-cells = <2>;
232 clocks = <&clock HIX5HD2_FIXED_100M>;
233 clock-names = "apb_pclk";
234 interrupt-controller;
235 #interrupt-cells = <2>;
236 status = "disabled";
237 };
239 gpio8: gpio@b28000 {
240 compatible = "arm,pl061", "arm,primecell";
241 reg = <0xb28000 0x1000>;
242 interrupts = <0 116 0x4>;
243 gpio-controller;
244 #gpio-cells = <2>;
245 clocks = <&clock HIX5HD2_FIXED_100M>;
246 clock-names = "apb_pclk";
247 interrupt-controller;
248 #interrupt-cells = <2>;
249 status = "disabled";
250 };
252 gpio9: gpio@b29000 {
253 compatible = "arm,pl061", "arm,primecell";
254 reg = <0xb29000 0x1000>;
255 interrupts = <0 117 0x4>;
256 gpio-controller;
257 #gpio-cells = <2>;
258 clocks = <&clock HIX5HD2_FIXED_100M>;
259 clock-names = "apb_pclk";
260 interrupt-controller;
261 #interrupt-cells = <2>;
262 status = "disabled";
263 };
265 gpio10: gpio@b2a000 {
266 compatible = "arm,pl061", "arm,primecell";
267 reg = <0xb2a000 0x1000>;
268 interrupts = <0 118 0x4>;
269 gpio-controller;
270 #gpio-cells = <2>;
271 clocks = <&clock HIX5HD2_FIXED_100M>;
272 clock-names = "apb_pclk";
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 status = "disabled";
276 };
278 gpio11: gpio@b2b000 {
279 compatible = "arm,pl061", "arm,primecell";
280 reg = <0xb2b000 0x1000>;
281 interrupts = <0 119 0x4>;
282 gpio-controller;
283 #gpio-cells = <2>;
284 clocks = <&clock HIX5HD2_FIXED_100M>;
285 clock-names = "apb_pclk";
286 interrupt-controller;
287 #interrupt-cells = <2>;
288 status = "disabled";
289 };
291 gpio12: gpio@b2c000 {
292 compatible = "arm,pl061", "arm,primecell";
293 reg = <0xb2c000 0x1000>;
294 interrupts = <0 120 0x4>;
295 gpio-controller;
296 #gpio-cells = <2>;
297 clocks = <&clock HIX5HD2_FIXED_100M>;
298 clock-names = "apb_pclk";
299 interrupt-controller;
300 #interrupt-cells = <2>;
301 status = "disabled";
302 };
304 gpio13: gpio@b2d000 {
305 compatible = "arm,pl061", "arm,primecell";
306 reg = <0xb2d000 0x1000>;
307 interrupts = <0 121 0x4>;
308 gpio-controller;
309 #gpio-cells = <2>;
310 clocks = <&clock HIX5HD2_FIXED_100M>;
311 clock-names = "apb_pclk";
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 status = "disabled";
315 };
317 gpio14: gpio@b2e000 {
318 compatible = "arm,pl061", "arm,primecell";
319 reg = <0xb2e000 0x1000>;
320 interrupts = <0 122 0x4>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 clocks = <&clock HIX5HD2_FIXED_100M>;
324 clock-names = "apb_pclk";
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 status = "disabled";
328 };
330 gpio15: gpio@b2f000 {
331 compatible = "arm,pl061", "arm,primecell";
332 reg = <0xb2f000 0x1000>;
333 interrupts = <0 123 0x4>;
334 gpio-controller;
335 #gpio-cells = <2>;
336 clocks = <&clock HIX5HD2_FIXED_100M>;
337 clock-names = "apb_pclk";
338 interrupt-controller;
339 #interrupt-cells = <2>;
340 status = "disabled";
341 };
343 gpio16: gpio@b30000 {
344 compatible = "arm,pl061", "arm,primecell";
345 reg = <0xb30000 0x1000>;
346 interrupts = <0 124 0x4>;
347 gpio-controller;
348 #gpio-cells = <2>;
349 clocks = <&clock HIX5HD2_FIXED_100M>;
350 clock-names = "apb_pclk";
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 status = "disabled";
354 };
356 gpio17: gpio@b31000 {
357 compatible = "arm,pl061", "arm,primecell";
358 reg = <0xb31000 0x1000>;
359 interrupts = <0 125 0x4>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 clocks = <&clock HIX5HD2_FIXED_100M>;
363 clock-names = "apb_pclk";
364 interrupt-controller;
365 #interrupt-cells = <2>;
366 status = "disabled";
367 };
369 wdt0: watchdog@a2c000 {
370 compatible = "arm,sp805", "arm,primecell";
371 arm,primecell-periphid = <0x00141805>;
372 reg = <0xa2c000 0x1000>;
373 interrupts = <0 29 4>;
374 clocks = <&clock HIX5HD2_WDG0_RST>;
375 clock-names = "apb_pclk";
376 };
377 };
379 local_timer@00a00600 {
380 compatible = "arm,cortex-a9-twd-timer";
381 reg = <0x00a00600 0x20>;
382 interrupts = <1 13 0xf01>;
383 };
385 l2: l2-cache {
386 compatible = "arm,pl310-cache";
387 reg = <0x00a10000 0x100000>;
388 interrupts = <0 15 4>;
389 cache-unified;
390 cache-level = <2>;
391 };
393 sysctrl: system-controller@00000000 {
394 compatible = "hisilicon,sysctrl", "syscon";
395 reg = <0x00000000 0x1000>;
396 };
398 reboot {
399 compatible = "syscon-reboot";
400 regmap = <&sysctrl>;
401 offset = <0x4>;
402 mask = <0xdeadbeef>;
403 };
405 cpuctrl@00a22000 {
406 compatible = "hisilicon,cpuctrl";
407 #address-cells = <1>;
408 #size-cells = <1>;
409 reg = <0x00a22000 0x2000>;
410 ranges = <0 0x00a22000 0x2000>;
412 clock: clock@0 {
413 compatible = "hisilicon,hix5hd2-clock";
414 reg = <0 0x2000>;
415 #clock-cells = <1>;
416 };
417 };
419 /* unremovable emmc as mmcblk0 */
420 mmc: mmc@1830000 {
421 compatible = "snps,dw-mshc";
422 reg = <0x1830000 0x1000>;
423 interrupts = <0 35 4>;
424 clocks = <&clock HIX5HD2_MMC_CIU_RST>,
425 <&clock HIX5HD2_MMC_BIU_CLK>;
426 clock-names = "ciu", "biu";
427 };
429 sd: mmc@1820000 {
430 compatible = "snps,dw-mshc";
431 reg = <0x1820000 0x1000>;
432 interrupts = <0 34 4>;
433 clocks = <&clock HIX5HD2_SD_CIU_RST>,
434 <&clock HIX5HD2_SD_BIU_CLK>;
435 clock-names = "ciu","biu";
436 };
438 gmac0: ethernet@1840000 {
439 compatible = "hisilicon,hix5hd2-gmac";
440 reg = <0x1840000 0x1000>,<0x184300c 0x4>;
441 interrupts = <0 71 4>;
442 clocks = <&clock HIX5HD2_MAC0_CLK>;
443 status = "disabled";
444 };
446 gmac1: ethernet@1841000 {
447 compatible = "hisilicon,hix5hd2-gmac";
448 reg = <0x1841000 0x1000>,<0x1843010 0x4>;
449 interrupts = <0 72 4>;
450 clocks = <&clock HIX5HD2_MAC1_CLK>;
451 status = "disabled";
452 };
454 usb0: ehci@1890000 {
455 compatible = "generic-ehci";
456 reg = <0x1890000 0x1000>;
457 interrupts = <0 66 4>;
458 clocks = <&clock HIX5HD2_USB_CLK>;
459 };
461 usb1: ohci@1880000 {
462 compatible = "generic-ohci";
463 reg = <0x1880000 0x1000>;
464 interrupts = <0 67 4>;
465 clocks = <&clock HIX5HD2_USB_CLK>;
466 };
468 peripheral_ctrl: syscon@a20000 {
469 compatible = "syscon";
470 reg = <0xa20000 0x1000>;
471 };
473 sata_phy: phy@1900000 {
474 compatible = "hisilicon,hix5hd2-sata-phy";
475 reg = <0x1900000 0x10000>;
476 #phy-cells = <0>;
477 hisilicon,peripheral-syscon = <&peripheral_ctrl>;
478 hisilicon,power-reg = <0x8 10>;
479 };
481 ahci: sata@1900000 {
482 compatible = "hisilicon,hisi-ahci";
483 reg = <0x1900000 0x10000>;
484 interrupts = <0 70 4>;
485 clocks = <&clock HIX5HD2_SATA_CLK>;
486 };
488 ir: ir@001000 {
489 compatible = "hisilicon,hix5hd2-ir";
490 reg = <0x001000 0x1000>;
491 interrupts = <0 47 4>;
492 clocks = <&clock HIX5HD2_FIXED_24M>;
493 hisilicon,power-syscon = <&sysctrl>;
494 };
496 i2c0: i2c@b10000 {
497 compatible = "hisilicon,hix5hd2-i2c";
498 reg = <0xb10000 0x1000>;
499 interrupts = <0 38 4>;
500 clocks = <&clock HIX5HD2_I2C0_RST>;
501 #address-cells = <1>;
502 #size-cells = <0>;
503 status = "disabled";
504 };
506 i2c1: i2c@b11000 {
507 compatible = "hisilicon,hix5hd2-i2c";
508 reg = <0xb11000 0x1000>;
509 interrupts = <0 39 4>;
510 clocks = <&clock HIX5HD2_I2C1_RST>;
511 #address-cells = <1>;
512 #size-cells = <0>;
513 status = "disabled";
514 };
516 i2c2: i2c@b12000 {
517 compatible = "hisilicon,hix5hd2-i2c";
518 reg = <0xb12000 0x1000>;
519 interrupts = <0 40 4>;
520 clocks = <&clock HIX5HD2_I2C2_RST>;
521 #address-cells = <1>;
522 #size-cells = <0>;
523 status = "disabled";
524 };
526 i2c3: i2c@b13000 {
527 compatible = "hisilicon,hix5hd2-i2c";
528 reg = <0xb13000 0x1000>;
529 interrupts = <0 41 4>;
530 clocks = <&clock HIX5HD2_I2C3_RST>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533 status = "disabled";
534 };
536 i2c4: i2c@b16000 {
537 compatible = "hisilicon,hix5hd2-i2c";
538 reg = <0xb16000 0x1000>;
539 interrupts = <0 43 4>;
540 clocks = <&clock HIX5HD2_I2C4_RST>;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 status = "disabled";
544 };
546 i2c5: i2c@b17000 {
547 compatible = "hisilicon,hix5hd2-i2c";
548 reg = <0xb17000 0x1000>;
549 interrupts = <0 44 4>;
550 clocks = <&clock HIX5HD2_I2C5_RST>;
551 #address-cells = <1>;
552 #size-cells = <0>;
553 status = "disabled";
554 };
555 };
556 };