arch/arm/boot/dts/imx25-pdk.dts

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 /dts-v1/;
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/input/input.h>
  15 #include "imx25.dtsi"
  16
  17 / {
  18         model = "Freescale i.MX25 Product Development Kit";
  19         compatible = "fsl,imx25-pdk", "fsl,imx25";
  20
  21         memory {
  22                 reg = <0x80000000 0x4000000>;
  23         };
  24
  25         regulators {
  26                 compatible = "simple-bus";
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 reg_fec_3v3: regulator@0 {
  31                         compatible = "regulator-fixed";
  32                         reg = <0>;
  33                         regulator-name = "fec-3v3";
  34                         regulator-min-microvolt = <3300000>;
  35                         regulator-max-microvolt = <3300000>;
  36                         gpio = <&gpio2 3 0>;
  37                         enable-active-high;
  38                 };
  39
  40                 reg_2p5v: regulator@1 {
  41                         compatible = "regulator-fixed";
  42                         reg = <1>;
  43                         regulator-name = "2P5V";
  44                         regulator-min-microvolt = <2500000>;
  45                         regulator-max-microvolt = <2500000>;
  46                 };
  47
  48                 reg_3p3v: regulator@2 {
  49                         compatible = "regulator-fixed";
  50                         reg = <2>;
  51                         regulator-name = "3P3V";
  52                         regulator-min-microvolt = <3300000>;
  53                         regulator-max-microvolt = <3300000>;
  54                 };
  55
  56                 reg_can_3v3: regulator@3 {
  57                         compatible = "regulator-fixed";
  58                         reg = <3>;
  59                         regulator-name = "can-3v3";
  60                         regulator-min-microvolt = <3300000>;
  61                         regulator-max-microvolt = <3300000>;
  62                         gpio = <&gpio4 6 0>;
  63                 };
  64         };
  65
  66         sound {
  67                 compatible = "fsl,imx25-pdk-sgtl5000",
  68                              "fsl,imx-audio-sgtl5000";
  69                 model = "imx25-pdk-sgtl5000";
  70                 ssi-controller = <&ssi1>;
  71                 audio-codec = <&codec>;
  72                 audio-routing =
  73                         "MIC_IN", "Mic Jack",
  74                         "Mic Jack", "Mic Bias",
  75                         "Headphone Jack", "HP_OUT";
  76                 mux-int-port = <1>;
  77                 mux-ext-port = <4>;
  78         };
  79
  80         wvga: display {
  81                 model = "CLAA057VC01CW";
  82                 bits-per-pixel = <16>;
  83                 fsl,pcr = <0xfa208b80>;
  84                 bus-width = <18>;
  85                 native-mode = <&wvga_timings>;
  86                 display-timings {
  87                         wvga_timings: 640x480 {
  88                                 hactive = <640>;
  89                                 vactive = <480>;
  90                                 hback-porch = <45>;
  91                                 hfront-porch = <114>;
  92                                 hsync-len = <1>;
  93                                 vback-porch = <33>;
  94                                 vfront-porch = <11>;
  95                                 vsync-len = <1>;
  96                                 clock-frequency = <25200000>;
  97                         };
  98                 };
  99         };
 100 };
 101
 102 &audmux {
 103         pinctrl-names = "default";
 104         pinctrl-0 = <&pinctrl_audmux>;
 105         status = "okay";
 106 };
 107
 108 &can1 {
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&pinctrl_can1>;
 111         xceiver-supply = <&reg_can_3v3>;
 112         status = "okay";
 113 };
 114
 115 &esdhc1 {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&pinctrl_esdhc1>;
 118         cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 119         wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
 120         status = "okay";
 121 };
 122
 123 &fec {
 124         phy-mode = "rmii";
 125         pinctrl-names = "default";
 126         pinctrl-0 = <&pinctrl_fec>;
 127         phy-supply = <&reg_fec_3v3>;
 128         phy-reset-gpios = <&gpio4 8 0>;
 129         status = "okay";
 130 };
 131
 132 &i2c1 {
 133         clock-frequency = <100000>;
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&pinctrl_i2c1>;
 136         status = "okay";
 137
 138         codec: sgtl5000@0a {
 139                 compatible = "fsl,sgtl5000";
 140                 reg = <0x0a>;
 141                 clocks = <&clks 129>;
 142                 VDDA-supply = <&reg_2p5v>;
 143                 VDDIO-supply = <&reg_3p3v>;
 144         };
 145 };
 146
 147 &iomuxc {
 148         imx25-pdk {
 149                 pinctrl_audmux: audmuxgrp {
 150                         fsl,pins = <
 151                                 MX25_PAD_RW__AUD4_TXFS                  0xe0
 152                                 MX25_PAD_OE__AUD4_TXC                   0xe0
 153                                 MX25_PAD_EB0__AUD4_TXD                  0xe0
 154                                 MX25_PAD_EB1__AUD4_RXD                  0xe0
 155                         >;
 156                 };
 157
 158                 pinctrl_can1: can1grp {
 159                         fsl,pins = <
 160                                 MX25_PAD_GPIO_A__CAN1_TX                0x0
 161                                 MX25_PAD_GPIO_B__CAN1_RX                0x0
 162                                 MX25_PAD_D14__GPIO_4_6                  0x80000000
 163                         >;
 164                 };
 165
 166                 pinctrl_esdhc1: esdhc1grp {
 167                         fsl,pins = <
 168                                 MX25_PAD_SD1_CMD__SD1_CMD               0x80000000
 169                                 MX25_PAD_SD1_CLK__SD1_CLK               0x80000000
 170                                 MX25_PAD_SD1_DATA0__SD1_DATA0           0x80000000
 171                                 MX25_PAD_SD1_DATA1__SD1_DATA1           0x80000000
 172                                 MX25_PAD_SD1_DATA2__SD1_DATA2           0x80000000
 173                                 MX25_PAD_SD1_DATA3__SD1_DATA3           0x80000000
 174                                 MX25_PAD_A14__GPIO_2_0                  0x80000000
 175                                 MX25_PAD_A15__GPIO_2_1                  0x80000000
 176                         >;
 177                 };
 178
 179                 pinctrl_fec: fecgrp {
 180                         fsl,pins = <
 181                                 MX25_PAD_FEC_MDC__FEC_MDC               0x80000000
 182                                 MX25_PAD_FEC_MDIO__FEC_MDIO             0x400001e0
 183                                 MX25_PAD_FEC_TDATA0__FEC_TDATA0         0x80000000
 184                                 MX25_PAD_FEC_TDATA1__FEC_TDATA1         0x80000000
 185                                 MX25_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
 186                                 MX25_PAD_FEC_RDATA0__FEC_RDATA0         0x80000000
 187                                 MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x80000000
 188                                 MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x80000000
 189                                 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK         0x1c0
 190                                 MX25_PAD_A17__GPIO_2_3                  0x80000000
 191                                 MX25_PAD_D12__GPIO_4_8                  0x80000000
 192                         >;
 193                 };
 194
 195                 pinctrl_i2c1: i2c1grp {
 196                         fsl,pins = <
 197                                 MX25_PAD_I2C1_CLK__I2C1_CLK             0x80000000
 198                                 MX25_PAD_I2C1_DAT__I2C1_DAT             0x80000000
 199                         >;
 200                 };
 201
 202                 pinctrl_kpp: kppgrp {
 203                         fsl,pins = <
 204                                 MX25_PAD_KPP_ROW0__KPP_ROW0     0x80000000
 205                                 MX25_PAD_KPP_ROW1__KPP_ROW1     0x80000000
 206                                 MX25_PAD_KPP_ROW2__KPP_ROW2     0x80000000
 207                                 MX25_PAD_KPP_ROW3__KPP_ROW3     0x80000000
 208                                 MX25_PAD_KPP_COL0__KPP_COL0     0x80000000
 209                                 MX25_PAD_KPP_COL1__KPP_COL1     0x80000000
 210                                 MX25_PAD_KPP_COL2__KPP_COL2     0x80000000
 211                                 MX25_PAD_KPP_COL3__KPP_COL3     0x80000000
 212                         >;
 213                 };
 214
 215                 pinctrl_lcd: lcdgrp {
 216                         fsl,pins = <
 217                                 MX25_PAD_LD0__LD0               0xe0
 218                                 MX25_PAD_LD1__LD1               0xe0
 219                                 MX25_PAD_LD2__LD2               0xe0
 220                                 MX25_PAD_LD3__LD3               0xe0
 221                                 MX25_PAD_LD4__LD4               0xe0
 222                                 MX25_PAD_LD5__LD5               0xe0
 223                                 MX25_PAD_LD6__LD6               0xe0
 224                                 MX25_PAD_LD7__LD7               0xe0
 225                                 MX25_PAD_LD8__LD8               0xe0
 226                                 MX25_PAD_LD9__LD9               0xe0
 227                                 MX25_PAD_LD10__LD10             0xe0
 228                                 MX25_PAD_LD11__LD11             0xe0
 229                                 MX25_PAD_LD12__LD12             0xe0
 230                                 MX25_PAD_LD13__LD13             0xe0
 231                                 MX25_PAD_LD14__LD14             0xe0
 232                                 MX25_PAD_LD15__LD15             0xe0
 233                                 MX25_PAD_GPIO_E__LD16           0xe0
 234                                 MX25_PAD_GPIO_F__LD17           0xe0
 235                                 MX25_PAD_HSYNC__HSYNC           0xe0
 236                                 MX25_PAD_VSYNC__VSYNC           0xe0
 237                                 MX25_PAD_LSCLK__LSCLK           0xe0
 238                                 MX25_PAD_OE_ACD__OE_ACD         0xe0
 239                                 MX25_PAD_CONTRAST__CONTRAST     0xe0
 240                         >;
 241                 };
 242
 243                 pinctrl_uart1: uart1grp {
 244                         fsl,pins = <
 245                                 MX25_PAD_UART1_RTS__UART1_RTS           0xe0
 246                                 MX25_PAD_UART1_CTS__UART1_CTS           0xe0
 247                                 MX25_PAD_UART1_TXD__UART1_TXD           0x80000000
 248                                 MX25_PAD_UART1_RXD__UART1_RXD           0xc0
 249                         >;
 250                 };
 251         };
 252 };
 253
 254 &lcdc {
 255         display = <&wvga>;
 256         fsl,lpccr = <0x00a903ff>;
 257         fsl,lscr1 = <0x00120300>;
 258         fsl,dmacr = <0x00020010>;
 259         pinctrl-names = "default";
 260         pinctrl-0 = <&pinctrl_lcd>;
 261         status = "okay";
 262 };
 263
 264 &nfc {
 265         nand-on-flash-bbt;
 266         status = "okay";
 267 };
 268
 269 &kpp {
 270         pinctrl-names = "default";
 271         pinctrl-0 = <&pinctrl_kpp>;
 272         linux,keymap = <
 273                         MATRIX_KEY(0x0, 0x0, KEY_UP)
 274                         MATRIX_KEY(0x0, 0x1, KEY_DOWN)
 275                         MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN)
 276                         MATRIX_KEY(0x0, 0x3, KEY_HOME)
 277                         MATRIX_KEY(0x1, 0x0, KEY_RIGHT)
 278                         MATRIX_KEY(0x1, 0x1, KEY_LEFT)
 279                         MATRIX_KEY(0x1, 0x2, KEY_ENTER)
 280                         MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP)
 281                         MATRIX_KEY(0x2, 0x0, KEY_F6)
 282                         MATRIX_KEY(0x2, 0x1, KEY_F8)
 283                         MATRIX_KEY(0x2, 0x2, KEY_F9)
 284                         MATRIX_KEY(0x2, 0x3, KEY_F10)
 285                         MATRIX_KEY(0x3, 0x0, KEY_F1)
 286                         MATRIX_KEY(0x3, 0x1, KEY_F2)
 287                         MATRIX_KEY(0x3, 0x2, KEY_F3)
 288                         MATRIX_KEY(0x3, 0x2, KEY_POWER)
 289         >;
 290         status = "okay";
 291 };
 292
 293 &ssi1 {
 294         codec-handle = <&codec>;
 295         status = "okay";
 296 };
 297
 298 &uart1 {
 299         pinctrl-names = "default";
 300         pinctrl-0 = <&pinctrl_uart1>;
 301         fsl,uart-has-rtscts;
 302         status = "okay";
 303 };
 304
 305 &usbhost1 {
 306         phy_type = "serial";
 307         dr_mode = "host";
 308         status = "okay";
 309 };
 310
 311 &usbotg {
 312         phy_type = "utmi";
 313         dr_mode = "otg";
 314         external-vbus-divider;
 315         status = "okay";
 316 };