| blob | cd170376eaca6be3bc6416363250271590b75153 |
1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
13 #include "skeleton.dtsi"
14 #include "imx53-pinfunc.h"
15 #include <dt-bindings/clock/imx5-clock.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
20 / {
21 aliases {
22 ethernet0 = &fec;
23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
30 i2c0 = &i2c1;
31 i2c1 = &i2c2;
32 i2c2 = &i2c3;
33 mmc0 = &esdhc1;
34 mmc1 = &esdhc2;
35 mmc2 = &esdhc3;
36 mmc3 = &esdhc4;
37 serial0 = &uart1;
38 serial1 = &uart2;
39 serial2 = &uart3;
40 serial3 = &uart4;
41 serial4 = &uart5;
42 spi0 = &ecspi1;
43 spi1 = &ecspi2;
44 spi2 = &cspi;
45 };
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 cpu0: cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a8";
53 reg = <0x0>;
54 clocks = <&clks IMX5_CLK_ARM>;
55 clock-latency = <61036>;
56 voltage-tolerance = <5>;
57 operating-points = <
58 /* kHz */
59 166666 850000
60 400000 900000
61 800000 1050000
62 1000000 1200000
63 1200000 1300000
64 >;
65 };
66 };
68 display-subsystem {
69 compatible = "fsl,imx-display-subsystem";
70 ports = <&ipu_di0>, <&ipu_di1>;
71 };
73 tzic: tz-interrupt-controller@0fffc000 {
74 compatible = "fsl,imx53-tzic", "fsl,tzic";
75 interrupt-controller;
76 #interrupt-cells = <1>;
77 reg = <0x0fffc000 0x4000>;
78 };
80 clocks {
81 #address-cells = <1>;
82 #size-cells = <0>;
84 ckil {
85 compatible = "fsl,imx-ckil", "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <32768>;
88 };
90 ckih1 {
91 compatible = "fsl,imx-ckih1", "fixed-clock";
92 #clock-cells = <0>;
93 clock-frequency = <22579200>;
94 };
96 ckih2 {
97 compatible = "fsl,imx-ckih2", "fixed-clock";
98 #clock-cells = <0>;
99 clock-frequency = <0>;
100 };
102 osc {
103 compatible = "fsl,imx-osc", "fixed-clock";
104 #clock-cells = <0>;
105 clock-frequency = <24000000>;
106 };
107 };
109 soc {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "simple-bus";
113 interrupt-parent = <&tzic>;
114 ranges;
116 sata: sata@10000000 {
117 compatible = "fsl,imx53-ahci";
118 reg = <0x10000000 0x1000>;
119 interrupts = <28>;
120 clocks = <&clks IMX5_CLK_SATA_GATE>,
121 <&clks IMX5_CLK_SATA_REF>,
122 <&clks IMX5_CLK_AHB>;
123 clock-names = "sata", "sata_ref", "ahb";
124 status = "disabled";
125 };
127 ipu: ipu@18000000 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 compatible = "fsl,imx53-ipu";
131 reg = <0x18000000 0x08000000>;
132 interrupts = <11 10>;
133 clocks = <&clks IMX5_CLK_IPU_GATE>,
134 <&clks IMX5_CLK_IPU_DI0_GATE>,
135 <&clks IMX5_CLK_IPU_DI1_GATE>;
136 clock-names = "bus", "di0", "di1";
137 resets = <&src 2>;
139 ipu_di0: port@2 {
140 #address-cells = <1>;
141 #size-cells = <0>;
142 reg = <2>;
144 ipu_di0_disp0: endpoint@0 {
145 reg = <0>;
146 };
148 ipu_di0_lvds0: endpoint@1 {
149 reg = <1>;
150 remote-endpoint = <&lvds0_in>;
151 };
152 };
154 ipu_di1: port@3 {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 reg = <3>;
159 ipu_di1_disp1: endpoint@0 {
160 reg = <0>;
161 };
163 ipu_di1_lvds1: endpoint@1 {
164 reg = <1>;
165 remote-endpoint = <&lvds1_in>;
166 };
168 ipu_di1_tve: endpoint@2 {
169 reg = <2>;
170 remote-endpoint = <&tve_in>;
171 };
172 };
173 };
175 aips@50000000 { /* AIPS1 */
176 compatible = "fsl,aips-bus", "simple-bus";
177 #address-cells = <1>;
178 #size-cells = <1>;
179 reg = <0x50000000 0x10000000>;
180 ranges;
182 spba@50000000 {
183 compatible = "fsl,spba-bus", "simple-bus";
184 #address-cells = <1>;
185 #size-cells = <1>;
186 reg = <0x50000000 0x40000>;
187 ranges;
189 esdhc1: esdhc@50004000 {
190 compatible = "fsl,imx53-esdhc";
191 reg = <0x50004000 0x4000>;
192 interrupts = <1>;
193 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
194 <&clks IMX5_CLK_DUMMY>,
195 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
196 clock-names = "ipg", "ahb", "per";
197 bus-width = <4>;
198 status = "disabled";
199 };
201 esdhc2: esdhc@50008000 {
202 compatible = "fsl,imx53-esdhc";
203 reg = <0x50008000 0x4000>;
204 interrupts = <2>;
205 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
206 <&clks IMX5_CLK_DUMMY>,
207 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
208 clock-names = "ipg", "ahb", "per";
209 bus-width = <4>;
210 status = "disabled";
211 };
213 uart3: serial@5000c000 {
214 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
215 reg = <0x5000c000 0x4000>;
216 interrupts = <33>;
217 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
218 <&clks IMX5_CLK_UART3_PER_GATE>;
219 clock-names = "ipg", "per";
220 status = "disabled";
221 };
223 ecspi1: ecspi@50010000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
227 reg = <0x50010000 0x4000>;
228 interrupts = <36>;
229 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
230 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
231 clock-names = "ipg", "per";
232 status = "disabled";
233 };
235 ssi2: ssi@50014000 {
236 #sound-dai-cells = <0>;
237 compatible = "fsl,imx53-ssi",
238 "fsl,imx51-ssi",
239 "fsl,imx21-ssi";
240 reg = <0x50014000 0x4000>;
241 interrupts = <30>;
242 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
243 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
244 clock-names = "ipg", "baud";
245 dmas = <&sdma 24 1 0>,
246 <&sdma 25 1 0>;
247 dma-names = "rx", "tx";
248 fsl,fifo-depth = <15>;
249 status = "disabled";
250 };
252 esdhc3: esdhc@50020000 {
253 compatible = "fsl,imx53-esdhc";
254 reg = <0x50020000 0x4000>;
255 interrupts = <3>;
256 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
257 <&clks IMX5_CLK_DUMMY>,
258 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
259 clock-names = "ipg", "ahb", "per";
260 bus-width = <4>;
261 status = "disabled";
262 };
264 esdhc4: esdhc@50024000 {
265 compatible = "fsl,imx53-esdhc";
266 reg = <0x50024000 0x4000>;
267 interrupts = <4>;
268 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
269 <&clks IMX5_CLK_DUMMY>,
270 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
271 clock-names = "ipg", "ahb", "per";
272 bus-width = <4>;
273 status = "disabled";
274 };
275 };
277 aipstz1: bridge@53f00000 {
278 compatible = "fsl,imx53-aipstz";
279 reg = <0x53f00000 0x60>;
280 };
282 usbphy0: usbphy@0 {
283 compatible = "usb-nop-xceiv";
284 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
285 clock-names = "main_clk";
286 status = "okay";
287 };
289 usbphy1: usbphy@1 {
290 compatible = "usb-nop-xceiv";
291 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
292 clock-names = "main_clk";
293 status = "okay";
294 };
296 usbotg: usb@53f80000 {
297 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
298 reg = <0x53f80000 0x0200>;
299 interrupts = <18>;
300 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
301 fsl,usbmisc = <&usbmisc 0>;
302 fsl,usbphy = <&usbphy0>;
303 status = "disabled";
304 };
306 usbh1: usb@53f80200 {
307 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
308 reg = <0x53f80200 0x0200>;
309 interrupts = <14>;
310 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
311 fsl,usbmisc = <&usbmisc 1>;
312 fsl,usbphy = <&usbphy1>;
313 dr_mode = "host";
314 status = "disabled";
315 };
317 usbh2: usb@53f80400 {
318 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
319 reg = <0x53f80400 0x0200>;
320 interrupts = <16>;
321 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
322 fsl,usbmisc = <&usbmisc 2>;
323 dr_mode = "host";
324 status = "disabled";
325 };
327 usbh3: usb@53f80600 {
328 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
329 reg = <0x53f80600 0x0200>;
330 interrupts = <17>;
331 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
332 fsl,usbmisc = <&usbmisc 3>;
333 dr_mode = "host";
334 status = "disabled";
335 };
337 usbmisc: usbmisc@53f80800 {
338 #index-cells = <1>;
339 compatible = "fsl,imx53-usbmisc";
340 reg = <0x53f80800 0x200>;
341 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
342 };
344 gpio1: gpio@53f84000 {
345 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
346 reg = <0x53f84000 0x4000>;
347 interrupts = <50 51>;
348 gpio-controller;
349 #gpio-cells = <2>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
352 };
354 gpio2: gpio@53f88000 {
355 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
356 reg = <0x53f88000 0x4000>;
357 interrupts = <52 53>;
358 gpio-controller;
359 #gpio-cells = <2>;
360 interrupt-controller;
361 #interrupt-cells = <2>;
362 };
364 gpio3: gpio@53f8c000 {
365 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
366 reg = <0x53f8c000 0x4000>;
367 interrupts = <54 55>;
368 gpio-controller;
369 #gpio-cells = <2>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 };
374 gpio4: gpio@53f90000 {
375 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
376 reg = <0x53f90000 0x4000>;
377 interrupts = <56 57>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
382 };
384 kpp: kpp@53f94000 {
385 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
386 reg = <0x53f94000 0x4000>;
387 interrupts = <60>;
388 clocks = <&clks IMX5_CLK_DUMMY>;
389 status = "disabled";
390 };
392 wdog1: wdog@53f98000 {
393 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
394 reg = <0x53f98000 0x4000>;
395 interrupts = <58>;
396 clocks = <&clks IMX5_CLK_DUMMY>;
397 };
399 wdog2: wdog@53f9c000 {
400 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
401 reg = <0x53f9c000 0x4000>;
402 interrupts = <59>;
403 clocks = <&clks IMX5_CLK_DUMMY>;
404 status = "disabled";
405 };
407 gpt: timer@53fa0000 {
408 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
409 reg = <0x53fa0000 0x4000>;
410 interrupts = <39>;
411 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
412 <&clks IMX5_CLK_GPT_HF_GATE>;
413 clock-names = "ipg", "per";
414 };
416 iomuxc: iomuxc@53fa8000 {
417 compatible = "fsl,imx53-iomuxc";
418 reg = <0x53fa8000 0x4000>;
419 };
421 gpr: iomuxc-gpr@53fa8000 {
422 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
423 reg = <0x53fa8000 0xc>;
424 };
426 ldb: ldb@53fa8008 {
427 #address-cells = <1>;
428 #size-cells = <0>;
429 compatible = "fsl,imx53-ldb";
430 reg = <0x53fa8008 0x4>;
431 gpr = <&gpr>;
432 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
433 <&clks IMX5_CLK_LDB_DI1_SEL>,
434 <&clks IMX5_CLK_IPU_DI0_SEL>,
435 <&clks IMX5_CLK_IPU_DI1_SEL>,
436 <&clks IMX5_CLK_LDB_DI0_GATE>,
437 <&clks IMX5_CLK_LDB_DI1_GATE>;
438 clock-names = "di0_pll", "di1_pll",
439 "di0_sel", "di1_sel",
440 "di0", "di1";
441 status = "disabled";
443 lvds-channel@0 {
444 #address-cells = <1>;
445 #size-cells = <0>;
446 reg = <0>;
447 status = "disabled";
449 port@0 {
450 reg = <0>;
452 lvds0_in: endpoint {
453 remote-endpoint = <&ipu_di0_lvds0>;
454 };
455 };
456 };
458 lvds-channel@1 {
459 #address-cells = <1>;
460 #size-cells = <0>;
461 reg = <1>;
462 status = "disabled";
464 port@1 {
465 reg = <1>;
467 lvds1_in: endpoint {
468 remote-endpoint = <&ipu_di1_lvds1>;
469 };
470 };
471 };
472 };
474 pwm1: pwm@53fb4000 {
475 #pwm-cells = <2>;
476 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
477 reg = <0x53fb4000 0x4000>;
478 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
479 <&clks IMX5_CLK_PWM1_HF_GATE>;
480 clock-names = "ipg", "per";
481 interrupts = <61>;
482 };
484 pwm2: pwm@53fb8000 {
485 #pwm-cells = <2>;
486 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
487 reg = <0x53fb8000 0x4000>;
488 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
489 <&clks IMX5_CLK_PWM2_HF_GATE>;
490 clock-names = "ipg", "per";
491 interrupts = <94>;
492 };
494 uart1: serial@53fbc000 {
495 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
496 reg = <0x53fbc000 0x4000>;
497 interrupts = <31>;
498 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
499 <&clks IMX5_CLK_UART1_PER_GATE>;
500 clock-names = "ipg", "per";
501 status = "disabled";
502 };
504 uart2: serial@53fc0000 {
505 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
506 reg = <0x53fc0000 0x4000>;
507 interrupts = <32>;
508 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
509 <&clks IMX5_CLK_UART2_PER_GATE>;
510 clock-names = "ipg", "per";
511 status = "disabled";
512 };
514 can1: can@53fc8000 {
515 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
516 reg = <0x53fc8000 0x4000>;
517 interrupts = <82>;
518 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
519 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
520 clock-names = "ipg", "per";
521 status = "disabled";
522 };
524 can2: can@53fcc000 {
525 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
526 reg = <0x53fcc000 0x4000>;
527 interrupts = <83>;
528 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
529 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
530 clock-names = "ipg", "per";
531 status = "disabled";
532 };
534 src: src@53fd0000 {
535 compatible = "fsl,imx53-src", "fsl,imx51-src";
536 reg = <0x53fd0000 0x4000>;
537 #reset-cells = <1>;
538 };
540 clks: ccm@53fd4000{
541 compatible = "fsl,imx53-ccm";
542 reg = <0x53fd4000 0x4000>;
543 interrupts = <0 71 0x04 0 72 0x04>;
544 #clock-cells = <1>;
545 };
547 gpio5: gpio@53fdc000 {
548 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
549 reg = <0x53fdc000 0x4000>;
550 interrupts = <103 104>;
551 gpio-controller;
552 #gpio-cells = <2>;
553 interrupt-controller;
554 #interrupt-cells = <2>;
555 };
557 gpio6: gpio@53fe0000 {
558 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
559 reg = <0x53fe0000 0x4000>;
560 interrupts = <105 106>;
561 gpio-controller;
562 #gpio-cells = <2>;
563 interrupt-controller;
564 #interrupt-cells = <2>;
565 };
567 gpio7: gpio@53fe4000 {
568 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
569 reg = <0x53fe4000 0x4000>;
570 interrupts = <107 108>;
571 gpio-controller;
572 #gpio-cells = <2>;
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 };
577 i2c3: i2c@53fec000 {
578 #address-cells = <1>;
579 #size-cells = <0>;
580 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
581 reg = <0x53fec000 0x4000>;
582 interrupts = <64>;
583 clocks = <&clks IMX5_CLK_I2C3_GATE>;
584 status = "disabled";
585 };
587 uart4: serial@53ff0000 {
588 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
589 reg = <0x53ff0000 0x4000>;
590 interrupts = <13>;
591 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
592 <&clks IMX5_CLK_UART4_PER_GATE>;
593 clock-names = "ipg", "per";
594 status = "disabled";
595 };
596 };
598 aips@60000000 { /* AIPS2 */
599 compatible = "fsl,aips-bus", "simple-bus";
600 #address-cells = <1>;
601 #size-cells = <1>;
602 reg = <0x60000000 0x10000000>;
603 ranges;
605 aipstz2: bridge@63f00000 {
606 compatible = "fsl,imx53-aipstz";
607 reg = <0x63f00000 0x60>;
608 };
610 iim: iim@63f98000 {
611 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
612 reg = <0x63f98000 0x4000>;
613 interrupts = <69>;
614 clocks = <&clks IMX5_CLK_IIM_GATE>;
615 };
617 uart5: serial@63f90000 {
618 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
619 reg = <0x63f90000 0x4000>;
620 interrupts = <86>;
621 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
622 <&clks IMX5_CLK_UART5_PER_GATE>;
623 clock-names = "ipg", "per";
624 status = "disabled";
625 };
627 owire: owire@63fa4000 {
628 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
629 reg = <0x63fa4000 0x4000>;
630 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
631 status = "disabled";
632 };
634 ecspi2: ecspi@63fac000 {
635 #address-cells = <1>;
636 #size-cells = <0>;
637 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
638 reg = <0x63fac000 0x4000>;
639 interrupts = <37>;
640 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
641 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
642 clock-names = "ipg", "per";
643 status = "disabled";
644 };
646 sdma: sdma@63fb0000 {
647 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
648 reg = <0x63fb0000 0x4000>;
649 interrupts = <6>;
650 clocks = <&clks IMX5_CLK_SDMA_GATE>,
651 <&clks IMX5_CLK_SDMA_GATE>;
652 clock-names = "ipg", "ahb";
653 #dma-cells = <3>;
654 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
655 };
657 cspi: cspi@63fc0000 {
658 #address-cells = <1>;
659 #size-cells = <0>;
660 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
661 reg = <0x63fc0000 0x4000>;
662 interrupts = <38>;
663 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
664 <&clks IMX5_CLK_CSPI_IPG_GATE>;
665 clock-names = "ipg", "per";
666 status = "disabled";
667 };
669 i2c2: i2c@63fc4000 {
670 #address-cells = <1>;
671 #size-cells = <0>;
672 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
673 reg = <0x63fc4000 0x4000>;
674 interrupts = <63>;
675 clocks = <&clks IMX5_CLK_I2C2_GATE>;
676 status = "disabled";
677 };
679 i2c1: i2c@63fc8000 {
680 #address-cells = <1>;
681 #size-cells = <0>;
682 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
683 reg = <0x63fc8000 0x4000>;
684 interrupts = <62>;
685 clocks = <&clks IMX5_CLK_I2C1_GATE>;
686 status = "disabled";
687 };
689 ssi1: ssi@63fcc000 {
690 #sound-dai-cells = <0>;
691 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
692 "fsl,imx21-ssi";
693 reg = <0x63fcc000 0x4000>;
694 interrupts = <29>;
695 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
696 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
697 clock-names = "ipg", "baud";
698 dmas = <&sdma 28 0 0>,
699 <&sdma 29 0 0>;
700 dma-names = "rx", "tx";
701 fsl,fifo-depth = <15>;
702 status = "disabled";
703 };
705 audmux: audmux@63fd0000 {
706 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
707 reg = <0x63fd0000 0x4000>;
708 status = "disabled";
709 };
711 nfc: nand@63fdb000 {
712 compatible = "fsl,imx53-nand";
713 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
714 interrupts = <8>;
715 clocks = <&clks IMX5_CLK_NFC_GATE>;
716 status = "disabled";
717 };
719 ssi3: ssi@63fe8000 {
720 #sound-dai-cells = <0>;
721 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
722 "fsl,imx21-ssi";
723 reg = <0x63fe8000 0x4000>;
724 interrupts = <96>;
725 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
726 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
727 clock-names = "ipg", "baud";
728 dmas = <&sdma 46 0 0>,
729 <&sdma 47 0 0>;
730 dma-names = "rx", "tx";
731 fsl,fifo-depth = <15>;
732 status = "disabled";
733 };
735 fec: ethernet@63fec000 {
736 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
737 reg = <0x63fec000 0x4000>;
738 interrupts = <87>;
739 clocks = <&clks IMX5_CLK_FEC_GATE>,
740 <&clks IMX5_CLK_FEC_GATE>,
741 <&clks IMX5_CLK_FEC_GATE>;
742 clock-names = "ipg", "ahb", "ptp";
743 status = "disabled";
744 };
746 tve: tve@63ff0000 {
747 compatible = "fsl,imx53-tve";
748 reg = <0x63ff0000 0x1000>;
749 interrupts = <92>;
750 clocks = <&clks IMX5_CLK_TVE_GATE>,
751 <&clks IMX5_CLK_IPU_DI1_SEL>;
752 clock-names = "tve", "di_sel";
753 status = "disabled";
755 port {
756 tve_in: endpoint {
757 remote-endpoint = <&ipu_di1_tve>;
758 };
759 };
760 };
762 vpu: vpu@63ff4000 {
763 compatible = "fsl,imx53-vpu", "cnm,coda7541";
764 reg = <0x63ff4000 0x1000>;
765 interrupts = <9>;
766 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
767 <&clks IMX5_CLK_VPU_GATE>;
768 clock-names = "per", "ahb";
769 resets = <&src 1>;
770 iram = <&ocram>;
771 };
773 sahara: crypto@63ff8000 {
774 compatible = "fsl,imx53-sahara";
775 reg = <0x63ff8000 0x4000>;
776 interrupts = <19 20>;
777 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
778 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
779 clock-names = "ipg", "ahb";
780 };
781 };
783 ocram: sram@f8000000 {
784 compatible = "mmio-sram";
785 reg = <0xf8000000 0x20000>;
786 clocks = <&clks IMX5_CLK_OCRAM>;
787 };
789 pmu {
790 compatible = "arm,cortex-a8-pmu";
791 interrupts = <77>;
792 };
793 };
794 };