arch/arm/boot/dts/imx6qdl-gw52xx.dtsi

   1 /*
   2  * Copyright 2013 Gateworks Corporation
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14 / {
  15         /* these are used by bootloader for disabling nodes */
  16         aliases {
  17                 led0 = &led0;
  18                 led1 = &led1;
  19                 led2 = &led2;
  20                 nand = &gpmi;
  21                 ssi0 = &ssi1;
  22                 usb0 = &usbh1;
  23                 usb1 = &usbotg;
  24         };
  25
  26         chosen {
  27                 bootargs = "console=ttymxc1,115200";
  28         };
  29
  30         backlight {
  31                 compatible = "pwm-backlight";
  32                 pwms = <&pwm4 0 5000000>;
  33                 brightness-levels = <0 4 8 16 32 64 128 255>;
  34                 default-brightness-level = <7>;
  35         };
  36
  37         leds {
  38                 compatible = "gpio-leds";
  39                 pinctrl-names = "default";
  40                 pinctrl-0 = <&pinctrl_gpio_leds>;
  41
  42                 led0: user1 {
  43                         label = "user1";
  44                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  45                         default-state = "on";
  46                         linux,default-trigger = "heartbeat";
  47                 };
  48
  49                 led1: user2 {
  50                         label = "user2";
  51                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  52                         default-state = "off";
  53                 };
  54
  55                 led2: user3 {
  56                         label = "user3";
  57                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  58                         default-state = "off";
  59                 };
  60         };
  61
  62         memory {
  63                 reg = <0x10000000 0x20000000>;
  64         };
  65
  66         pps {
  67                 compatible = "pps-gpio";
  68                 pinctrl-names = "default";
  69                 pinctrl-0 = <&pinctrl_pps>;
  70                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  71                 status = "okay";
  72         };
  73
  74         regulators {
  75                 compatible = "simple-bus";
  76                 #address-cells = <1>;
  77                 #size-cells = <0>;
  78
  79                 reg_1p0v: regulator@0 {
  80                         compatible = "regulator-fixed";
  81                         reg = <0>;
  82                         regulator-name = "1P0V";
  83                         regulator-min-microvolt = <1000000>;
  84                         regulator-max-microvolt = <1000000>;
  85                         regulator-always-on;
  86                 };
  87
  88                 /* remove this fixed regulator once ltc3676__sw2 driver available */
  89                 reg_1p8v: regulator@1 {
  90                         compatible = "regulator-fixed";
  91                         reg = <1>;
  92                         regulator-name = "1P8V";
  93                         regulator-min-microvolt = <1800000>;
  94                         regulator-max-microvolt = <1800000>;
  95                         regulator-always-on;
  96                 };
  97
  98                 reg_3p3v: regulator@2 {
  99                         compatible = "regulator-fixed";
 100                         reg = <2>;
 101                         regulator-name = "3P3V";
 102                         regulator-min-microvolt = <3300000>;
 103                         regulator-max-microvolt = <3300000>;
 104                         regulator-always-on;
 105                 };
 106
 107                 reg_5p0v: regulator@3 {
 108                         compatible = "regulator-fixed";
 109                         reg = <3>;
 110                         regulator-name = "5P0V";
 111                         regulator-min-microvolt = <5000000>;
 112                         regulator-max-microvolt = <5000000>;
 113                         regulator-always-on;
 114                 };
 115
 116                 reg_usb_otg_vbus: regulator@4 {
 117                         compatible = "regulator-fixed";
 118                         reg = <4>;
 119                         regulator-name = "usb_otg_vbus";
 120                         regulator-min-microvolt = <5000000>;
 121                         regulator-max-microvolt = <5000000>;
 122                         gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 123                         enable-active-high;
 124                 };
 125         };
 126
 127         sound {
 128                 compatible = "fsl,imx6q-ventana-sgtl5000",
 129                              "fsl,imx-audio-sgtl5000";
 130                 model = "sgtl5000-audio";
 131                 ssi-controller = <&ssi1>;
 132                 audio-codec = <&codec>;
 133                 audio-routing =
 134                         "MIC_IN", "Mic Jack",
 135                         "Mic Jack", "Mic Bias",
 136                         "Headphone Jack", "HP_OUT";
 137                 mux-int-port = <1>;
 138                 mux-ext-port = <4>;
 139         };
 140 };
 141
 142 &audmux {
 143         pinctrl-names = "default";
 144         pinctrl-0 = <&pinctrl_audmux>;
 145         status = "okay";
 146 };
 147
 148 &can1 {
 149         pinctrl-names = "default";
 150         pinctrl-0 = <&pinctrl_flexcan1>;
 151         status = "okay";
 152 };
 153
 154 &fec {
 155         pinctrl-names = "default";
 156         pinctrl-0 = <&pinctrl_enet>;
 157         phy-mode = "rgmii";
 158         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 159         status = "okay";
 160 };
 161
 162 &gpmi {
 163         pinctrl-names = "default";
 164         pinctrl-0 = <&pinctrl_gpmi_nand>;
 165         status = "okay";
 166 };
 167
 168 &hdmi {
 169         ddc-i2c-bus = <&i2c3>;
 170         status = "okay";
 171 };
 172
 173 &i2c1 {
 174         clock-frequency = <100000>;
 175         pinctrl-names = "default";
 176         pinctrl-0 = <&pinctrl_i2c1>;
 177         status = "okay";
 178
 179         eeprom1: eeprom@50 {
 180                 compatible = "atmel,24c02";
 181                 reg = <0x50>;
 182                 pagesize = <16>;
 183         };
 184
 185         eeprom2: eeprom@51 {
 186                 compatible = "atmel,24c02";
 187                 reg = <0x51>;
 188                 pagesize = <16>;
 189         };
 190
 191         eeprom3: eeprom@52 {
 192                 compatible = "atmel,24c02";
 193                 reg = <0x52>;
 194                 pagesize = <16>;
 195         };
 196
 197         eeprom4: eeprom@53 {
 198                 compatible = "atmel,24c02";
 199                 reg = <0x53>;
 200                 pagesize = <16>;
 201         };
 202
 203         gpio: pca9555@23 {
 204                 compatible = "nxp,pca9555";
 205                 reg = <0x23>;
 206                 gpio-controller;
 207                 #gpio-cells = <2>;
 208         };
 209
 210         rtc: ds1672@68 {
 211                 compatible = "dallas,ds1672";
 212                 reg = <0x68>;
 213         };
 214 };
 215
 216 &i2c2 {
 217         clock-frequency = <100000>;
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_i2c2>;
 220         status = "okay";
 221 };
 222
 223 &i2c3 {
 224         clock-frequency = <100000>;
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pinctrl_i2c3>;
 227         status = "okay";
 228
 229         codec: sgtl5000@0a {
 230                 compatible = "fsl,sgtl5000";
 231                 reg = <0x0a>;
 232                 clocks = <&clks 201>;
 233                 VDDA-supply = <&reg_1p8v>;
 234                 VDDIO-supply = <&reg_3p3v>;
 235         };
 236
 237         touchscreen: egalax_ts@04 {
 238                 compatible = "eeti,egalax_ts";
 239                 reg = <0x04>;
 240                 interrupt-parent = <&gpio7>;
 241                 interrupts = <12 2>;
 242                 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
 243         };
 244 };
 245
 246 &ldb {
 247         status = "okay";
 248
 249         lvds-channel@0 {
 250                 fsl,data-mapping = "spwg";
 251                 fsl,data-width = <18>;
 252                 status = "okay";
 253
 254                 display-timings {
 255                         native-mode = <&timing0>;
 256                         timing0: hsd100pxn1 {
 257                                 clock-frequency = <65000000>;
 258                                 hactive = <1024>;
 259                                 vactive = <768>;
 260                                 hback-porch = <220>;
 261                                 hfront-porch = <40>;
 262                                 vback-porch = <21>;
 263                                 vfront-porch = <7>;
 264                                 hsync-len = <60>;
 265                                 vsync-len = <10>;
 266                         };
 267                 };
 268         };
 269 };
 270
 271 &pcie {
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&pinctrl_pcie>;
 274         reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
 275         status = "okay";
 276 };
 277
 278 &pwm4 {
 279         pinctrl-names = "default";
 280         pinctrl-0 = <&pinctrl_pwm4>;
 281         status = "okay";
 282 };
 283
 284 &ssi1 {
 285         status = "okay";
 286 };
 287
 288 &uart1 {
 289         pinctrl-names = "default";
 290         pinctrl-0 = <&pinctrl_uart1>;
 291         status = "okay";
 292 };
 293
 294 &uart2 {
 295         pinctrl-names = "default";
 296         pinctrl-0 = <&pinctrl_uart2>;
 297         status = "okay";
 298 };
 299
 300 &uart5 {
 301         pinctrl-names = "default";
 302         pinctrl-0 = <&pinctrl_uart5>;
 303         status = "okay";
 304 };
 305
 306 &usbotg {
 307         vbus-supply = <&reg_usb_otg_vbus>;
 308         pinctrl-names = "default";
 309         pinctrl-0 = <&pinctrl_usbotg>;
 310         disable-over-current;
 311         status = "okay";
 312 };
 313
 314 &usbh1 {
 315         status = "okay";
 316 };
 317
 318 &usdhc3 {
 319         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 320         pinctrl-0 = <&pinctrl_usdhc3>;
 321         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 322         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 323         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 324         vmmc-supply = <&reg_3p3v>;
 325         no-1-8-v; /* firmware will remove if board revision supports */
 326         status = "okay";
 327 };
 328
 329 &iomuxc {
 330         imx6qdl-gw52xx {
 331                 pinctrl_audmux: audmuxgrp {
 332                         fsl,pins = <
 333                                 MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
 334                                 MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
 335                                 MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
 336                                 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
 337                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0 /* AUD4_MCK */
 338                         >;
 339                 };
 340
 341                 pinctrl_enet: enetgrp {
 342                         fsl,pins = <
 343                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 344                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 345                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 346                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 347                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 348                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 349                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 350                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 351                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 352                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 353                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 354                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 355                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 356                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 357                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 358                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 359                                 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0 /* PHY Reset */
 360                         >;
 361                 };
 362
 363                 pinctrl_flexcan1: flexcan1grp {
 364                         fsl,pins = <
 365                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 366                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 367                                 MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x4001b0b0 /* CAN_STBY */
 368                         >;
 369                 };
 370
 371                 pinctrl_gpio_leds: gpioledsgrp {
 372                         fsl,pins = <
 373                                 MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x1b0b0
 374                                 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x1b0b0
 375                                 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15  0x1b0b0
 376                         >;
 377                 };
 378
 379                 pinctrl_gpmi_nand: gpminandgrp {
 380                         fsl,pins = <
 381                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 382                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 383                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 384                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 385                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 386                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 387                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 388                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 389                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 390                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 391                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 392                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 393                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 394                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 395                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 396                         >;
 397                 };
 398
 399                 pinctrl_i2c1: i2c1grp {
 400                         fsl,pins = <
 401                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 402                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 403                         >;
 404                 };
 405
 406                 pinctrl_i2c2: i2c2grp {
 407                         fsl,pins = <
 408                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 409                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 410                         >;
 411                 };
 412
 413                 pinctrl_i2c3: i2c3grp {
 414                         fsl,pins = <
 415                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 416                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 417                         >;
 418                 };
 419
 420                 pinctrl_pcie: pciegrp {
 421                         fsl,pins = <
 422                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0 /* PCIE_RST# */
 423                         >;
 424                 };
 425
 426                 pinctrl_pps: ppsgrp {
 427                         fsl,pins = <
 428                                 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 429                         >;
 430                 };
 431
 432                 pinctrl_pwm4: pwm4grp {
 433                         fsl,pins = <
 434                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 435                         >;
 436                 };
 437
 438                 pinctrl_uart1: uart1grp {
 439                         fsl,pins = <
 440                                 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 441                                 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 442                         >;
 443                 };
 444
 445                 pinctrl_uart2: uart2grp {
 446                         fsl,pins = <
 447                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 448                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 449                         >;
 450                 };
 451
 452                 pinctrl_uart5: uart5grp {
 453                         fsl,pins = <
 454                                 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 455                                 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 456                         >;
 457                 };
 458
 459                 pinctrl_usbotg: usbotggrp {
 460                         fsl,pins = <
 461                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 462                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0 /* OTG_PWR_EN */
 463                         >;
 464                 };
 465
 466                 pinctrl_usdhc3: usdhc3grp {
 467                         fsl,pins = <
 468                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 469                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 470                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 471                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 472                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 473                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 474                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 475                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 476                         >;
 477                 };
 478
 479                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 480                         fsl,pins = <
 481                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 482                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x170b9
 483                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 484                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 485                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 486                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 487                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 488                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 489                         >;
 490                 };
 491
 492                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 493                         fsl,pins = <
 494                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 495                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 496                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 497                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 498                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 499                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 500                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 501                                 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 502                         >;
 503                 };
 504         };
 505 };