mm: hugetlb: fix hugepage memory leak caused by wrong reserve count
[linux/fpc-iii.git] / arch / arm / boot / dts / imx6qdl-microsom.dtsi
blob6d4069cc9419eae3361fece8cd52a1e29b25b853
1 /*
2  * Copyright (C) 2013,2014 Russell King
3  *
4  * This file is dual-licensed: you can use it either under the terms
5  * of the GPL or the X11 license, at your option. Note that this dual
6  * licensing only applies to this file, and not this project as a
7  * whole.
8  *
9  *  a) This file is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License
11  *     version 2 as published by the Free Software Foundation.
12  *
13  *     This file is distributed in the hope that it will be useful
14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *     GNU General Public License for more details.
17  *
18  * Or, alternatively
19  *
20  *  b) Permission is hereby granted, free of charge, to any person
21  *     obtaining a copy of this software and associated documentation
22  *     files (the "Software"), to deal in the Software without
23  *     restriction, including without limitation the rights to use
24  *     copy, modify, merge, publish, distribute, sublicense, and/or
25  *     sell copies of the Software, and to permit persons to whom the
26  *     Software is furnished to do so, subject to the following
27  *     conditions:
28  *
29  *     The above copyright notice and this permission notice shall be
30  *     included in all copies or substantial portions of the Software.
31  *
32  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39  *     OTHER DEALINGS IN THE SOFTWARE.
40  */
41 #include <dt-bindings/gpio/gpio.h>
42 / {
43         clk_sdio: sdio-clock {
44                 compatible = "gpio-gate-clock";
45                 #clock-cells = <0>;
46                 pinctrl-names = "default";
47                 pinctrl-0 = <&pinctrl_microsom_brcm_osc>;
48                 enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
49         };
51         regulators {
52                 compatible = "simple-bus";
54                 reg_brcm: brcm-reg {
55                         compatible = "regulator-fixed";
56                         enable-active-high;
57                         gpio = <&gpio3 19 0>;
58                         pinctrl-names = "default";
59                         pinctrl-0 = <&pinctrl_microsom_brcm_reg>;
60                         regulator-name = "brcm_reg";
61                         regulator-min-microvolt = <3300000>;
62                         regulator-max-microvolt = <3300000>;
63                         startup-delay-us = <200000>;
64                 };
65         };
67         usdhc1_pwrseq: usdhc1_pwrseq {
68                 compatible = "mmc-pwrseq-simple";
69                 reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>,
70                               <&gpio6 0 GPIO_ACTIVE_LOW>;
71                 clocks = <&clk_sdio>;
72                 clock-names = "ext_clock";
73         };
76 &iomuxc {
77         microsom {
78                 pinctrl_microsom_brcm_bt: microsom-brcm-bt {
79                         fsl,pins = <
80                                 MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00       0x40013070
81                                 MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01       0x40013070
82                                 MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04       0x40013070
83                         >;
84                 };
86                 pinctrl_microsom_brcm_osc: microsom-brcm-osc {
87                         fsl,pins = <
88                                 MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05      0x40013070
89                         >;
90                 };
92                 pinctrl_microsom_brcm_reg: microsom-brcm-reg {
93                         fsl,pins = <
94                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x40013070
95                         >;
96                 };
98                 pinctrl_microsom_brcm_wifi: microsom-brcm-wifi {
99                         fsl,pins = <
100                                 MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K  0x1b0b0
101                                 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20     0x40013070
102                                 MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26        0x40013070
103                                 MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27        0x40013070
104                         >;
105                 };
107                 pinctrl_microsom_uart1: microsom-uart1 {
108                         fsl,pins = <
109                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
110                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
111                         >;
112                 };
114                 pinctrl_microsom_uart4: microsom-uart4 {
115                         fsl,pins = <
116                                 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
117                                 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
118                                 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
119                                 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
120                         >;
121                 };
123                 pinctrl_microsom_usdhc1: microsom-usdhc1 {
124                         fsl,pins = <
125                                 MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
126                                 MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
127                                 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
128                                 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
129                                 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
130                                 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
131                         >;
132                 };
133         };
136 &uart1 {
137         pinctrl-names = "default";
138         pinctrl-0 = <&pinctrl_microsom_uart1>;
139         status = "okay";
142 /* UART4 - Connected to optional BRCM Wifi/BT/FM */
143 &uart4 {
144         pinctrl-names = "default";
145         pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>;
146         fsl,uart-has-rtscts;
147         status = "okay";
150 /* USDHC1 - Connected to optional BRCM Wifi/BT/FM */
151 &usdhc1 {
152         pinctrl-names = "default";
153         pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>;
154         bus-width = <4>;
155         mmc-pwrseq = <&usdhc1_pwrseq>;
156         keep-power-in-suspend;
157         non-removable;
158         vmmc-supply = <&reg_brcm>;
159         status = "okay";