| blob | 167f77b3bd43654c45d181e2a7f31965f6f1c946 |
1 /*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
9 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "imx6sx-pinfunc.h"
14 #include "skeleton.dtsi"
16 / {
17 aliases {
18 can0 = &flexcan1;
19 can1 = &flexcan2;
20 ethernet0 = &fec1;
21 ethernet1 = &fec2;
22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
29 i2c0 = &i2c1;
30 i2c1 = &i2c2;
31 i2c2 = &i2c3;
32 i2c3 = &i2c4;
33 mmc0 = &usdhc1;
34 mmc1 = &usdhc2;
35 mmc2 = &usdhc3;
36 mmc3 = &usdhc4;
37 serial0 = &uart1;
38 serial1 = &uart2;
39 serial2 = &uart3;
40 serial3 = &uart4;
41 serial4 = &uart5;
42 serial5 = &uart6;
43 spi0 = &ecspi1;
44 spi1 = &ecspi2;
45 spi2 = &ecspi3;
46 spi3 = &ecspi4;
47 spi4 = &ecspi5;
48 usbphy0 = &usbphy1;
49 usbphy1 = &usbphy2;
50 };
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
56 cpu0: cpu@0 {
57 compatible = "arm,cortex-a9";
58 device_type = "cpu";
59 reg = <0>;
60 next-level-cache = <&L2>;
61 operating-points = <
62 /* kHz uV */
63 996000 1250000
64 792000 1175000
65 396000 1075000
66 >;
67 fsl,soc-operating-points = <
68 /* ARM kHz SOC uV */
69 996000 1175000
70 792000 1175000
71 396000 1175000
72 >;
73 clock-latency = <61036>; /* two CLK32 periods */
74 clocks = <&clks IMX6SX_CLK_ARM>,
75 <&clks IMX6SX_CLK_PLL2_PFD2>,
76 <&clks IMX6SX_CLK_STEP>,
77 <&clks IMX6SX_CLK_PLL1_SW>,
78 <&clks IMX6SX_CLK_PLL1_SYS>;
79 clock-names = "arm", "pll2_pfd2_396m", "step",
80 "pll1_sw", "pll1_sys";
81 arm-supply = <®_arm>;
82 soc-supply = <®_soc>;
83 };
84 };
86 intc: interrupt-controller@00a01000 {
87 compatible = "arm,cortex-a9-gic";
88 #interrupt-cells = <3>;
89 interrupt-controller;
90 reg = <0x00a01000 0x1000>,
91 <0x00a00100 0x100>;
92 interrupt-parent = <&intc>;
93 };
95 clocks {
96 #address-cells = <1>;
97 #size-cells = <0>;
99 ckil: clock@0 {
100 compatible = "fixed-clock";
101 reg = <0>;
102 #clock-cells = <0>;
103 clock-frequency = <32768>;
104 clock-output-names = "ckil";
105 };
107 osc: clock@1 {
108 compatible = "fixed-clock";
109 reg = <1>;
110 #clock-cells = <0>;
111 clock-frequency = <24000000>;
112 clock-output-names = "osc";
113 };
115 ipp_di0: clock@2 {
116 compatible = "fixed-clock";
117 reg = <2>;
118 #clock-cells = <0>;
119 clock-frequency = <0>;
120 clock-output-names = "ipp_di0";
121 };
123 ipp_di1: clock@3 {
124 compatible = "fixed-clock";
125 reg = <3>;
126 #clock-cells = <0>;
127 clock-frequency = <0>;
128 clock-output-names = "ipp_di1";
129 };
130 };
132 soc {
133 #address-cells = <1>;
134 #size-cells = <1>;
135 compatible = "simple-bus";
136 interrupt-parent = <&gpc>;
137 ranges;
139 pmu {
140 compatible = "arm,cortex-a9-pmu";
141 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
142 };
144 ocram: sram@00900000 {
145 compatible = "mmio-sram";
146 reg = <0x00900000 0x20000>;
147 clocks = <&clks IMX6SX_CLK_OCRAM>;
148 };
150 L2: l2-cache@00a02000 {
151 compatible = "arm,pl310-cache";
152 reg = <0x00a02000 0x1000>;
153 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
154 cache-unified;
155 cache-level = <2>;
156 arm,tag-latency = <4 2 3>;
157 arm,data-latency = <4 2 3>;
158 };
160 dma_apbh: dma-apbh@01804000 {
161 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
162 reg = <0x01804000 0x2000>;
163 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
167 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
168 #dma-cells = <1>;
169 dma-channels = <4>;
170 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
171 };
173 gpmi: gpmi-nand@01806000{
174 compatible = "fsl,imx6sx-gpmi-nand";
175 #address-cells = <1>;
176 #size-cells = <1>;
177 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
178 reg-names = "gpmi-nand", "bch";
179 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-names = "bch";
181 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
182 <&clks IMX6SX_CLK_GPMI_APB>,
183 <&clks IMX6SX_CLK_GPMI_BCH>,
184 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
185 <&clks IMX6SX_CLK_PER1_BCH>;
186 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
187 "gpmi_bch_apb", "per1_bch";
188 dmas = <&dma_apbh 0>;
189 dma-names = "rx-tx";
190 status = "disabled";
191 };
193 aips1: aips-bus@02000000 {
194 compatible = "fsl,aips-bus", "simple-bus";
195 #address-cells = <1>;
196 #size-cells = <1>;
197 reg = <0x02000000 0x100000>;
198 ranges;
200 spba-bus@02000000 {
201 compatible = "fsl,spba-bus", "simple-bus";
202 #address-cells = <1>;
203 #size-cells = <1>;
204 reg = <0x02000000 0x40000>;
205 ranges;
207 spdif: spdif@02004000 {
208 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
209 reg = <0x02004000 0x4000>;
210 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
211 dmas = <&sdma 14 18 0>,
212 <&sdma 15 18 0>;
213 dma-names = "rx", "tx";
214 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
215 <&clks IMX6SX_CLK_OSC>,
216 <&clks IMX6SX_CLK_SPDIF>,
217 <&clks 0>, <&clks 0>, <&clks 0>,
218 <&clks IMX6SX_CLK_IPG>,
219 <&clks 0>, <&clks 0>,
220 <&clks IMX6SX_CLK_SPBA>;
221 clock-names = "core", "rxtx0",
222 "rxtx1", "rxtx2",
223 "rxtx3", "rxtx4",
224 "rxtx5", "rxtx6",
225 "rxtx7", "dma";
226 status = "disabled";
227 };
229 ecspi1: ecspi@02008000 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
233 reg = <0x02008000 0x4000>;
234 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&clks IMX6SX_CLK_ECSPI1>,
236 <&clks IMX6SX_CLK_ECSPI1>;
237 clock-names = "ipg", "per";
238 status = "disabled";
239 };
241 ecspi2: ecspi@0200c000 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
245 reg = <0x0200c000 0x4000>;
246 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clks IMX6SX_CLK_ECSPI2>,
248 <&clks IMX6SX_CLK_ECSPI2>;
249 clock-names = "ipg", "per";
250 status = "disabled";
251 };
253 ecspi3: ecspi@02010000 {
254 #address-cells = <1>;
255 #size-cells = <0>;
256 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
257 reg = <0x02010000 0x4000>;
258 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&clks IMX6SX_CLK_ECSPI3>,
260 <&clks IMX6SX_CLK_ECSPI3>;
261 clock-names = "ipg", "per";
262 status = "disabled";
263 };
265 ecspi4: ecspi@02014000 {
266 #address-cells = <1>;
267 #size-cells = <0>;
268 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
269 reg = <0x02014000 0x4000>;
270 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&clks IMX6SX_CLK_ECSPI4>,
272 <&clks IMX6SX_CLK_ECSPI4>;
273 clock-names = "ipg", "per";
274 status = "disabled";
275 };
277 uart1: serial@02020000 {
278 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
279 reg = <0x02020000 0x4000>;
280 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clks IMX6SX_CLK_UART_IPG>,
282 <&clks IMX6SX_CLK_UART_SERIAL>;
283 clock-names = "ipg", "per";
284 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
285 dma-names = "rx", "tx";
286 status = "disabled";
287 };
289 esai: esai@02024000 {
290 reg = <0x02024000 0x4000>;
291 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
293 <&clks IMX6SX_CLK_ESAI_MEM>,
294 <&clks IMX6SX_CLK_ESAI_EXTAL>,
295 <&clks IMX6SX_CLK_ESAI_IPG>,
296 <&clks IMX6SX_CLK_SPBA>;
297 clock-names = "core", "mem", "extal",
298 "fsys", "dma";
299 status = "disabled";
300 };
302 ssi1: ssi@02028000 {
303 #sound-dai-cells = <0>;
304 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
305 reg = <0x02028000 0x4000>;
306 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
308 <&clks IMX6SX_CLK_SSI1>;
309 clock-names = "ipg", "baud";
310 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
311 dma-names = "rx", "tx";
312 fsl,fifo-depth = <15>;
313 status = "disabled";
314 };
316 ssi2: ssi@0202c000 {
317 #sound-dai-cells = <0>;
318 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
319 reg = <0x0202c000 0x4000>;
320 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
322 <&clks IMX6SX_CLK_SSI2>;
323 clock-names = "ipg", "baud";
324 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
325 dma-names = "rx", "tx";
326 fsl,fifo-depth = <15>;
327 status = "disabled";
328 };
330 ssi3: ssi@02030000 {
331 #sound-dai-cells = <0>;
332 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
333 reg = <0x02030000 0x4000>;
334 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
336 <&clks IMX6SX_CLK_SSI3>;
337 clock-names = "ipg", "baud";
338 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
339 dma-names = "rx", "tx";
340 fsl,fifo-depth = <15>;
341 status = "disabled";
342 };
344 asrc: asrc@02034000 {
345 reg = <0x02034000 0x4000>;
346 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
348 <&clks IMX6SX_CLK_ASRC_IPG>,
349 <&clks IMX6SX_CLK_SPDIF>,
350 <&clks IMX6SX_CLK_SPBA>;
351 clock-names = "mem", "ipg", "asrck", "dma";
352 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
353 <&sdma 19 20 1>, <&sdma 20 20 1>,
354 <&sdma 21 20 1>, <&sdma 22 20 1>;
355 dma-names = "rxa", "rxb", "rxc",
356 "txa", "txb", "txc";
357 status = "okay";
358 };
359 };
361 pwm1: pwm@02080000 {
362 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
363 reg = <0x02080000 0x4000>;
364 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&clks IMX6SX_CLK_PWM1>,
366 <&clks IMX6SX_CLK_PWM1>;
367 clock-names = "ipg", "per";
368 #pwm-cells = <2>;
369 };
371 pwm2: pwm@02084000 {
372 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
373 reg = <0x02084000 0x4000>;
374 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&clks IMX6SX_CLK_PWM2>,
376 <&clks IMX6SX_CLK_PWM2>;
377 clock-names = "ipg", "per";
378 #pwm-cells = <2>;
379 };
381 pwm3: pwm@02088000 {
382 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
383 reg = <0x02088000 0x4000>;
384 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&clks IMX6SX_CLK_PWM3>,
386 <&clks IMX6SX_CLK_PWM3>;
387 clock-names = "ipg", "per";
388 #pwm-cells = <2>;
389 };
391 pwm4: pwm@0208c000 {
392 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
393 reg = <0x0208c000 0x4000>;
394 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&clks IMX6SX_CLK_PWM4>,
396 <&clks IMX6SX_CLK_PWM4>;
397 clock-names = "ipg", "per";
398 #pwm-cells = <2>;
399 };
401 flexcan1: can@02090000 {
402 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
403 reg = <0x02090000 0x4000>;
404 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
406 <&clks IMX6SX_CLK_CAN1_SERIAL>;
407 clock-names = "ipg", "per";
408 status = "disabled";
409 };
411 flexcan2: can@02094000 {
412 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
413 reg = <0x02094000 0x4000>;
414 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
416 <&clks IMX6SX_CLK_CAN2_SERIAL>;
417 clock-names = "ipg", "per";
418 status = "disabled";
419 };
421 gpt: gpt@02098000 {
422 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
423 reg = <0x02098000 0x4000>;
424 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
426 <&clks IMX6SX_CLK_GPT_3M>;
427 clock-names = "ipg", "per";
428 };
430 gpio1: gpio@0209c000 {
431 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
432 reg = <0x0209c000 0x4000>;
433 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
435 gpio-controller;
436 #gpio-cells = <2>;
437 interrupt-controller;
438 #interrupt-cells = <2>;
439 };
441 gpio2: gpio@020a0000 {
442 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
443 reg = <0x020a0000 0x4000>;
444 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
446 gpio-controller;
447 #gpio-cells = <2>;
448 interrupt-controller;
449 #interrupt-cells = <2>;
450 };
452 gpio3: gpio@020a4000 {
453 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
454 reg = <0x020a4000 0x4000>;
455 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
461 };
463 gpio4: gpio@020a8000 {
464 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
465 reg = <0x020a8000 0x4000>;
466 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
468 gpio-controller;
469 #gpio-cells = <2>;
470 interrupt-controller;
471 #interrupt-cells = <2>;
472 };
474 gpio5: gpio@020ac000 {
475 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
476 reg = <0x020ac000 0x4000>;
477 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
479 gpio-controller;
480 #gpio-cells = <2>;
481 interrupt-controller;
482 #interrupt-cells = <2>;
483 };
485 gpio6: gpio@020b0000 {
486 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
487 reg = <0x020b0000 0x4000>;
488 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
490 gpio-controller;
491 #gpio-cells = <2>;
492 interrupt-controller;
493 #interrupt-cells = <2>;
494 };
496 gpio7: gpio@020b4000 {
497 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
498 reg = <0x020b4000 0x4000>;
499 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
501 gpio-controller;
502 #gpio-cells = <2>;
503 interrupt-controller;
504 #interrupt-cells = <2>;
505 };
507 kpp: kpp@020b8000 {
508 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
509 reg = <0x020b8000 0x4000>;
510 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&clks IMX6SX_CLK_DUMMY>;
512 status = "disabled";
513 };
515 wdog1: wdog@020bc000 {
516 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
517 reg = <0x020bc000 0x4000>;
518 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&clks IMX6SX_CLK_DUMMY>;
520 };
522 wdog2: wdog@020c0000 {
523 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
524 reg = <0x020c0000 0x4000>;
525 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&clks IMX6SX_CLK_DUMMY>;
527 status = "disabled";
528 };
530 clks: ccm@020c4000 {
531 compatible = "fsl,imx6sx-ccm";
532 reg = <0x020c4000 0x4000>;
533 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
535 #clock-cells = <1>;
536 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
537 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
538 };
540 anatop: anatop@020c8000 {
541 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
542 "syscon", "simple-bus";
543 reg = <0x020c8000 0x1000>;
544 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
548 regulator-1p1@110 {
549 compatible = "fsl,anatop-regulator";
550 regulator-name = "vdd1p1";
551 regulator-min-microvolt = <800000>;
552 regulator-max-microvolt = <1375000>;
553 regulator-always-on;
554 anatop-reg-offset = <0x110>;
555 anatop-vol-bit-shift = <8>;
556 anatop-vol-bit-width = <5>;
557 anatop-min-bit-val = <4>;
558 anatop-min-voltage = <800000>;
559 anatop-max-voltage = <1375000>;
560 };
562 regulator-3p0@120 {
563 compatible = "fsl,anatop-regulator";
564 regulator-name = "vdd3p0";
565 regulator-min-microvolt = <2800000>;
566 regulator-max-microvolt = <3150000>;
567 regulator-always-on;
568 anatop-reg-offset = <0x120>;
569 anatop-vol-bit-shift = <8>;
570 anatop-vol-bit-width = <5>;
571 anatop-min-bit-val = <0>;
572 anatop-min-voltage = <2625000>;
573 anatop-max-voltage = <3400000>;
574 };
576 regulator-2p5@130 {
577 compatible = "fsl,anatop-regulator";
578 regulator-name = "vdd2p5";
579 regulator-min-microvolt = <2100000>;
580 regulator-max-microvolt = <2875000>;
581 regulator-always-on;
582 anatop-reg-offset = <0x130>;
583 anatop-vol-bit-shift = <8>;
584 anatop-vol-bit-width = <5>;
585 anatop-min-bit-val = <0>;
586 anatop-min-voltage = <2100000>;
587 anatop-max-voltage = <2875000>;
588 };
590 reg_arm: regulator-vddcore@140 {
591 compatible = "fsl,anatop-regulator";
592 regulator-name = "vddarm";
593 regulator-min-microvolt = <725000>;
594 regulator-max-microvolt = <1450000>;
595 regulator-always-on;
596 anatop-reg-offset = <0x140>;
597 anatop-vol-bit-shift = <0>;
598 anatop-vol-bit-width = <5>;
599 anatop-delay-reg-offset = <0x170>;
600 anatop-delay-bit-shift = <24>;
601 anatop-delay-bit-width = <2>;
602 anatop-min-bit-val = <1>;
603 anatop-min-voltage = <725000>;
604 anatop-max-voltage = <1450000>;
605 };
607 reg_pcie: regulator-vddpcie@140 {
608 compatible = "fsl,anatop-regulator";
609 regulator-name = "vddpcie";
610 regulator-min-microvolt = <725000>;
611 regulator-max-microvolt = <1450000>;
612 anatop-reg-offset = <0x140>;
613 anatop-vol-bit-shift = <9>;
614 anatop-vol-bit-width = <5>;
615 anatop-delay-reg-offset = <0x170>;
616 anatop-delay-bit-shift = <26>;
617 anatop-delay-bit-width = <2>;
618 anatop-min-bit-val = <1>;
619 anatop-min-voltage = <725000>;
620 anatop-max-voltage = <1450000>;
621 };
623 reg_soc: regulator-vddsoc@140 {
624 compatible = "fsl,anatop-regulator";
625 regulator-name = "vddsoc";
626 regulator-min-microvolt = <725000>;
627 regulator-max-microvolt = <1450000>;
628 regulator-always-on;
629 anatop-reg-offset = <0x140>;
630 anatop-vol-bit-shift = <18>;
631 anatop-vol-bit-width = <5>;
632 anatop-delay-reg-offset = <0x170>;
633 anatop-delay-bit-shift = <28>;
634 anatop-delay-bit-width = <2>;
635 anatop-min-bit-val = <1>;
636 anatop-min-voltage = <725000>;
637 anatop-max-voltage = <1450000>;
638 };
639 };
641 tempmon: tempmon {
642 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
643 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
644 fsl,tempmon = <&anatop>;
645 fsl,tempmon-data = <&ocotp>;
646 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
647 };
649 usbphy1: usbphy@020c9000 {
650 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
651 reg = <0x020c9000 0x1000>;
652 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&clks IMX6SX_CLK_USBPHY1>;
654 fsl,anatop = <&anatop>;
655 };
657 usbphy2: usbphy@020ca000 {
658 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
659 reg = <0x020ca000 0x1000>;
660 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&clks IMX6SX_CLK_USBPHY2>;
662 fsl,anatop = <&anatop>;
663 };
665 snvs: snvs@020cc000 {
666 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
667 reg = <0x020cc000 0x4000>;
669 snvs_rtc: snvs-rtc-lp {
670 compatible = "fsl,sec-v4.0-mon-rtc-lp";
671 regmap = <&snvs>;
672 offset = <0x34>;
673 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
674 };
676 snvs_poweroff: snvs-poweroff {
677 compatible = "syscon-poweroff";
678 regmap = <&snvs>;
679 offset = <0x38>;
680 mask = <0x60>;
681 status = "disabled";
682 };
684 snvs_pwrkey: snvs-powerkey {
685 compatible = "fsl,sec-v4.0-pwrkey";
686 regmap = <&snvs>;
687 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
688 linux,keycode = <KEY_POWER>;
689 wakeup-source;
690 };
691 };
693 epit1: epit@020d0000 {
694 reg = <0x020d0000 0x4000>;
695 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
696 };
698 epit2: epit@020d4000 {
699 reg = <0x020d4000 0x4000>;
700 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
701 };
703 src: src@020d8000 {
704 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
705 reg = <0x020d8000 0x4000>;
706 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
708 #reset-cells = <1>;
709 };
711 gpc: gpc@020dc000 {
712 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
713 reg = <0x020dc000 0x4000>;
714 interrupt-controller;
715 #interrupt-cells = <3>;
716 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
717 interrupt-parent = <&intc>;
718 };
720 iomuxc: iomuxc@020e0000 {
721 compatible = "fsl,imx6sx-iomuxc";
722 reg = <0x020e0000 0x4000>;
723 };
725 gpr: iomuxc-gpr@020e4000 {
726 compatible = "fsl,imx6sx-iomuxc-gpr",
727 "fsl,imx6q-iomuxc-gpr", "syscon";
728 reg = <0x020e4000 0x4000>;
729 };
731 sdma: sdma@020ec000 {
732 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
733 reg = <0x020ec000 0x4000>;
734 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&clks IMX6SX_CLK_SDMA>,
736 <&clks IMX6SX_CLK_SDMA>;
737 clock-names = "ipg", "ahb";
738 #dma-cells = <3>;
739 /* imx6sx reuses imx6q sdma firmware */
740 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
741 };
742 };
744 aips2: aips-bus@02100000 {
745 compatible = "fsl,aips-bus", "simple-bus";
746 #address-cells = <1>;
747 #size-cells = <1>;
748 reg = <0x02100000 0x100000>;
749 ranges;
751 crypto: caam@2100000 {
752 compatible = "fsl,sec-v4.0";
753 fsl,sec-era = <4>;
754 #address-cells = <1>;
755 #size-cells = <1>;
756 reg = <0x2100000 0x10000>;
757 ranges = <0 0x2100000 0x10000>;
758 interrupt-parent = <&intc>;
759 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
760 <&clks IMX6SX_CLK_CAAM_ACLK>,
761 <&clks IMX6SX_CLK_CAAM_IPG>,
762 <&clks IMX6SX_CLK_EIM_SLOW>;
763 clock-names = "mem", "aclk", "ipg", "emi_slow";
765 sec_jr0: jr0@1000 {
766 compatible = "fsl,sec-v4.0-job-ring";
767 reg = <0x1000 0x1000>;
768 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
769 };
771 sec_jr1: jr1@2000 {
772 compatible = "fsl,sec-v4.0-job-ring";
773 reg = <0x2000 0x1000>;
774 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
775 };
776 };
778 usbotg1: usb@02184000 {
779 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
780 reg = <0x02184000 0x200>;
781 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&clks IMX6SX_CLK_USBOH3>;
783 fsl,usbphy = <&usbphy1>;
784 fsl,usbmisc = <&usbmisc 0>;
785 fsl,anatop = <&anatop>;
786 status = "disabled";
787 };
789 usbotg2: usb@02184200 {
790 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
791 reg = <0x02184200 0x200>;
792 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&clks IMX6SX_CLK_USBOH3>;
794 fsl,usbphy = <&usbphy2>;
795 fsl,usbmisc = <&usbmisc 1>;
796 status = "disabled";
797 };
799 usbh: usb@02184400 {
800 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
801 reg = <0x02184400 0x200>;
802 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&clks IMX6SX_CLK_USBOH3>;
804 fsl,usbmisc = <&usbmisc 2>;
805 phy_type = "hsic";
806 fsl,anatop = <&anatop>;
807 dr_mode = "host";
808 status = "disabled";
809 };
811 usbmisc: usbmisc@02184800 {
812 #index-cells = <1>;
813 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
814 reg = <0x02184800 0x200>;
815 clocks = <&clks IMX6SX_CLK_USBOH3>;
816 };
818 fec1: ethernet@02188000 {
819 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
820 reg = <0x02188000 0x4000>;
821 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&clks IMX6SX_CLK_ENET>,
824 <&clks IMX6SX_CLK_ENET_AHB>,
825 <&clks IMX6SX_CLK_ENET_PTP>,
826 <&clks IMX6SX_CLK_ENET_REF>,
827 <&clks IMX6SX_CLK_ENET_PTP>;
828 clock-names = "ipg", "ahb", "ptp",
829 "enet_clk_ref", "enet_out";
830 fsl,num-tx-queues=<3>;
831 fsl,num-rx-queues=<3>;
832 status = "disabled";
833 };
835 mlb: mlb@0218c000 {
836 reg = <0x0218c000 0x4000>;
837 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
838 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
839 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&clks IMX6SX_CLK_MLB>;
841 status = "disabled";
842 };
844 usdhc1: usdhc@02190000 {
845 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
846 reg = <0x02190000 0x4000>;
847 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&clks IMX6SX_CLK_USDHC1>,
849 <&clks IMX6SX_CLK_USDHC1>,
850 <&clks IMX6SX_CLK_USDHC1>;
851 clock-names = "ipg", "ahb", "per";
852 bus-width = <4>;
853 status = "disabled";
854 };
856 usdhc2: usdhc@02194000 {
857 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
858 reg = <0x02194000 0x4000>;
859 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
860 clocks = <&clks IMX6SX_CLK_USDHC2>,
861 <&clks IMX6SX_CLK_USDHC2>,
862 <&clks IMX6SX_CLK_USDHC2>;
863 clock-names = "ipg", "ahb", "per";
864 bus-width = <4>;
865 status = "disabled";
866 };
868 usdhc3: usdhc@02198000 {
869 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
870 reg = <0x02198000 0x4000>;
871 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&clks IMX6SX_CLK_USDHC3>,
873 <&clks IMX6SX_CLK_USDHC3>,
874 <&clks IMX6SX_CLK_USDHC3>;
875 clock-names = "ipg", "ahb", "per";
876 bus-width = <4>;
877 status = "disabled";
878 };
880 usdhc4: usdhc@0219c000 {
881 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
882 reg = <0x0219c000 0x4000>;
883 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&clks IMX6SX_CLK_USDHC4>,
885 <&clks IMX6SX_CLK_USDHC4>,
886 <&clks IMX6SX_CLK_USDHC4>;
887 clock-names = "ipg", "ahb", "per";
888 bus-width = <4>;
889 status = "disabled";
890 };
892 i2c1: i2c@021a0000 {
893 #address-cells = <1>;
894 #size-cells = <0>;
895 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
896 reg = <0x021a0000 0x4000>;
897 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&clks IMX6SX_CLK_I2C1>;
899 status = "disabled";
900 };
902 i2c2: i2c@021a4000 {
903 #address-cells = <1>;
904 #size-cells = <0>;
905 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
906 reg = <0x021a4000 0x4000>;
907 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
908 clocks = <&clks IMX6SX_CLK_I2C2>;
909 status = "disabled";
910 };
912 i2c3: i2c@021a8000 {
913 #address-cells = <1>;
914 #size-cells = <0>;
915 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
916 reg = <0x021a8000 0x4000>;
917 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&clks IMX6SX_CLK_I2C3>;
919 status = "disabled";
920 };
922 mmdc: mmdc@021b0000 {
923 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
924 reg = <0x021b0000 0x4000>;
925 };
927 fec2: ethernet@021b4000 {
928 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
929 reg = <0x021b4000 0x4000>;
930 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&clks IMX6SX_CLK_ENET>,
933 <&clks IMX6SX_CLK_ENET_AHB>,
934 <&clks IMX6SX_CLK_ENET_PTP>,
935 <&clks IMX6SX_CLK_ENET2_REF_125M>,
936 <&clks IMX6SX_CLK_ENET_PTP>;
937 clock-names = "ipg", "ahb", "ptp",
938 "enet_clk_ref", "enet_out";
939 status = "disabled";
940 };
942 weim: weim@021b8000 {
943 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
944 reg = <0x021b8000 0x4000>;
945 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
947 };
949 ocotp: ocotp@021bc000 {
950 compatible = "fsl,imx6sx-ocotp", "syscon";
951 reg = <0x021bc000 0x4000>;
952 clocks = <&clks IMX6SX_CLK_OCOTP>;
953 };
955 sai1: sai@021d4000 {
956 compatible = "fsl,imx6sx-sai";
957 reg = <0x021d4000 0x4000>;
958 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
960 <&clks IMX6SX_CLK_SAI1>,
961 <&clks 0>, <&clks 0>;
962 clock-names = "bus", "mclk1", "mclk2", "mclk3";
963 dma-names = "rx", "tx";
964 dmas = <&sdma 31 23 0>, <&sdma 32 23 0>;
965 dma-source = <&gpr 0 15 0 16>;
966 status = "disabled";
967 };
969 audmux: audmux@021d8000 {
970 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
971 reg = <0x021d8000 0x4000>;
972 status = "disabled";
973 };
975 sai2: sai@021dc000 {
976 compatible = "fsl,imx6sx-sai";
977 reg = <0x021dc000 0x4000>;
978 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
979 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
980 <&clks IMX6SX_CLK_SAI2>,
981 <&clks 0>, <&clks 0>;
982 clock-names = "bus", "mclk1", "mclk2", "mclk3";
983 dma-names = "rx", "tx";
984 dmas = <&sdma 33 23 0>, <&sdma 34 23 0>;
985 dma-source = <&gpr 0 17 0 18>;
986 status = "disabled";
987 };
989 qspi1: qspi@021e0000 {
990 #address-cells = <1>;
991 #size-cells = <0>;
992 compatible = "fsl,imx6sx-qspi";
993 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
994 reg-names = "QuadSPI", "QuadSPI-memory";
995 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&clks IMX6SX_CLK_QSPI1>,
997 <&clks IMX6SX_CLK_QSPI1>;
998 clock-names = "qspi_en", "qspi";
999 status = "disabled";
1000 };
1002 qspi2: qspi@021e4000 {
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005 compatible = "fsl,imx6sx-qspi";
1006 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1007 reg-names = "QuadSPI", "QuadSPI-memory";
1008 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&clks IMX6SX_CLK_QSPI2>,
1010 <&clks IMX6SX_CLK_QSPI2>;
1011 clock-names = "qspi_en", "qspi";
1012 status = "disabled";
1013 };
1015 uart2: serial@021e8000 {
1016 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1017 reg = <0x021e8000 0x4000>;
1018 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1020 <&clks IMX6SX_CLK_UART_SERIAL>;
1021 clock-names = "ipg", "per";
1022 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1023 dma-names = "rx", "tx";
1024 status = "disabled";
1025 };
1027 uart3: serial@021ec000 {
1028 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1029 reg = <0x021ec000 0x4000>;
1030 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1032 <&clks IMX6SX_CLK_UART_SERIAL>;
1033 clock-names = "ipg", "per";
1034 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1035 dma-names = "rx", "tx";
1036 status = "disabled";
1037 };
1039 uart4: serial@021f0000 {
1040 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1041 reg = <0x021f0000 0x4000>;
1042 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1043 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1044 <&clks IMX6SX_CLK_UART_SERIAL>;
1045 clock-names = "ipg", "per";
1046 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1047 dma-names = "rx", "tx";
1048 status = "disabled";
1049 };
1051 uart5: serial@021f4000 {
1052 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1053 reg = <0x021f4000 0x4000>;
1054 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1055 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1056 <&clks IMX6SX_CLK_UART_SERIAL>;
1057 clock-names = "ipg", "per";
1058 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1059 dma-names = "rx", "tx";
1060 status = "disabled";
1061 };
1063 i2c4: i2c@021f8000 {
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1066 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1067 reg = <0x021f8000 0x4000>;
1068 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1069 clocks = <&clks IMX6SX_CLK_I2C4>;
1070 status = "disabled";
1071 };
1072 };
1074 aips3: aips-bus@02200000 {
1075 compatible = "fsl,aips-bus", "simple-bus";
1076 #address-cells = <1>;
1077 #size-cells = <1>;
1078 reg = <0x02200000 0x100000>;
1079 ranges;
1081 spba-bus@02200000 {
1082 compatible = "fsl,spba-bus", "simple-bus";
1083 #address-cells = <1>;
1084 #size-cells = <1>;
1085 reg = <0x02240000 0x40000>;
1086 ranges;
1088 csi1: csi@02214000 {
1089 reg = <0x02214000 0x4000>;
1090 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1092 <&clks IMX6SX_CLK_CSI>,
1093 <&clks IMX6SX_CLK_DCIC1>;
1094 clock-names = "disp-axi", "csi_mclk", "dcic";
1095 status = "disabled";
1096 };
1098 pxp: pxp@02218000 {
1099 reg = <0x02218000 0x4000>;
1100 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1101 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1102 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1103 clock-names = "pxp-axi", "disp-axi";
1104 status = "disabled";
1105 };
1107 csi2: csi@0221c000 {
1108 reg = <0x0221c000 0x4000>;
1109 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1110 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1111 <&clks IMX6SX_CLK_CSI>,
1112 <&clks IMX6SX_CLK_DCIC2>;
1113 clock-names = "disp-axi", "csi_mclk", "dcic";
1114 status = "disabled";
1115 };
1117 lcdif1: lcdif@02220000 {
1118 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1119 reg = <0x02220000 0x4000>;
1120 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1122 <&clks IMX6SX_CLK_LCDIF_APB>,
1123 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1124 clock-names = "pix", "axi", "disp_axi";
1125 status = "disabled";
1126 };
1128 lcdif2: lcdif@02224000 {
1129 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1130 reg = <0x02224000 0x4000>;
1131 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1132 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1133 <&clks IMX6SX_CLK_LCDIF_APB>,
1134 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1135 clock-names = "pix", "axi", "disp_axi";
1136 status = "disabled";
1137 };
1139 vadc: vadc@02228000 {
1140 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1141 reg-names = "vadc-vafe", "vadc-vdec";
1142 clocks = <&clks IMX6SX_CLK_VADC>,
1143 <&clks IMX6SX_CLK_CSI>;
1144 clock-names = "vadc", "csi";
1145 status = "disabled";
1146 };
1147 };
1149 adc1: adc@02280000 {
1150 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1151 reg = <0x02280000 0x4000>;
1152 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1153 clocks = <&clks IMX6SX_CLK_IPG>;
1154 clock-names = "adc";
1155 status = "disabled";
1156 };
1158 adc2: adc@02284000 {
1159 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1160 reg = <0x02284000 0x4000>;
1161 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&clks IMX6SX_CLK_IPG>;
1163 clock-names = "adc";
1164 status = "disabled";
1165 };
1167 wdog3: wdog@02288000 {
1168 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1169 reg = <0x02288000 0x4000>;
1170 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1171 clocks = <&clks IMX6SX_CLK_DUMMY>;
1172 status = "disabled";
1173 };
1175 ecspi5: ecspi@0228c000 {
1176 #address-cells = <1>;
1177 #size-cells = <0>;
1178 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1179 reg = <0x0228c000 0x4000>;
1180 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1181 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1182 <&clks IMX6SX_CLK_ECSPI5>;
1183 clock-names = "ipg", "per";
1184 status = "disabled";
1185 };
1187 uart6: serial@022a0000 {
1188 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1189 reg = <0x022a0000 0x4000>;
1190 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1191 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1192 <&clks IMX6SX_CLK_UART_SERIAL>;
1193 clock-names = "ipg", "per";
1194 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1195 dma-names = "rx", "tx";
1196 status = "disabled";
1197 };
1199 pwm5: pwm@022a4000 {
1200 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1201 reg = <0x022a4000 0x4000>;
1202 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1203 clocks = <&clks IMX6SX_CLK_PWM5>,
1204 <&clks IMX6SX_CLK_PWM5>;
1205 clock-names = "ipg", "per";
1206 #pwm-cells = <2>;
1207 };
1209 pwm6: pwm@022a8000 {
1210 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1211 reg = <0x022a8000 0x4000>;
1212 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1213 clocks = <&clks IMX6SX_CLK_PWM6>,
1214 <&clks IMX6SX_CLK_PWM6>;
1215 clock-names = "ipg", "per";
1216 #pwm-cells = <2>;
1217 };
1219 pwm7: pwm@022ac000 {
1220 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1221 reg = <0x022ac000 0x4000>;
1222 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1223 clocks = <&clks IMX6SX_CLK_PWM7>,
1224 <&clks IMX6SX_CLK_PWM7>;
1225 clock-names = "ipg", "per";
1226 #pwm-cells = <2>;
1227 };
1229 pwm8: pwm@0022b0000 {
1230 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1231 reg = <0x0022b0000 0x4000>;
1232 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1233 clocks = <&clks IMX6SX_CLK_PWM8>,
1234 <&clks IMX6SX_CLK_PWM8>;
1235 clock-names = "ipg", "per";
1236 #pwm-cells = <2>;
1237 };
1238 };
1240 pcie: pcie@0x08000000 {
1241 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1242 reg = <0x08ffc000 0x4000>; /* DBI */
1243 #address-cells = <3>;
1244 #size-cells = <2>;
1245 device_type = "pci";
1246 /* configuration space */
1247 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1248 /* downstream I/O */
1249 0x81000000 0 0 0x08f80000 0 0x00010000
1250 /* non-prefetchable memory */
1251 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1252 num-lanes = <1>;
1253 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1254 clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1255 <&clks IMX6SX_CLK_PCIE_AXI>,
1256 <&clks IMX6SX_CLK_LVDS1_OUT>,
1257 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1258 clock-names = "pcie_ref_125m", "pcie_axi",
1259 "lvds_gate", "display_axi";
1260 status = "disabled";
1261 };
1262 };
1263 };