arch/arm/boot/dts/mt6589.dtsi

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Matthias Brugger <matthias.bgg@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include "skeleton.dtsi"
  19
  20 / {
  21         compatible = "mediatek,mt6589";
  22         interrupt-parent = <&sysirq>;
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a7";
  31                         reg = <0x0>;
  32                 };
  33                 cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a7";
  36                         reg = <0x1>;
  37                 };
  38                 cpu@2 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a7";
  41                         reg = <0x2>;
  42                 };
  43                 cpu@3 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a7";
  46                         reg = <0x3>;
  47                 };
  48
  49         };
  50
  51         clocks {
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 compatible = "simple-bus";
  55                 ranges;
  56
  57                 system_clk: dummy13m {
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <13000000>;
  60                         #clock-cells = <0>;
  61                 };
  62
  63                 rtc_clk: dummy32k {
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <32000>;
  66                         #clock-cells = <0>;
  67                 };
  68
  69                 uart_clk: dummy26m {
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <26000000>;
  72                         #clock-cells = <0>;
  73                 };
  74         };
  75
  76         soc {
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 compatible = "simple-bus";
  80                 ranges;
  81
  82                 timer: timer@10008000 {
  83                         compatible = "mediatek,mt6577-timer";
  84                         reg = <0x10008000 0x80>;
  85                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
  86                         clocks = <&system_clk>, <&rtc_clk>;
  87                         clock-names = "system-clk", "rtc-clk";
  88                 };
  89
  90                 sysirq: interrupt-controller@10200100 {
  91                         compatible = "mediatek,mt6589-sysirq",
  92                                      "mediatek,mt6577-sysirq";
  93                         interrupt-controller;
  94                         #interrupt-cells = <3>;
  95                         interrupt-parent = <&gic>;
  96                         reg = <0x10200100 0x1c>;
  97                 };
  98
  99                 gic: interrupt-controller@10211000 {
 100                         compatible = "arm,cortex-a7-gic";
 101                         interrupt-controller;
 102                         #interrupt-cells = <3>;
 103                         interrupt-parent = <&gic>;
 104                         reg = <0x10211000 0x1000>,
 105                               <0x10212000 0x1000>,
 106                               <0x10214000 0x2000>,
 107                               <0x10216000 0x2000>;
 108                 };
 109
 110                 uart0: serial@11006000 {
 111                         compatible = "mediatek,mt6577-uart";
 112                         reg = <0x11006000 0x400>;
 113                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 114                         clocks = <&uart_clk>;
 115                         status = "disabled";
 116                 };
 117
 118                 uart1: serial@11007000 {
 119                         compatible = "mediatek,mt6577-uart";
 120                         reg = <0x11007000 0x400>;
 121                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 122                         clocks = <&uart_clk>;
 123                         status = "disabled";
 124                 };
 125
 126                 uart2: serial@11008000 {
 127                         compatible = "mediatek,mt6577-uart";
 128                         reg = <0x11008000 0x400>;
 129                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 130                         clocks = <&uart_clk>;
 131                         status = "disabled";
 132                 };
 133
 134                 uart3: serial@11009000 {
 135                         compatible = "mediatek,mt6577-uart";
 136                         reg = <0x11009000 0x400>;
 137                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 138                         clocks = <&uart_clk>;
 139                         status = "disabled";
 140                 };
 141
 142                 wdt: watchdog@010000000 {
 143                         compatible = "mediatek,mt6589-wdt";
 144                         reg = <0x10000000 0x44>;
 145                 };
 146         };
 147 };